Analog chips, compared to general chip products, typically boast longer lifecycles and broader applications. With a diverse range of product categories and applications spanning consumer electronics, telecommunications, industrial, and automotive terminal markets, analog chips demonstrate industry resilience by catering to various market demands even during semiconductor downturns, as was evident during the inventory adjustments in 2022.

This might be why analog chip designers seem to invest more in their designs, right? Designers often express how exhausting the process can be!

For instance, while digital chip design emphasizes speed and cost-effectiveness and is mainly completed at an abstract level without delving into the details of gate/transistor-level placement and routing, analog chip design prioritizes aspects like high signal-to-noise ratio, low distortion, low power consumption, and stability. Designers spend their days sketching colorful MOS transistors on circuit diagrams, deciding on the number of components to use, the arrangement methods, and how to minimize chip volume, maximize performance, and save costs. It involves addressing the individual characteristics of each circuit, down to the size and details of each transistor, making both design and verification more complex.

There aren't many renowned analog chip design companies globally. Internationally, major players include Texas Instruments, Analog Devices, and Infineon, while domestically, there are companies like Avia, Silan Microelectronics, and Sanan Microelectronics. VBSemiConductor, with 20 years in the industry, is among them.

Chip design is a process that integrates and organizes highly specialized knowledge. The requirements for equipment and software tools used are also extremely high, such as EDA tools. Today, we'll primarily explore the analog chip design journey from the perspective of computational tasks of EDA tools.

As for perspectives beyond computational tasks, such as scheduling/management/data/collaboration/CAD, we'll leave that for another chapter.

First, let's get a brief overview of the general process of analog chip design.

The early stages essentially involve numerical calculations, mostly multi-corner and Monte Carlo tasks. These tasks require high peak computing power and moderate storage.

Now, what are multi-corner and Monte Carlo? Let's briefly explain. These are two different methods for estimating circuit performance and process errors. The tasks within these methods are independent, with no data correlation between individual tasks, making them suitable for distributed parallel computing.

Multi-corner involves fixing the upper and lower limits of parameters such as component resistance, temperature, and voltage, then arranging each parameter's extreme values in combinations. Each combination constitutes an independent task. One such combination is called a corner, and all combinations form multi-corner.

It's like going to a bubble tea shop, but this one's a bit special. They offer extreme services—you can only choose sugar-free or the sweetest option, either scalding hot or icy cold, with or without toppings.

You're basically just combining these options to get your bubble tea. For example, extra sweet, scalding hot, with extra toppings. The next time, you might go for a different combination, sugar-free, extra cold, no toppings. When you've tried all the combinations, that's multi-corner.

But if you don't like the bubble tea from this shop, you head to a new one, which allows complete customization according to your preferences.

You could choose 5% sweetness, slightly cold, no toppings, or get a bit creative with 5.5% sweetness, half cold, half hot, with half a scoop of pearls, and so on.

This results in countless combinations of bubble tea, which is akin to Monte Carlo—endless permutations within the upper and lower limits. The more combinations you try, the more accurately you can estimate errors caused by process deviations and predict the actual yield range of finished products. Of course, this also exponentially increases the computational load.

The mid-stage involves layout design, transforming the circuit schematic into a layout pattern containing actual layout and wiring planning content. Layout verification compares the drawn layout with the schematic to ensure their topological connections are consistent and checks whether the layout complies with foundry design processes.

Layout design and verification are like playing a game of "spot the difference" between the layout and schematic. If there are issues, you redo it until it's right. You check, correct, and repeat the process. Layout checks are extensive, but fortunately, layouts can be divided into modules, with each module being checked independently. You make your changes and resubmit for the next round without affecting ongoing checks.

Dividing the layout and properly allocating resources for checks enables layout designers to avoid waiting for a single computer to check each part of a large layout one by one, allowing multiple computers to simultaneously check different parts of the same large layout and automatically consolidate the results. This speeds up the task completion.

The post-simulation stage essentially involves numerical calculations, as various parasitic parameters of components are introduced, making it the most computationally intensive of the three stages.

For example, in RF chips, the crown jewel of analog circuits, often considered the "peak of Mount Hua" in chip design, the physical shape of RF circuits and the distribution of surrounding media significantly affect RF signal transmission. Therefore, the design process is extremely challenging. Extensive simulation testing is required in the early stages. Additionally, to ensure high-frequency performance, material selection is crucial, such as gallium arsenide and gallium nitride.

Moreover, RF requires electromagnetic field simulation, necessitating three-dimensional space vector calculations. If layout is like slicing a two-dimensional world into pieces, RF is like cutting a three-dimensional space into bits—more challenging and requiring exponentially more computational power.

In summary, regarding analog chip design, from the perspective of computational tasks at different design stages, we can conclude the following:

1. The computational demand of the three stages shows the trend of early-stage < mid-stage < post-stage.

2. Tasks like multi-corner, Monte Carlo, DRC, LVS, etc., are very suitable for parallel computing to enhance task efficiency.

3. For tasks based on single-module inseparability, although distributed processing isn't possible, task efficiency can be improved by using machines with large memory and high CPU frequency.