Practical Design of the Power Management Chain for High-End Medical Robot Data Management Systems: Balancing Data Integrity, Power Density, and Ultimate Reliability
Medical Robot Data Management System Power Chain Topology
Medical Robot Data Management System - Overall Power Chain Topology
graph LR
%% Main Power Input & Distribution
subgraph "Input Power & Redundancy"
AC_IN["AC Mains Input 230VAC/50Hz"] --> MEDICAL_PSU["Medical-Grade PSU IEC 60601-1 Compliant"]
BACKUP_IN["Backup Power Input 24-48VDC"] --> ORING_CONTROLLER["OR-ing Controller"]
MEDICAL_PSU --> ORING_CONTROLLER
ORING_CONTROLLER --> PRIMARY_BUS["Primary Power Bus 12VDC/24VDC"]
end
%% Primary Power Conversion Stages
subgraph "Core Power Conversion & Distribution"
PRIMARY_BUS --> INTERMEDIATE_BUS_CONVERTER["Intermediate Bus Converter 48V to 12V/5V"]
subgraph "High-Current CPU/GPU VRM"
Q_VRM1["VBGM1151N 150V/80A SGT MOSFET"]
Q_VRM2["VBGM1151N 150V/80A SGT MOSFET"]
Q_VRM3["VBGM1151N 150V/80A SGT MOSFET"]
Q_VRM4["VBGM1151N 150V/80A SGT MOSFET"]
end
INTERMEDIATE_BUS_CONVERTER --> Q_VRM1
INTERMEDIATE_BUS_CONVERTER --> Q_VRM2
INTERMEDIATE_BUS_CONVERTER --> Q_VRM3
INTERMEDIATE_BUS_CONVERTER --> Q_VRM4
Q_VRM1 --> CPU_POWER["CPU/GPU Core Power 0.8-1.2V"]
Q_VRM2 --> CPU_POWER
Q_VRM3 --> CPU_POWER
Q_VRM4 --> CPU_POWER
subgraph "Intelligent Load & Hot-Swap Management"
SW_MEMORY["VBC2333 Memory Power Switch"]
SW_STORAGE["VBC2333 Storage Power Switch"]
SW_NETWORK["VBC2333 Network Module Switch"]
SW_FAN_CTRL["VBC2333 Fan Control Switch"]
end
PRIMARY_BUS --> SW_MEMORY
PRIMARY_BUS --> SW_STORAGE
PRIMARY_BUS --> SW_NETWORK
PRIMARY_BUS --> SW_FAN_CTRL
SW_MEMORY --> MEMORY_POWER["DDR Memory Power 1.2V/1.8V"]
SW_STORAGE --> STORAGE_POWER["NVMe/SSD Power 3.3V/5V"]
SW_NETWORK --> NETWORK_POWER["Network Interface Power"]
SW_FAN_CTRL --> FAN_POWER["Cooling Fan Power"]
end
%% System Control & Monitoring
subgraph "System Management & Protection"
SYSTEM_MCU["System Management Controller with PMBus"] --> POWER_SEQUENCER["Power Sequencing IC"]
SYSTEM_MCU --> TEMP_SENSORS["Temperature Sensors"]
SYSTEM_MCU --> CURRENT_MONITORS["Current Monitors"]
SYSTEM_MCU --> VOLTAGE_MONITORS["Voltage Monitors"]
subgraph "Signal Conditioning & Logic Control"
CTRL_ENABLE["VBK362K Enable Signal Control"]
CTRL_STATUS["VBK362K Status LED Control"]
CTRL_RESET["VBK362K System Reset Control"]
CTRL_LEVEL_SHIFT["VBK362K I2C Level Shifter"]
end
SYSTEM_MCU --> CTRL_ENABLE
SYSTEM_MCU --> CTRL_STATUS
SYSTEM_MCU --> CTRL_RESET
SYSTEM_MCU --> CTRL_LEVEL_SHIFT
CTRL_ENABLE --> Q_VRM1
CTRL_STATUS --> STATUS_LEDS["Status Indicators"]
CTRL_RESET --> RESET_CIRCUIT["System Reset Circuit"]
CTRL_LEVEL_SHIFT --> PMBUS["PMBus Communication"]
subgraph "Protection Circuits"
OVP_CIRCUIT["Over-Voltage Protection"]
OCP_CIRCUIT["Over-Current Protection"]
OTP_CIRCUIT["Over-Temperature Protection"]
UVP_CIRCUIT["Under-Voltage Protection"]
end
VOLTAGE_MONITORS --> OVP_CIRCUIT
CURRENT_MONITORS --> OCP_CIRCUIT
TEMP_SENSORS --> OTP_CIRCUIT
VOLTAGE_MONITORS --> UVP_CIRCUIT
OVP_CIRCUIT --> SYSTEM_MCU
OCP_CIRCUIT --> SYSTEM_MCU
OTP_CIRCUIT --> SYSTEM_MCU
UVP_CIRCUIT --> SYSTEM_MCU
end
%% Thermal Management System
subgraph "Multi-Zone Thermal Management"
subgraph "Zone 1: High Heat Flux"
COOLING_CPU["CPU/GPU Heatsink with Heat Pipes"]
COOLING_VRM["VRM Heatsink Forced Air Cooling"]
end
subgraph "Zone 2: Medium Power"
COOLING_SWITCHES["PCB Thermal Vias + Copper Pour"]
COOLING_CONVERTERS["Passive Heatsinks"]
end
subgraph "Zone 3: Low Power/Signal"
COOLING_LOGIC["Natural Convection PCB Conduction"]
end
COOLING_CPU --> CPU_POWER
COOLING_VRM --> Q_VRM1
COOLING_SWITCHES --> SW_MEMORY
COOLING_CONVERTERS --> INTERMEDIATE_BUS_CONVERTER
COOLING_LOGIC --> CTRL_ENABLE
TEMP_SENSORS --> THERMAL_CONTROLLER["Thermal Management Controller"]
THERMAL_CONTROLLER --> FAN_SPEED_CONTROL["Fan Speed PWM"]
THERMAL_CONTROLLER --> ALARM_SYSTEM["Thermal Alarm System"]
FAN_SPEED_CONTROL --> FAN_POWER
end
%% Data Integrity & Communication
subgraph "Data Integrity & System Communication"
POWER_INTEGRITY["Power Integrity Network Low-ESR/ESL Capacitors"] --> CPU_POWER
POWER_INTEGRITY --> MEMORY_POWER
POWER_INTEGRITY --> STORAGE_POWER
EMC_FILTERS["EMI/EMC Filters"] --> NETWORK_POWER
EMC_FILTERS --> STORAGE_POWER
SYSTEM_MCU --> NETWORK_INTERFACE["Ethernet Network"]
SYSTEM_MCU --> STORAGE_CONTROLLER["Storage Controller"]
SYSTEM_MCU --> DIAGNOSTIC_PORT["Diagnostic & Service Port"]
end
%% Style Definitions
style Q_VRM1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
style SW_MEMORY fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style CTRL_ENABLE fill:#fff3e0,stroke:#ff9800,stroke-width:2px
style SYSTEM_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px
As high-end medical robotic systems (e.g., surgical, diagnostic, logistics) evolve towards greater data processing loads, higher network bandwidth, and continuous uptime requirements, their internal data management servers and storage arrays are no longer simple computing units. Instead, their power delivery networks (PDNs) are the core determinants of system stability, data integrity, and operational availability. A meticulously designed power chain is the physical foundation for these critical systems to achieve flawless data processing, high-efficiency power conversion, and fault-tolerant operation within the constrained, sensitive environments of medical facilities. However, building such a chain presents multi-dimensional challenges: How to ensure absolutely clean power for sensitive processing and storage chips? How to guarantee the long-term reliability of power components in 24/7 operating conditions with strict thermal and acoustic constraints? How to seamlessly integrate intelligent power sequencing, fault monitoring, and hot-swap capabilities? The answers lie within every engineering detail, from the selection of key components to system-level integration. I. Three Dimensions for Core Power Component Selection: Coordinated Consideration of Voltage, Noise, and Integration 1. Primary CPU/GPU VRM & Intermediate Bus Converter MOSFET: The Engine of Computational Power The key device is the VBGM1151N (150V/80A/TO-220, SGT MOSFET), whose selection requires deep technical analysis. Voltage Stress & Noise Sensitivity Analysis: In a data management system, the primary power stages (e.g., 48V to 12V/5V Intermediate Bus Converters, or 12V to sub-1V CPU VRMs) require switches with low gate charge (Qg) and excellent reverse recovery characteristics to minimize switching noise. The 150V rating provides ample margin for 48V bus applications, including transients. The Shielded Gate Trench (SGT) technology offers a favorable balance of low RDS(on) and low Qg, crucial for high-frequency (>500kHz) synchronous buck converters powering FPGAs and GPUs, where switching noise can directly impact signal integrity. Dynamic Characteristics and Loss Optimization: The ultra-low RDS(on) (10.4mΩ @10V) directly minimizes conduction loss during high-current delivery to multi-core processors. The SGT structure inherently reduces gate-drain capacitance (Cgd), leading to faster switching transitions and lower switching loss, which is vital for efficiency at high frequency. This also reduces the generation of high-frequency noise that could couple into data lines. Thermal Design Relevance: The TO-220 package offers a proven path for heatsinking. In a forced-air-cooled server chassis, its thermal performance must be carefully modeled: Tj = Tc + (I² RDS(on)) Rθjc. The low RDS(on) is the first line of defense against heat generation in a densely packed system. 2. Intelligent Load Point & Hot-Swap Power Switch MOSFET: The Guardian of System Stability The key device is the VBC2333 (-30V/-5A/TSSOP8, Trench MOSFET), enabling precise, intelligent power control. High-Density Power Distribution & Sequencing: Modern medical data systems require sophisticated power sequencing for various boards (CPU, memory, storage, network). This P-channel MOSFET, with its remarkably low RDS(on) (40mΩ @10V), is ideal as a high-side load switch for 12V or 5V rails. Its compact TSSOP8 package allows for high-density placement on management controller boards. It enables features like soft-start (inrush current control), sequential power-up/down, and individual rail enable/disable for power gating and fault isolation. Reliability and Protection: The low RDS(on) ensures minimal voltage drop and heat generation when supplying power to critical sub-systems. This is essential for maintaining power integrity margins for ASICs and memory. Integrated into hot-swap controllers, it can provide smooth, controlled insertion of storage or expansion modules without causing bus glitches. PCB Layout and Control: The small package saves valuable real estate but demands careful thermal management via PCB copper pours. Its gate can be easily driven by a dedicated power sequencer/controller IC, allowing for programmable timing and fault response (e.g., fast shutdown on overcurrent). 3. Signal Conditioning & Auxiliary Power Control MOSFET: The Enabler of Precision Management The key device is the VBK362K (Dual 60V/0.3A/SC70-6, Trench MOSFET), providing highly integrated control for auxiliary functions. Low-Level Control and Interface Logic: This dual N-channel MOSFET pair is designed for space-constrained, low-power control applications. Typical uses include: controlling enable signals for other power stages, driving LEDs for status indication, level-shifting for management bus signals (I2C, PMBus), and implementing simple logic functions or reset circuits. Its ultra-small SC70-6 package is perfect for integration near connectors or microcontrollers on system management boards. Noise Immunity and Leakage Current: For medical systems, minimizing leakage current and ensuring clean digital signals are paramount. The device's specified Vth and low gate leakage are important for robust operation in noisy digital environments. The dual independent channels offer design flexibility and further component count reduction. System Monitoring Integration: These switches can be used to selectively connect monitoring points (e.g., temperature sensor pull-ups, diagnostic signals) to the management microcontroller, aiding in comprehensive system health monitoring without adding constant load. II. System Integration Engineering Implementation 1. Multi-Zone Thermal and Acoustic Management A tiered thermal strategy is essential in acoustically-sensitive medical environments. Zone 1 (High Heat Flux): Components like the VBGM1151N in CPU VRMs use dedicated heatsinks with heat pipes or vapor chambers, coupled with speed-controlled fans. The goal is to maintain junction temperature while minimizing fan acoustic noise through efficient thermal design. Zone 2 (Medium Power): POL (Point-of-Load) converters and switches like the VBC2333 rely on optimized PCB layout with thick copper layers, thermal vias, and strategic airflow from system fans. Zone 3 (Low Power/Signal): Devices like the VBK362K depend entirely on conduction through the PCB to the board's ground plane and the overall system airflow. 2. Power Integrity (PI) and Electromagnetic Compatibility (EMC) Low-Noise PDN Design: Use multi-phase VRM topologies with the VBGM1151N to reduce input and output current ripple. Employ high-quality, low-ESR/ESL ceramic capacitors at the switch nodes. Implement careful grounding and shielding to contain high-frequency switching noise from affecting sensitive data acquisition or communication circuits within the robot. Radiated Emissions Control: Keep high di/dt loops (switching nodes) extremely small. Use shielded compartments within the chassis for switching power supplies. Filter all external cable interfaces (Ethernet, storage links) with common-mode chokes and ferrites. Redundancy and Fault Tolerance: For critical power rails, implement N+1 redundant power supplies with OR-ing MOSFETs (for which low RDS(on) devices like VBFB1101N could be considered). All power management controllers should have watchdog timers and communicate fault status via IPMI or similar protocols. 3. Reliability and Safety Enhancement Design Electrical Stress Protection: Ensure proper snubber networks or RC damping on switch nodes to prevent voltage overshoot. Implement robust overcurrent protection (OCP) and overtemperature protection (OTP) for all power stages, with hardware-based fast-trip thresholds. Predictive Health Monitoring (PHM): Leverage system management controllers to monitor trends in MOSFET junction temperature (via associated sensors), input/output voltages, and load currents. Predictive algorithms can flag potential degradation (e.g., increasing RDS(on)) before failure, enabling planned maintenance—a critical feature for medical equipment uptime. Safety Compliance: The overall system must comply with relevant medical safety standards (e.g., IEC 60601-1), requiring proper creepage/clearance, insulation, and leakage current control, which influences PCB layout around power components. III. Performance Verification and Testing Protocol 1. Key Test Items and Standards Power Integrity Test: Measure voltage ripple and transient response on critical rails (CPU Vcore, memory VDDQ) under worst-case load steps using a high-bandwidth oscilloscope. Thermal and Acoustic Profile Test: Map component temperatures and system noise levels under various computational loads (idle, benchmark, sustained processing) in an ambient-controlled chamber. Electromagnetic Emissions Test: Conduct according to CISPR 32/EN 55032 (Class B for medical environments) to ensure no interference with other sensitive medical devices. Reliability and Endurance Test: Perform extended burn-in tests (e.g., 1000+ hours) at elevated temperature to validate MTBF calculations and identify early-life failures. Fault Injection and Recovery Test: Verify the response of power sequencing, OCP, OTP, and redundant supply switchover mechanisms. 2. Design Verification Example Test data from a medical data storage controller unit (Primary input: 12VDC, Ambient: 25°C) shows: The 12V to 1.8V POL converter (using devices like VBGM1151N in sync rectifier role) achieved peak efficiency of 94%. Key Point Temperature Rise: During a full data-write stress test, the primary switch MOSFET case temperature stabilized at 68°C with targeted airflow. Output voltage deviation during a 50% load step was contained within ±2%, meeting the stringent requirements of high-speed memory interfaces. The system passed 72-hour continuous operation with zero data corruption or uncorrectable errors. IV. Solution Scalability 1. Adjustments for Different System Tiers Compact Surgical Controller (<10U): Emphasize ultra-high power density. May use chip-scale packaged MOSFETs or integrated power stages for POL, with VBC2333 and VBK362K for board-level management. Hospital-Core Data Server Rack: Prioritize redundancy and serviceability. Use higher-current devices in TO-263 or similar packages for primary conversion, with robust hot-swap circuitry and comprehensive PMBus monitoring. Cloud-Based Medical Analysis Cluster: Focus on peak efficiency (PUE). May employ 48V direct-to-chip architectures, where 100V-rated devices like VBFB1101N become relevant for high-efficiency, high-power intermediate conversion. 2. Integration of Cutting-Edge Technologies Intelligent Power Management (IPM): Deep integration of PMBus with system software for dynamic power capping, workload-aware efficiency optimization, and granular PHM. Gallium Nitride (GaN) Technology Roadmap: Phase 1 (Current): High-frequency (>1MHz) POL converters using GaN HEMTs for the smallest form-factor cards, coexisting with silicon MOSFETs (VBGM1151N, VBC2333) in other stages. Phase 2 (Next 2-3 years): Adoption of GaN in 48V-12V IBCs, significantly increasing rack-level power density and efficiency. Phase 3 (Future): Exploration of integrated GaN-based solutions for complete on-board power, driven by the need for AI acceleration in medical data processing. Liquid Cooling Integration: For the highest-performance computing nodes, direct-to-chip or immersion cooling will become necessary, fundamentally changing the thermal design approach for power components like the VBGM1151N, requiring compatible packaging and materials. Conclusion The power chain design for high-end medical robot data management systems is a critical engineering discipline balancing relentless demands for data integrity, availability, and density within strict environmental and safety constraints. The tiered optimization scheme proposed—employing high-efficiency, low-noise SGT/SJ MOSFETs for core computation power, utilizing ultra-low RDS(on) integrated switches for intelligent power distribution, and deploying miniature dual MOSFETs for precision management logic—provides a robust, scalable foundation. As medical robotics generate and process ever more critical data, their supporting infrastructure's power design will trend towards greater intelligence, transparency, and resilience. It is recommended that engineers adhere to the stringent rigor of medical device development processes while leveraging this framework, proactively planning for the integration of wide-bandgap semiconductors and advanced cooling technologies. Ultimately, excellent power design in this field remains largely invisible, operating silently and reliably in the background. Yet, it is the fundamental enabler that ensures the flawless, uninterrupted data flow upon which modern precision medicine increasingly depends, safeguarding both patient outcomes and valuable medical data. This is the paramount value of engineering excellence in the digital healthcare revolution.
Detailed Power Topology Diagrams
Primary Power Conversion & CPU/GPU VRM Detail
graph LR
subgraph "Intermediate Bus Converter Stage"
A["48V DC Input"] --> B["EMI Filter"]
B --> C["Synchronous Buck Converter"]
subgraph "Primary Switching MOSFETs"
D["VBGM1151N High-Side Switch"]
E["VBGM1151N Low-Side Switch"]
end
C --> D
C --> E
D --> F["12V Intermediate Bus"]
E --> GND1[Primary Ground]
F --> H["Output Filter Low-ESL Capacitors"]
H --> I["12V/5V Rails to POL Converters"]
end
subgraph "Multi-Phase CPU/GPU VRM"
I --> J["Multi-Phase Buck Controller"]
subgraph "Phase 1"
K1["VBGM1151N High-Side"]
K2["VBGM1151N Low-Side"]
end
subgraph "Phase 2"
L1["VBGM1151N High-Side"]
L2["VBGM1151N Low-Side"]
end
subgraph "Phase 3"
M1["VBGM1151N High-Side"]
M2["VBGM1151N Low-Side"]
end
subgraph "Phase 4"
N1["VBGM1151N High-Side"]
N2["VBGM1151N Low-Side"]
end
J --> K1
J --> L1
J --> M1
J --> N1
K1 --> O["Inductor Array"]
L1 --> O
M1 --> O
N1 --> O
K2 --> GND2[Power Ground]
L2 --> GND2
M2 --> GND2
N2 --> GND2
O --> P["VRM Output Filter"]
P --> Q["CPU/GPU Vcore 0.8-1.2V @ 100A+"]
R["Current Sensing"] --> J
S["Voltage Feedback"] --> J
end
style D fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
style K1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
Intelligent Load Management & Power Sequencing Detail
graph LR
subgraph "Intelligent Load Switch Channels"
A["12V/5V Input Rail"] --> B["VBC2333 P-MOSFET Hot-Swap Switch"]
B --> C["Soft-Start Circuit"]
C --> D["Current Limit Control"]
D --> E["Output Rail"]
subgraph "Power Sequencing Controller"
F["Sequencer IC"] --> G["Timing Configuration via I2C/PMBus"]
F --> H["Fault Detection Logic"]
F --> I["Enable/Disable Control"]
end
subgraph "Sequenced Power Rails"
J["Rail 1: CPU Vcore (First)"]
K["Rail 2: Memory VDDQ (+10ms)"]
L["Rail 3: Chipset Power (+20ms)"]
M["Rail 4: Storage Power (+30ms)"]
N["Rail 5: Peripherals (+50ms)"]
end
I --> J
I --> K
I --> L
I --> M
I --> N
H --> O["Fault Latch"]
O --> P["Global Power Good"]
O --> Q["Fault Indicator"]
end
subgraph "Signal Control & Interface Logic"
R["System MCU GPIO"] --> S["VBK362K Dual N-MOS Level Shifter"]
S --> T["PMBus Interface to Power ICs"]
U["MCU Control Signals"] --> V["VBK362K Dual N-MOS Enable/Reset Logic"]
V --> W["Power Stage Enables"]
V --> X["System Reset Signals"]
Y["Status Monitoring"] --> Z["VBK362K Dual N-MOS MUX/Demux"]
Z --> AA["LED Drivers"]
Z --> AB["Diagnostic Points"]
end
subgraph "Monitoring & Protection"
AC["Voltage Monitors"] --> AD["Comparator Array"]
AE["Current Monitors"] --> AD
AF["Temperature Sensors"] --> AD
AD --> AG["Fault Decision Logic"]
AG --> AH["Protection Actions: Shutdown, Throttle, Alarm"]
end
style B fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style S fill:#fff3e0,stroke:#ff9800,stroke-width:2px
Thermal Management & Protection Circuit Detail
graph LR
subgraph "Three-Zone Thermal Architecture"
subgraph "Zone 1: High Heat Flux"
A["Active Cooling: Heat Pipes + Vapor Chamber"]
B["Forced Air: Speed-Controlled Fans"]
C["Liquid Cold Plate (Optional Upgrade)"]
end
subgraph "Zone 2: Medium Power"
D["PCB Thermal Design: 2oz Copper + Thermal Vias"]
E["Passive Heatsinks: Aluminum Extrusions"]
F["Strategic Airflow from System Fans"]
end
subgraph "Zone 3: Low Power/Signal"
G["Natural Convection: Component Placement"]
H["PCB Conduction: Ground Plane Thermal Path"]
I["Minimal Heat Generation Design"]
end
A --> J["CPU/GPU Processors"]
B --> K["VRM MOSFETs (VBGM1151N)"]
C --> L["High-Power ASICs"]
D --> M["Load Switches (VBC2333)"]
E --> N["Converter ICs"]
F --> O["Power Inductors"]
G --> P["Control Logic (VBK362K)"]
H --> Q["Interface Circuits"]
I --> R["Sensors & Monitoring"]
end
subgraph "Thermal Monitoring & Control"
S["NTC/PTC Temperature Sensors"] --> T["Thermal Monitoring IC"]
U["Digital Temperature Sensors"] --> T
T --> V["Thermal Management Controller"]
V --> W["Fan PWM Control Algorithm"]
V --> X["Pump Speed Control (Liquid Cooling)"]
V --> Y["Power Throttling Logic"]
V --> Z["Thermal Alarm System"]
W --> AA["Fan Speed Adjustment"]
X --> BB["Coolant Flow Control"]
Y --> CC["Clock Frequency Throttle"]
Y --> DD["Voltage/Frequency Scaling"]
Z --> EE["Visual Alarms"]
Z --> FF["Audible Alerts"]
Z --> GG["Remote Notifications"]
end
subgraph "Electrical Protection Network"
HH["Voltage Transients"] --> II["TVS Diodes + MOVs"]
JJ["Switching Noise"] --> KK["RC Snubber Circuits"]
LL["High-Frequency Ringing"] --> MM["Ferrite Beads + Caps"]
NN["ESD Events"] --> OO["ESD Protection Diodes"]
II --> PP["Protected Power Rails"]
KK --> QQ["Clean Switch Nodes"]
MM --> RR["Stable Control Signals"]
OO --> SS["ESD-Safe Interfaces"]
TT["Current Faults"] --> UU["Fast Comparators"]
VV["Voltage Faults"] --> UU
UU --> WW["Hardware Fault Latch"]
WW --> XX["Immediate Shutdown Bypassing Software"]
end
style K fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
style M fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style P fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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