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Practical Design of the Power Chain for AI-Portable Ultrasound Devices: Balancing Performance, Efficiency, and Miniaturization
AI-Portable Ultrasound Device Power Chain Topology Diagram

AI-Portable Ultrasound Device Power Chain Overall Topology Diagram

graph LR %% Battery & Primary Power Distribution subgraph "Battery & Main Power Management" BAT["Li-ion Battery Pack
14.8V Nominal"] --> BAT_PROT["Battery Protection Circuit"] BAT_PROT --> MAIN_SWITCH["VBGQF1606
Main Power Path Switch"] MAIN_SWITCH --> SYS_PWR["System Power Bus
14.8V"] end %% DC-DC Conversion Stages subgraph "High-Efficiency DC-DC Conversion" SYS_PWR --> BUCK_SW["VBGQF1606
Synchronous Buck Switch"] BUCK_SW --> BUCK_CONV["High-Frequency Buck Converter"] BUCK_CONV --> VCC_5V["5V Rail
Digital/Analog Power"] BUCK_CONV --> VCC_3V3["3.3V Rail
Processor/Logic"] SYS_PWR --> BOOST_SW["VBGQF1606
Boost Switch"] BOOST_SW --> BOOST_CONV["Boost Converter"] BOOST_CONV --> HV_BIAS["±8V Rail
Analog Front-End"] end %% Transducer Interface & Signal Path subgraph "Transducer Transmit/Receive Interface" HV_PULSER["High-Voltage Transmit Pulser"] --> TX_NODE["Transmit Node"] TX_NODE --> PROT_SW["VB165R01
High-Voltage Protection Switch"] PROT_SW --> TRANS_CONN["Transducer Connector"] TRANS_CONN --> TR_SW_NODE["T/R Switch Node"] TR_SW_NODE --> TR_SW["VBI5325
Dual N+P T/R Switch"] TR_SW --> RX_AMP["Low-Noise Receive Amplifier"] RX_AMP --> ADC["High-Resolution ADC"] end %% System Control & Processing subgraph "Control & Signal Processing" MCU["Main Control MCU"] --> PMIC["Power Management IC"] MCU --> AFE_CTRL["Analog Front-End Controller"] MCU --> AI_PROC["AI Imaging Processor"] PMIC --> BUCK_SW PMIC --> BOOST_SW AFE_CTRL --> TR_SW AFE_CTRL --> HV_PULSER end %% Protection & Monitoring subgraph "Protection & Monitoring Circuits" TEMP_SENSORS["NTC Temperature Sensors"] --> MCU CURRENT_SENSE["High-Precision Current Sensing"] --> MCU OVP_UVP["OVP/UVP Protection"] --> PMIC TVS_ARRAY["TVS Protection Array"] --> TRANS_CONN RC_SNUBBER["RC Snubber Network"] --> HV_PULSER end %% Thermal Management subgraph "Tiered Thermal Management" LEVEL1["Level 1: PCB Conduction
Main Power MOSFETs"] --> BUCK_SW LEVEL1 --> BOOST_SW LEVEL2["Level 2: Layout Air Flow
Analog Switches"] --> TR_SW LEVEL3["Level 3: Ambient Conduction
Protection MOSFETs"] --> PROT_SW end %% Communication Interfaces subgraph "System Communication" MCU --> USB_IF["USB Interface"] MCU --> WIFI_BT["Wi-Fi/Bluetooth Module"] MCU --> DISPLAY_IF["Display Interface"] end %% Style Definitions style BUCK_SW fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style TR_SW fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style PROT_SW fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

As AI-portable ultrasound devices evolve towards higher imaging resolution, longer battery life, and greater operational reliability, their internal power management and transducer drive systems are no longer simple converters. Instead, they are the core determinants of device imaging performance, operational duration, and user experience. A well-designed power chain is the physical foundation for these devices to achieve high signal fidelity for both transmit and receive, efficient power utilization, and stable operation under varying environmental conditions.
However, building such a chain presents multi-dimensional challenges within a compact form factor: How to generate high-voltage, precise pulses for the transducer while minimizing switching noise that interferes with sensitive receive signals? How to manage power efficiently from a limited battery to extend scanning time? How to ensure reliable protection and low heat generation in a sealed, handheld device? The answers lie within every engineering detail, from the selection of key components to system-level integration.
I. Three Dimensions for Core Power Component Selection: Coordinated Consideration of Voltage, Current, and Topology
1. Transmit/Receive Switch & H-Bridge Driver MOSFETs: The Core of Signal Integrity and Protection
The key device is the VBI5325 (Dual-N+P, ±30V, RDS(on) 24/40mΩ @4.5V, SOT89-6), whose selection is critical for the analog front-end.
Voltage Stress and Functionality: The ±30V drain-to-source voltage (VDS) is suitable for low-voltage transducer excitation and signal conditioning paths. The integrated complementary N-Channel and P-Channel pair in a single package is ideal for constructing compact transmit/receive (T/R) switches or H-bridge drivers for probe elements. This configuration allows for efficient steering of signals between the high-voltage transmit circuitry and the ultra-sensitive receive amplifier, providing essential isolation and protection.
Dynamic Characteristics and Loss Optimization: The low and balanced RDS(on) for both N and P channels ensures minimal signal attenuation and distortion when the switch is on. The fast switching capability (inherent to Trench technology) is crucial for maintaining pulse shape fidelity during transmission and for quickly isolating the receiver after the transmit phase.
PCB Layout Relevance: The SOT89-6 package offers a good compromise between compact size and ability to handle power/heat for its class. Its pins allow for a symmetrical layout, which is vital for maintaining signal balance in differential or push-pull circuits.
2. Main Power Path & DC-DC Conversion MOSFET: The Backbone of System Efficiency
The key device selected is the VBGQF1606 (Single-N, 60V, RDS(on) 6.5mΩ @10V, ID=50A, DFN8(3x3), SGT).
Efficiency and Power Density Enhancement: For a portable device powered by a battery pack (e.g., 14.8V nominal), a 60V rating provides ample margin for inductive voltage spikes. The ultra-low RDS(on) of 6.5mΩ is paramount for main power path management (e.g., load switches) and synchronous rectification in buck/boost converters. This minimizes conduction loss, directly extending battery life and reducing thermal buildup. The SGT (Shielded Gate Trench) technology offers an excellent figure-of-merit (RDS(on)Qg), enabling high-frequency switching in compact, high-efficiency DC-DC converters to power various internal rails (e.g., 5V, 3.3V, ±8V).
Portability and Thermal Constraints: The DFN8(3x3) package provides superior thermal performance through its exposed pad in an extremely small footprint. This allows for high-current handling (50A continuous) in space-constrained designs, which is essential for managing peak power demands during system startup or simultaneous operation of multiple subsystems (display, AI processor, probes).
3. High-Voltage Protection & Bias Supply MOSFET: The Guardian for Front-End Safety
The key device is the VB165R01 (Single-N, 650V, RDS(on) 8400mΩ @10V, SOT23-3, Planar).
System-Level Protection Role: While its current rating is modest (1A), its primary function is not power switching but protection and isolation. Its 650V rating is crucial for circuits interfacing with high-voltage transmit pulsers (which can generate spikes over 200V). It can be used as a series isolation switch or in a clamping circuit to protect downstream low-voltage circuitry from high-voltage breakdown or transients.
Reliability in Harsh Signal Environment: The Planar technology, while not as high-performance as newer trench types for low RDS(on), offers robust and predictable characteristics at high voltages. Its SOT23-3 package is universally available and allows for placement very close to connectors or sensitive nodes needing protection. Its relatively higher on-resistance is acceptable for its intended protective and light-duty bias switching functions.
II. System Integration Engineering Implementation
1. Tiered Thermal Management in a Confined Space
A multi-level heat dissipation strategy is essential.
Level 1: PCB Conduction & Chassis Coupling: The VBGQF1606 (DFN package) must be soldered to a large, multi-layer thermal pad with numerous vias connecting to internal ground planes, effectively using the PCB as a heatsink. Its heat may also be conductively coupled to the device's metal internal frame or housing.
Level 2: Layout-Optimized Air Cooling: Components like the VBI5325 and other analog switches generate less heat but are sensitive to noise. Their heat is managed through careful PCB copper pour and ensuring they are placed in areas with some natural airflow (if available) or away from major heat sources like the processor.
Level 3: Component Derating: For the VB165R01, its power dissipation is kept minimal by design, relying on ambient conduction through its leads and the PCB.
2. Electromagnetic Compatibility (EMC) and Signal Integrity Design
Noise Isolation: Physically separate the high-current switching path (containing VBGQF1606) from the sensitive analog front-end (containing VBI5325 and receive amplifiers). Use separate power planes and ground partitions.
Switching Loop Minimization: For all switch-mode power supplies using VBGQF1606, keep the high-di/dt loops (input capacitor, MOSFET, inductor) extremely small and tight to minimize radiated noise.
Shielding and Filtering: Shield the entire transducer cable and front-end section. Use ferrite beads and LC filters on all power rails entering the analog domain. The VB165R01 acts as part of the front-end protection filter against high-voltage noise.
3. Reliability Enhancement Design
Electrical Stress Protection: Use TVS diodes and RC snubbers at the transducer connector to absorb reflected energy. Ensure proper gate driving for all MOSFETs to avoid slow switching and excessive heat. The VB165R01 itself is a key component in the protection scheme.
Fault Diagnosis: Implement overcurrent protection on the main battery input path (monitoring via a sense resistor). Monitor temperature of the main PCB near the processor and power management ICs.
III. Performance Verification and Testing Protocol
1. Key Test Items and Standards
Acoustic Performance Test: Verify image signal-to-noise ratio (SNR) and contrast resolution with the power system operating, ensuring no introduced switching noise degrades image quality.
Battery Run-Time Test: Measure operational duration under a standardized scanning protocol, directly linked to the efficiency of the power chain centered around components like VBGQF1606.
Thermal Imaging Test: Use a thermal camera after prolonged operation to identify hot spots, ensuring junction temperatures of all semiconductors, especially VBGQF1606, are within safe limits.
EMC Compliance Test: Must meet medical equipment standards (e.g., IEC 60601-1-2) for emissions and immunity, ensuring the device does not interfere with nor is affected by other equipment.
Drop and Vibration Test: Ensure solder joints of packages like DFN and SOT can withstand mechanical shocks typical of portable device handling.
2. Design Verification Example
Test data from a prototype AI ultrasound device (Battery: 4-cell Li-ion, 14.8V, 6000mAh) shows:
System quiescent current met the sub-50mA target, enabled by efficient load switching.
Peak efficiency of the 14.8V to 5V/3A DC-DC converter (using VBGQF1606 as sync rectifier) exceeded 94%.
No observable degradation in phantom image quality was detected when the display backlight and AI processing were at maximum load.
The device casing temperature remained below 40°C during a continuous 45-minute scanning session.
IV. Solution Scalability
1. Adjustments for Different Probes and Performance Levels
Basic Linear/Convex Probe Devices: The selected trio provides a robust, cost-effective foundation. The VBI5325 can manage smaller channel counts.
High-Channel Count Phased Array Devices: May require multiple VBI5325 devices or similar for larger T/R switch matrices. The main power path (VBGQF1606) may need to be paralleled or a higher-current variant used to support increased digital and analog power demands.
Ultra-Portable "Pocket" Devices: Focus on even smaller packages (e.g., considering VBQG8658 for P-side needs in a smaller DFN). May operate at lower voltages, allowing for further optimization of RDS(on) and gate drive.
2. Integration of Cutting-Edge Technologies
Advanced Packaging: Future iterations can leverage wafer-level chip-scale packages (WLCSP) for MOSFETs in the signal path to save even more space.
GaN Technology Roadmap: For the next generation, Gallium Nitride (GaN) HEMTs could be evaluated for the very high-frequency DC-DC conversion stage, pushing power density and efficiency even higher, allowing for smaller magnetics and potentially a thinner device profile.
Intelligent Power Management: Deeper integration with the AI processor to implement predictive power state control based on usage mode (B-mode, Doppler, etc.), dynamically scaling voltage and clock frequencies to minimize power draw.
Conclusion
The power chain design for AI-portable ultrasound devices is a meticulous exercise in balancing conflicting constraints: high-voltage signal generation, microvolt-level signal reception, stringent thermal limits, and the uncompromising demand for miniaturization and battery life. The tiered optimization scheme proposed—prioritizing signal integrity and protection at the front-end with VBI5325, focusing on ultra-high efficiency and power density in the core converter with VBGQF1606, and ensuring robust high-voltage safety with VB165R01—provides a clear and reliable implementation path for developing a new generation of intelligent, handheld diagnostic tools.
As computational imaging and AI inference become more central, future device architectures will trend towards greater power domain segmentation and dynamic control. It is recommended that engineers adhere to medical-grade design and validation processes while employing this framework, laying a solid foundation for subsequent integration of higher-efficiency wide-bandgap semiconductors and advanced power management algorithms.
Ultimately, excellent power design in a medical device is silent and invisible. It does not manifest in the user interface, yet it fundamentally enables the device's clinical utility through clear images, long battery life, cool operation, and dependable performance—directly contributing to the value of point-of-care diagnostics.

Detailed Topology Diagrams

Transmit/Receive Switch & H-Bridge Driver Topology Detail

graph LR subgraph "Transmit/Receive Switch Configuration" TX_PULSE["High-Voltage Transmit Pulse"] --> TX_IN["Transmit Input"] RX_SIG["Receive Signal from Transducer"] --> RX_IN["Receive Input"] subgraph "VBI5325 Dual N+P Switch" direction TB NGATE["N-Channel Gate"] PGATE["P-Channel Gate"] NCHAN["N-Channel
RDS(on)=24mΩ"] PCHAN["P-Channel
RDS(on)=40mΩ"] end TX_IN --> CONTROL_LOGIC["T/R Control Logic"] CONTROL_LOGIC --> NGATE CONTROL_LOGIC --> PGATE NCHAN --> COMMON_NODE["Common Node"] PCHAN --> COMMON_NODE COMMON_NODE --> TRANSDUCER["To Transducer Element"] COMMON_NODE --> RX_OUT["To Receive Amplifier"] end subgraph "H-Bridge Driver for Probe Elements" DRV_PWR["Driver Power ±8V"] --> H_BRIDGE_PWR subgraph "H-Bridge Using VBI5325 Devices" Q1["VBI5325-1
(High Side P)"] Q2["VBI5325-2
(Low Side N)"] Q3["VBI5325-3
(High Side P)"] Q4["VBI5325-4
(Low Side N)"] end H_BRIDGE_CTRL["H-Bridge Controller"] --> Q1 H_BRIDGE_CTRL --> Q2 H_BRIDGE_CTRL --> Q3 H_BRIDGE_CTRL --> Q4 Q1 --> TRANS_A["Transducer Element A"] Q2 --> TRANS_A Q3 --> TRANS_B["Transducer Element B"] Q4 --> TRANS_B end style NCHAN fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style PCHAN fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Main Power Path & DC-DC Conversion Topology Detail

graph LR subgraph "Synchronous Buck Converter (14.8V to 5V/3.3V)" SYS_14V["14.8V System Bus"] --> BUCK_IN subgraph "VBGQF1606 Synchronous Pair" HS_SW["High-Side Switch
VBGQF1606"] LS_SW["Low-Side Switch
VBGQF1606"] end BUCK_CONTROLLER["Buck Controller"] --> HS_DRV["High-Side Driver"] BUCK_CONTROLLER --> LS_DRV["Low-Side Driver"] HS_DRV --> HS_SW LS_DRV --> LS_SW HS_SW --> SW_NODE["Switching Node"] LS_SW --> SW_NODE SW_NODE --> BUCK_INDUCTOR["Buck Inductor"] BUCK_INDUCTOR --> BUCK_CAP["Output Capacitors"] BUCK_CAP --> VCC_5V_OUT["5V Output"] FB_NETWORK["Voltage Feedback Network"] --> BUCK_CONTROLLER end subgraph "Main Power Path Management" BAT_IN["Battery Input"] --> BAT_PROT_CIRCUIT["Protection Circuit"] BAT_PROT_CIRCUIT --> LOAD_SWITCH["VBGQF1606 Load Switch"] subgraph "Load Switch Configuration" LOAD_SW_GATE["Gate Drive"] LOAD_SW_DS["Drain-Source Path
RDS(on)=6.5mΩ"] end MCU_GPIO["MCU GPIO Control"] --> LOAD_SW_GATE LOAD_SW_DS --> SYS_POWER["System Power Distribution"] SYS_POWER --> SUB_SYSTEM1["Display Backlight"] SYS_POWER --> SUB_SYSTEM2["AI Processor"] SYS_POWER --> SUB_SYSTEM3["Wireless Module"] end subgraph "Thermal Management Implementation" HS_SW --> THERMAL_PAD["Exposed Thermal Pad"] THERMAL_PAD --> PCB_VIA["Thermal Vias Array"] PCB_VIA --> GROUND_PLANE["Inner Ground Plane"] GROUND_PLANE --> CHASSIS["Metal Chassis Coupling"] TEMP_MONITOR["Temperature Monitor"] --> PWM_CONTROL["Fan PWM Control"] PWM_CONTROL --> COOLING_FAN["Cooling Fan (if present)"] end style HS_SW fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style LS_SW fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style LOAD_SW_DS fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

High-Voltage Protection & Front-End Safety Topology Detail

graph LR subgraph "High-Voltage Transmit Protection" HV_TX["High-Voltage Transmit Circuit
>200V Pulses"] --> SERIES_SW["VB165R01 Series Switch"] subgraph "VB165R01 Protection Switch" HV_GATE["Gate Control"] HV_DS["650V Drain-Source
RDS(on)=8400mΩ"] end PROT_CONTROL["Protection Controller"] --> HV_GATE HV_DS --> TRANS_OUT["To Transducer Connector"] TRANS_OUT --> CLAMP_NODE["Clamping Node"] CLAMP_NODE --> TVS_DIODE["High-Voltage TVS Diode"] CLAMP_NODE --> RC_SNUBBER["RC Snubber Network"] TVS_DIODE --> GND_HV["High-Voltage Ground"] RC_SNUBBER --> GND_HV end subgraph "Front-End Signal Isolation & Protection" TRANS_IN["From Transducer"] --> PROTECTION_IN subgraph "Multi-Stage Protection Network" BAND_PASS["Band-Pass Filter"] LIMITER["Signal Limiter"] DC_BLOCK["DC Blocking Capacitor"] end PROTECTION_IN --> BAND_PASS BAND_PASS --> LIMITER LIMITER --> DC_BLOCK DC_BLOCK --> AFE_IN["To Analog Front-End"] LIMITER --> PROTECTION_DIODES["Schottky Protection Diodes"] PROTECTION_DIODES --> SUPPLY_RAILS["±8V Supply Rails"] end subgraph "EMC & Signal Integrity Measures" POWER_IN["Power Input"] --> PI_FILTER["π-Filter Network"] PI_FILTER --> FERRITE_BEAD["Ferrite Bead"] FERRITE_BEAD --> CLEAN_POWER["Clean Analog Power"] subgraph "Grounding Strategy" DIGITAL_GND["Digital Ground Plane"] ANALOG_GND["Analog Ground Plane"] POWER_GND["Power Ground Plane"] end CLEAN_POWER --> ANALOG_GND GND_SEP["Star Ground Connection"] --> DIGITAL_GND GND_SEP --> ANALOG_GND GND_SEP --> POWER_GND SHIELDING["RF Shielding Can"] --> AFE_IN end style HV_DS fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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