In the pursuit of quantum supremacy, the performance of a quantum computer is not solely determined by the coherence time of qubits. It is equally constrained by the precision, stability, and noise level of its classical support systems—the electronic control and power infrastructure. This infrastructure, operating often at the boundary of room temperature and cryogenic environments, must deliver exceptionally clean, stable, and reliable power to sensitive components like qubit control lines (RF/microwave), cryo-amplifiers, magnet systems, and peripheral logic circuits. The selection of power semiconductor devices, therefore, transcends mere efficiency; it becomes a critical exercise in minimizing electrical noise (both conducted and radiated), ensuring reliability under thermal cycling stress, and achieving precise digital control over analog power domains.
This article adopts a holistic, noise-aware design philosophy to address the core challenges within the power delivery network (PDN) of a high-end quantum computing system: how to select the optimal power MOSFETs/IGBTs for three distinct yet interconnected nodes—high-voltage primary side isolation/ conversion, intermediate voltage bus regulation, and ultra-low-noise, high-current bias generation for cryogenic stages—under the extreme constraints of low electromagnetic interference (EMI), high dV/dt immunity, and often, non-standard operating temperatures.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Voltage Isolated Gatekeeper: VBP113MI25 (1350V IGBT, 25A, FS Technology, TO-247) – Primary Side Main Switch in Isolated DC-DC Converters for High-Voltage Input
Core Positioning & Topology Deep Dive: This 1350V Field-Stop (FS) Trench IGBT is engineered for the front-end power factor correction (PFC) or isolated DC-DC converter stage that interfaces with a high-voltage AC/DC input (e.g., 480VAC three-phase). Its high voltage rating provides robust margin against line transients and ensures safe operation in hard-switching or resonant (LLC) topologies commonly used for galvanic isolation. The FS technology offers a favorable trade-off between low saturation voltage (VCEsat typ. 2V @15V) and moderate switching losses.
Key Technical Parameter Analysis:
Voltage Ruggedness & Safety Margin: The 1350V rating is ideal for 600-800V DC-link applications post-rectification, offering >50% derating for enhanced long-term reliability, a critical factor for 24/7 operational quantum systems.
Low-Conduction Loss in Medium-Frequency Range: For switching frequencies in the 20-50kHz range typical of medium/high-power isolated converters, the conduction loss dominates. The low VCEsat minimizes this loss, improving efficiency at the system's entry point.
Drive Consideration for Noise Minimization: The VGEth of 5.5V and recommended VGE of ±30V allow for a robust gate drive design that can suppress parasitic turn-on due to high dV/dt, a key requirement for maintaining clean switching waveforms and low EMI.
2. The Efficient & Quiet Bus Regulator: VBM16R32S (600V, 32A, SJ_Multi-EPI, TO-220) – Main Switch in Intermediate Bus Converter (IBC) or Non-Isolated Point-of-Load (POL) Regulators
Core Positioning & System Benefit: Positioned after the isolated stage, this 600V Super-Junction (SJ) MOSFET is optimized for converting the primary isolated DC voltage (e.g., 400V) to a lower intermediate bus voltage (e.g., 48V or 12V). Its low Rds(on) of 85mΩ @10V and fast switching capability of SJ technology are crucial.
High Efficiency at Elevated Frequencies: Enables the use of higher switching frequencies (e.g., 100-300kHz) in synchronous buck converters, reducing the size of magnetic components while maintaining high efficiency, directly contributing to a more compact and cooler operating power supply unit.
Low Gate Charge (Qg) for Precision Control: The SJ_Multi-EPI process typically yields a good FOM (Figure of Merit: Rds(on)Qg). Lower Qg allows for faster, crisper switching transitions with less drive current, reducing switching loss and the high-frequency content of switching noise that can couple into sensitive analog lines.
Thermal Performance: The TO-220 package offers a good balance between current handling and thermal impedance, facilitating effective heatsinking for this central conversion stage.
3. The Ultra-Low-Noise Cryogenic Bias Power Workhorse: VBFB1311 (30V, 50A, Trench, TO-251) – Low-Side Switch in High-Current, Low-Voltage Linear/Switching Regulators for Qubit Control and Cryo-Amplifier Bias
Core Positioning & System Integration Advantage: This device is the cornerstone for generating the ultra-stable, ultra-low-noise bias voltages and currents required at the quantum chip's front-end. Its exceptionally low Rds(on) of 7mΩ @10V is paramount.
Minimizing Conducted Noise & Voltage Ripple: In a linear regulator pass element configuration or as the synchronous switch in a low-noise buck converter, the ultra-low Rds(on) ensures minimal voltage drop and associated thermal (Johnson-Nyquist) noise, preserving signal integrity for qubit control pulses.
High Current Delivery in Compact Form: The 50A continuous current rating in a TO-251 package allows it to deliver substantial current (e.g., for multiple flux qubit bias lines or a cryogenic HEMT amplifier) from a tightly regulated source, enabling centralized, high-performance bias generation.
Cryogenic Operation Suitability: While specific data is needed, Trench MOSFETs often exhibit favorable behavior at cryogenic temperatures (e.g., 77K, 4K), including reduced Rds(on) and altered threshold characteristics. This makes the VBFB1311 a candidate for stages located within or interfacing with the cryostat, subject to thorough characterization.
II. System Integration Design and Expanded Key Considerations
1. Noise-Aware Topology, Drive, and Control
High-Voltage Stage (VBP113MI25): Employ soft-switching topologies (e.g., LLC) wherever possible to minimize high-frequency switching noise generation at the primary side. The gate drive loop must be tightly laid out with optimal turn-on/off resistors to control dI/dt and dV/dt.
Intermediate Bus Stage (VBM16R32S): Use synchronous rectification with careful dead-time management to avoid shoot-through and body diode conduction, both sources of loss and noise. Implement spread-spectrum frequency modulation (if applicable) to reduce peak EMI.
Low-Noise Bias Stage (VBFB1311): For the most critical analog rails, consider linear regulator post-regulation after a low-noise switcher. When used in a switcher, operate at a fixed frequency well outside the sensitive qubit control bands (e.g., GHz range) and use multi-stage LC filtering with ferrite beads. The gate drive signal itself must be exceptionally clean.
2. Hierarchical Thermal & Cryogenic Management Strategy
Primary Heat Source (External Cooling): The VBP113MI25 (IGBT) and VBM16R32S (MOSFET) in the room-temperature power supply will require forced air or liquid cooling based on calculated losses, with temperature stability being a key goal to prevent drift.
Cryogenic Interface Management: Any stage involving the VBFB1311 operating at low temperatures requires specialized thermal and electrical design. PCB material selection (e.g., low-outgassing, matched CTE), thermal anchoring, and understanding of device parameter shifts are critical.
3. Engineering Details for Quantum-Grade Reliability & Noise Immunity
Electrical Stress & Snubbing: Rigorous snubbing (RCD, RC) across all switching devices, especially the 1350V IGBT, to clamp voltage spikes from transformer leakage inductance that are both a reliability risk and a broadband noise source.
Enhanced Shielding & Layout: Enclose primary-side and intermediate switching circuits in separate, grounded shields. Use multi-layer PCBs with dedicated power and ground planes. Route sensitive analog bias lines away from any switching nodes with careful attention to return paths.
Precision Derating Practice:
Voltage Derating: Operate VBP113MI25 below 1080V (80% of 1350V); VBM16R32S below 480V (80% of 600V); VBFB1311 with ample margin from its 30V rating.
Current & Thermal Derating: Derate current based on worst-case junction temperature, aiming for Tj < 100°C for room-temperature devices to enhance lifespan. For cryogenic applications, base ratings on characterized low-temperature performance data.
III. Quantifiable Perspective on Scheme Advantages
Quantifiable Noise Reduction: Employing the ultra-low Rds(on) VBFB1311 in a linear regulator pass stage can reduce output voltage noise density by minimizing the intrinsic thermal noise contribution of the pass element, directly translating to narrower qubit resonance lines and potentially longer dephasing times.
Quantifiable System Efficiency & Thermal Gain: Using the high-performance SJ MOSFET VBM16R32S in the intermediate bus converter can achieve efficiency >96%, drastically reducing the thermal load that must be removed from the electronics rack, simplifying cooling system design.
Enhanced System Uptime: The conservative voltage derating and robust selection of the VBP113MI25 IGBT for the high-voltage front-end significantly reduce the failure rate due to voltage overstress, a critical factor for maximizing the operational availability of expensive quantum computing systems.
IV. Summary and Forward Look
This scheme outlines a meticulously optimized power chain for a high-end quantum computing platform, addressing the unique demands from AC inlet to quantum chip bias:
Power Input & Isolation Level – Focus on "Ruggedness & Safety": Select high-voltage-rated, robust switching devices to ensure unconditional safety and reliability of the primary power interface.
Power Distribution Level – Focus on "Efficient & Quiet Conversion": Utilize fast-switching, low-loss SJ MOSFETs to achieve high power density and efficiency while maintaining controllability over switching noise.
Precision Analog Bias Level – Focus on "Ultra-Low Noise & Current Delivery": Invest in components with the lowest possible conduction loss and noise characteristics, forming the foundation for high-fidelity quantum control.
Future Evolution Directions:
Wide Bandgap (WBG) Adoption: For the ultimate in efficiency and frequency, the primary and intermediate stages could migrate to Silicon Carbide (SiC) MOSFETs, enabling MHz+ switching frequencies, drastically smaller magnetics, and potentially lower noise spectra.
Integrated Intelligent Power Stages: For the low-voltage bias rails, consider power stage modules that integrate the MOSFET, driver, and protection, offering pre-characterized performance and reducing design uncertainty, especially for cryogenic applications.
Co-Design with Cryogenics: Future devices may be specifically characterized and optimized for operation at 4K or 77K, including custom packaging to manage thermal contraction and minimize parasitic inductance.
Engineers can refine this framework based on specific quantum computer architecture details, such as total power budget, required bias voltage/current accuracies, physical layout constraints between room-temperature and cryogenic stages, and the accepted EMI/EMC compliance levels.

Detailed Topology Diagrams