As high-end liquid-cooled storage systems evolve towards higher compute density, greater energy efficiency, and stringent reliability requirements, their internal power delivery and management systems are no longer simple converters. Instead, they are the core determinants of rack-level power performance, operational PUE (Power Usage Effectiveness), and total cost of ownership. A well-designed power chain is the physical foundation for these systems to achieve stable high-current delivery, ultra-high conversion efficiency, and flawless 24/7 operation under continuous full load.
However, building such a chain presents multi-dimensional challenges: How to maximize power density within the constrained space of a server tray or power shelf? How to ensure the long-term reliability of power semiconductors in a direct liquid-cooled environment that minimizes thermal resistance but introduces unique mechanical and environmental stresses? How to seamlessly integrate high-efficiency conversion, fast transient response, and intelligent power management? The answers lie within every engineering detail, from the selection of key components to system-level integration.
I. Three Dimensions for Core Power Component Selection: Coordinated Consideration of Voltage, Current, and Topology
1. High-Voltage Bus Switching & PFC Stage MOSFET: The Guardian of Input Power Integrity
The key device is the VBP165R06 (650V/6A/TO-247, Planar).
Voltage Stress & Technology Analysis: For 3-phase 400VAC input or high-voltage DC bus systems (e.g., 380VDC), a 650V-rated device is standard. The planar technology offers robust, well-characterized performance and high avalanche energy capability, suitable for handling input transients and inrush currents. Its TO-247 package is ideal for mounting onto a liquid-cooled cold plate, enabling efficient heat extraction from the front-end power stage.
Loss & Reliability Trade-off: The RDS(on) of 1700mΩ is acceptable for the relatively lower currents in this stage (e.g., for a 3-5kW PFC stage). The focus here is on high-voltage ruggedness and reliability over absolute lowest loss. The integrated body diode's reverse recovery characteristics must be considered in hard-switching topologies, but its robustness is beneficial.
2. High-Current, Low-Voltage POL (Point-of-Load) Converter MOSFET: The Engine of CPU/ASIC Power Delivery
The key device is the VBGQA1303 (30V/85A/DFN8(5x6), SGT).
Efficiency and Power Density Paramount: This device is engineered for the core of multi-phase buck converters powering CPUs, GPUs, or ASICs. Its ultra-low RDS(on) (2.7mΩ @10V) is critical for minimizing conduction loss, which dominates at these very high currents (often 100A+ per phase). The SGT (Shielded Gate Trench) technology optimizes switching loss and gate charge (Qg), enabling high switching frequencies (500kHz to 1MHz+). This shrinks inductor size and improves transient response. The compact DFN8 package minimizes parasitic inductance and saves critical board area, directly boosting power density.
Liquid Cooling Synergy: While the junction-to-case thermal resistance is low, the primary heat path is through the exposed pad into the PCB. In a liquid-cooled system, this heat is efficiently transferred via thermal vias and inner-plane copper layers to the system cold plate or a dedicated cold frame, allowing the device to sustain its high current rating continuously.
3. High-Side/Low-Side Power Switch for Bulk Power Distribution:
The key device is the VBM2603 (-60V/-120A/TO-220, Trench, P-Channel).
Role in Intelligent Power Management: This P-Channel MOSFET, with its exceptionally low RDS(on) of 3mΩ, is ideal for serving as a high-current load switch or high-side switch within a power shelf. It can intelligently control power rails to entire server blades, storage banks, or backup systems, enabling sequenced power-up/down and fault isolation.
Advantage of P-Channel: As a high-side switch, it simplifies gate drive circuitry compared to an N-Channel which requires a charge pump or bootstrap. This enhances reliability. The TO-220 package offers a classic, reliable mechanical interface for screw mounting to a busbar or a dedicated heatsink spot on the cold plate, ensuring minimal connection resistance and optimal thermal performance for a device handling hundreds of amps.
II. System Integration Engineering Implementation
1. Hierarchical Thermal Management Leveraging Liquid Cooling
Level 1: Direct Cold Plate Attachment: High-power dissipation devices like the VBP165R06 (PFC stage) and VBM2603 (bulk switch) are directly mounted onto a liquid-cooled baseplate or dedicated cold plates. Thermal interface material (TIM) selection is critical for minimizing junction-to-fluid thermal resistance.
Level 2: PCB-Conduction to Cold Frame: For high-density POL converters using devices like the VBGQA1303, heat is conducted through a thick, multi-layer PCB with embedded copper planes and arrays of thermal vias. The PCB itself is clamped or attached to a system-wide cold frame circulating coolant, creating an isothermal environment.
Level 3: System-Level Fluid Dynamics: Design focuses on uniform flow distribution across all cold plates and cold frames to prevent hot spots. Materials must be compatible with dielectric coolant (e.g., immersion fluids) if used.
2. Signal Integrity and Low-Noise Power Delivery Design
High di/dt Loop Minimization: For the POL stage using VBGQA1303, use a symmetric, tightly coupled layout with input ceramic capacitors placed immediately adjacent to the MOSFET pair. This minimizes parasitic inductance in the switching loop, reducing voltage spikes and EMI.
Gate Drive Optimization: The fast switching capability of SGT MOSFETs demands careful gate drive design. Use low-inductance gate driver ICs placed close to the MOSFET, with properly sized gate resistors to balance switching speed and ringing.
Bulk Power Distribution: For circuits using the VBM2603, employ wide, laminated busbars to distribute high current with minimal loss and inductance. Kelvin connections for current sensing are essential for accurate measurement and control.
3. Reliability Enhancement for 24/7 Operation
Electrical Stress Protection: Implement active clamp circuits or snubbers in high-voltage switching nodes (e.g., around VBP165R06) to manage voltage overshoot. Ensure proper drain-source TVS protection for the VBM2603 against inductive kickback from the load.
Fault Diagnosis and Health Monitoring: Implement comprehensive telemetry: monitor current via precision shunts, voltage at key nodes, and temperature at multiple points (case, coolant in/out). For critical POL stages, monitor the output voltage ripple and transient response as indicators of capacitor health. Predictive algorithms can track the gradual increase in MOSFET RDS(on) over time.
III. Performance Verification and Testing Protocol
1. Key Test Items and Standards
Conversion Efficiency Test: Measure full-load efficiency across the entire load range (10%-110%) for each power stage (PFC, POL). Target peak efficiency >96% for POL, >98% for high-voltage stages.
Thermal & Liquid Cooling Performance Test: Under maximum continuous load, verify that all semiconductor junction temperatures remain within safe limits (e.g., Tj < 125°C) with specified coolant flow rate and inlet temperature (e.g., 45°C). Map temperature distribution across the board.
Transient Response Test: Apply step loads (e.g., 50% to 100% of max current in 1µs) to POL converters and verify output voltage deviation and recovery time meet processor specifications.
Long-Term Reliability Test: Conduct accelerated life testing (HTOL) at elevated temperature and humidity, along with thermal cycling tests, to validate MTBF projections.
2. Design Verification Example
Test data from a 5kW liquid-cooled storage server power shelf (400VDC input, 12V/1.8V intermediate buses):
High-voltage input stage (using VBP165R06) efficiency: 99.2% at full load.
48V to 12V intermediate bus converter (using similar SGT tech) peak efficiency: 98%.
12V to 1.8V POL stage (using VBGQA1303) peak efficiency: 96.5% at 150A load.
Key Point Temperature: POL MOSFET (VBGQA1303) case temperature stabilized at 68°C with 45°C coolant inlet.
Bulk distribution switch (VBM2603) case temperature: 55°C under 80A continuous load.
IV. Solution Scalability
1. Adjustments for Different Power Levels and Architectures
High-Performance Computing (HPC) Node: Emphasizes extreme POL density. Can utilize multiple VBGQA1303 in parallel per phase or explore even more advanced wafer-level packaging.
Scale-Out Storage Shelf: Focuses on efficiency of bulk conversion and distribution. The VBM2603 and VBP165R06 play central roles, with scalability achieved by paralleling devices.
Backup Power & Management System: Requires robust, high-voltage switches like VBP165R06 for bus tie and isolation functions.
2. Integration of Cutting-Edge Technologies
Wide-Bandgap (GaN/SiC) Roadmap: Can be planned in phases:
Phase 1 (Current): Optimized Si MOSFETs (VBGQA1303) for POL, Si Planar (VBP165R06) for HV input.
Phase 2 (Near-term): Introduce GaN HEMTs for the 48V-12V or 12V-1.8V stages to push switching frequency beyond 1MHz, drastically reducing magnetic size.
Phase 3 (Future): Adopt SiC MOSFETs for the front-end PFC/high-voltage bus section to reduce loss and increase power density further.
AI-Driven Dynamic Power & Thermal Management: Integrate system telemetry with machine learning algorithms to dynamically adjust voltage regulators, fan pumps, and workload placement for optimal efficiency and reliability under real-time loads.
Conclusion
The power chain design for high-end liquid-cooled storage systems is a multi-dimensional challenge balancing power density, conversion efficiency, thermal performance, and unwavering reliability. The tiered optimization scheme proposed—prioritizing high-voltage ruggedness at the input, extreme low-RDS(on) and high-frequency performance at the POL, and intelligent, low-loss switching for bulk distribution—provides a clear implementation path for next-generation data center power architectures.
As data centers move towards full immersion cooling and rack-scale power management, future designs will trend towards deeper integration of power stages and domain-level control. Engineers must adhere to rigorous telecom/server-grade design standards while leveraging this framework, preparing for the inevitable transition to wide-bandgap semiconductors and AI-optimized power management.
Ultimately, excellent power design in a liquid-cooled environment is characterized by its silent, efficient, and relentless operation. It delivers the pristine, stable power required by advanced silicon, translating directly into higher computational throughput, lower operational costs, and superior reliability—the true metrics of value in the modern data center.

Detailed Topology Diagrams