With the rapid growth of high-density computing and green data centers, immersion-cooled IT container units have become a core solution for achieving extreme power density and optimal energy efficiency. The power conversion and distribution systems, serving as the "heart" of the unit, provide precise and reliable power delivery to critical loads such as server racks, pump drives, and cooling control systems. The selection of power MOSFETs and IGBTs directly determines system efficiency, thermal performance, power density, and long-term reliability. Addressing the stringent demands of immersion-cooled containers for high efficiency, high reliability, compactness, and operation in specialized environments, this article develops a practical and optimized device selection strategy based on scenario-specific adaptation. I. Core Selection Principles and Scenario Adaptation Logic (A) Core Selection Principles: Multi-Dimensional Co-optimization Device selection requires a balanced consideration across key dimensions—voltage rating, conduction/switching losses, package ruggedness, and reliability—ensuring robust performance within the immersion-cooling context. High Voltage & Robustness: For direct AC-fed or high-voltage DC bus architectures (e.g., 400V AC, 800V DC), prioritize devices with sufficient voltage margin (≥50-100%) to withstand line transients and switching spikes in a potentially noisy container environment. Ultra-Low Loss Operation: Prioritize devices with very low Rds(on) and optimized switching figures (Qg, Coss, VCEsat for IGBTs) to minimize losses, which is critical for maximizing Power Usage Effectiveness (PUE) and reducing heat dumped into the dielectric coolant. Package & Thermal Compatibility: Select packages (TO-220, TO-220F, DFN) that offer a good balance between current handling, thermal impedance, and compatibility with immersion or secondary cooling interfaces. Robust isolation and material integrity are essential for long-term fluid compatibility. Reliability & Environmental Suitability: Devices must offer high thermal stability, wide junction temperature range, and ruggedness to meet 24/7/365 operation demands in a sealed, potentially high-humidity internal environment. (B) Scenario Adaptation Logic: Categorization by Power Stage Function Divide main power stages into three core scenarios: First, Primary AC-DC Conversion & PFC (High Voltage), requiring high-voltage blocking and good switching performance. Second, Intermediate DC-DC Conversion & Pump Motor Drive (Medium Voltage/Current), requiring a balance of voltage rating, low Rds(on), and drive capability. Third, Point-of-Load (POL) Conversion & Auxiliary Control (Low Voltage/High Current), requiring very low conduction loss and compact thermal footprint. II. Detailed Device Selection Scheme by Scenario (A) Scenario 1: Primary AC-DC & PFC Stage (400-800V Bus) – High Voltage Switch This stage handles rectified line voltage and requires high-voltage devices with good efficiency for power factor correction and initial conversion. Recommended Model: VBM19R09S (Single-N MOSFET, 900V, 9A, TO-220) Parameter Advantages: Super-Junction Multi-EPI technology provides excellent Rds(on)Area product for 900V rating (750mΩ @10V). The 900V VDS offers ample margin for 400VAC systems (565V DC link). TO-220 package facilitates mounting to a heatsink or cold plate for primary heat removal. Adaptation Value: Enables efficient high-voltage switching in PFC or two-stage converter topologies. Its high voltage rating enhances system robustness against grid surges. The technology offers a favorable trade-off between switching loss and conduction loss for medium-frequency (e.g., 50-100 kHz) operation. Selection Notes: Verify operating frequency and loss breakdown. Gate drive must be robust (±30V max VGS). Requires careful attention to switching node layout to minimize parasitic oscillations. Heatsinking is mandatory. (B) Scenario 2: Intermediate DC-DC & Pump Drive (48V-200V Bus) – Medium Power Switch This stage includes bus converters, pump motor drives (for coolant circulation), and fan controls, requiring efficient power handling and control. Recommended Model: VBGMB1207N (Single-N MOSFET, 200V, 20A, TO-220F) Parameter Advantages: SGT (Shielded Gate Trench) technology achieves very low Rds(on) of 68mΩ @10V. The 200V rating is ideal for 48V/96V/190V intermediate bus applications with good margin. TO-220F (fully molded) package offers improved creepage/clearance and is suitable for environments where condensation might be a concern. Adaptation Value: Excellent for synchronous rectification in DC-DC converters or for driving pump BLDC motors. Low conduction loss boosts stage efficiency. The SGT technology typically offers low Qg, facilitating higher frequency operation and magnetics size reduction. Selection Notes: Ensure drive current is sufficient for its Qg at target frequency. For motor drive, consider current derating for startup loads. Thermal management via heatsink or cold plate attachment is required for full current operation. (C) Scenario 3: High-Current Point-of-Load (POL) Conversion (12V/5V Bus) – Ultra-Low Loss Switch Server POL converters demand extremely high efficiency and current density, necessitating switches with minimal conduction loss. Recommended Model: VBM1615 (Single-N MOSFET, 60V, 60A, TO-220) Parameter Advantages: Advanced Trench technology provides an exceptionally low Rds(on) of 11mΩ @10V (13mΩ @4.5V). The 60A continuous current rating handles high POL currents with ease. 60V VDS is perfectly suited for inputs from 12V or 48V-to-12V intermediate buses. Adaptation Value: Dramatically reduces conduction loss in synchronous buck converters. For a 12V input, 100A output POL, conduction loss per switch is exceptionally low, enabling efficiency >97%. This directly reduces heat generation within the immersed server tray environment. Selection Notes: Requires very careful PCB layout to minimize parasitic resistance and inductance in the high-current loop. Must be paired with a low-side MOSFET of similar performance. Heatsinking is critical, ideally through direct attachment to a cold plate or the immersion-cooled substrate. III. System-Level Design Implementation Points (A) Drive Circuit Design: Matching Device Characteristics VBM19R09S: Requires a high-side gate driver with sufficient drive capability (≥2A peak) to manage its Miller capacitance. Use negative voltage turn-off for robust operation in bridge configurations. VBGMB1207N: Can be driven by standard half-bridge drivers (e.g., IRS2184). Optimize gate resistance to balance switching loss and EMI. VBM1615: Requires a high-current, fast driver dedicated to POL controllers. Pay extreme attention to gate loop layout shortness to prevent parasitic turn-on. (B) Thermal Management Design for Immersion Context Immersion-Specific Considerations: While primary cooling is via dielectric fluid, device packages must still transfer heat to the fluid or to a secondary cold plate. Ensure package surfaces are compatible with fluid chemistry. Use thermal interface materials rated for immersion if needed. Mounting: For TO-220/TO-220F devices, secure mounting to designated thermally conductive surfaces (cold plates, chassis walls) is essential. Apply appropriate torque. PCB-Level Cooling: For POL devices (VBM1615), ensure the PCB itself is designed for excellent thermal conduction, using thick copper, thermal vias, and potentially direct fluid contact or attachment to cooling structures. (C) EMC and Reliability Assurance EMC Suppression: Implement snubber circuits (RC across switches) for high-voltage switches (VBM19R09S). Use ferrite beads on gate drives. Ensure excellent input filtering at the container power inlet. Reliability Protection: Derating: Apply conservative derating (voltage ≥60%, current ≥50% at max anticipated case temperature). Overcurrent Protection: Implement precise shunt-based or FET Rds(on)-sensing protection on all critical power stages. Overvoltage/Transient Protection: Utilize MOVs at the AC input and TVS diodes on DC buses and gate drives. For immersion environments, ensure protection devices are also rated for the operational environment. IV. Scheme Core Value and Optimization Suggestions (A) Core Value Maximized System Efficiency: The combination of high-voltage SJ MOSFETs, efficient medium-voltage SGT devices, and ultra-low Rds(on) POL switches drives peak system efficiency, directly improving PUE. High Power Density & Reliability: Selected devices enable compact, high-frequency designs. Their rugged packages and specifications ensure long-term reliability in the demanding container environment. Thermal Management Synergy: Device choices align with immersion cooling's strengths, allowing heat to be efficiently removed from critical loss points. (B) Optimization Suggestions For Higher Power PFC: Consider paralleling VBM19R09S or evaluating IGBTs (e.g., VBM16I07) for very high power, lower frequency stages. For Space-Constrained POL: For applications where TO-220 is too large, explore high-performance DFN packages (e.g., VBQF1208N) with direct cold-plate attach, ensuring thermal performance is met. For Pump Drive Redundancy: Use dual N+P channel combinations or intelligent power modules for fault-tolerant pump control circuits. Specialized Gate Drivers: Pair high-side switches with isolated gate drivers featuring reinforced isolation for safety and noise immunity in the high-power environment. Conclusion The strategic selection of power semiconductors is central to achieving the efficiency, density, and unwavering reliability targets of next-generation immersion-cooled IT container units. This scenario-based scheme, from high-voltage input to low-voltage POL, provides a comprehensive technical roadmap. Future exploration can focus on the integration of Wide Bandgap (SiC, GaN) devices for the highest frequency and efficiency frontiers, and on co-packaged power stages that further optimize thermal and electrical performance within the immersion-cooled ecosystem.
Detailed Topology Diagrams
Primary AC-DC & PFC Stage Topology Detail
graph LR
subgraph "Three-Phase PFC Boost Converter"
A["Three-Phase 400VAC"] --> B["EMI Filter"]
B --> C["Three-Phase Rectifier"]
C --> D["DC Link Capacitor"]
D --> E["PFC Inductor"]
E --> F["PFC Switching Node"]
subgraph "High-Voltage MOSFETs"
Q1["VBM19R09S 900V/9A"]
Q2["VBM19R09S 900V/9A"]
Q3["VBM19R09S 900V/9A"]
end
F --> Q1
F --> Q2
F --> Q3
Q1 --> G["High-Voltage Bus 800VDC"]
Q2 --> G
Q3 --> G
H["PFC Controller"] --> I["Gate Driver"]
I --> Q1
I --> Q2
I --> Q3
G -->|Voltage Feedback| H
end
subgraph "Protection Circuits"
J["RCD Snubber"] --> Q1
K["RC Snubber"] --> Q2
L["MOV Array"] --> C
M["TVS Diodes"] --> I
end
subgraph "Thermal Interface"
N["Immersion Cooling Plate"] --> Q1
N --> Q2
N --> Q3
O["Temperature Sensor"] --> P["Thermal Monitor"]
P --> H
end
style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
style N fill:#e8f4f8,stroke:#0288d1,stroke-width:2px
Intermediate DC-DC & Pump Drive Topology Detail
graph LR
subgraph "DC-DC LLC Resonant Converter"
A["800V DC Input"] --> B["LLC Resonant Tank"]
B --> C["High-Frequency Transformer"]
C --> D["Secondary Winding"]
subgraph "Synchronous Rectification"
Q_SR_H1["VBGMB1207N 200V/20A"]
Q_SR_L1["VBGMB1207N 200V/20A"]
end
D --> Q_SR_H1
D --> Q_SR_L1
Q_SR_H1 --> E["Output Filter"]
Q_SR_L1 --> E
E --> F["Intermediate Bus 48-200VDC"]
G["LLC Controller"] --> H["SR Controller"]
H --> Q_SR_H1
H --> Q_SR_L1
end
subgraph "Pump BLDC Motor Drive"
F --> I["Three-Phase Inverter"]
subgraph "Inverter Bridge"
Q_U1["VBGMB1207N 200V/20A"]
Q_V1["VBGMB1207N 200V/20A"]
Q_W1["VBGMB1207N 200V/20A"]
Q_U2["VBGMB1207N 200V/20A"]
Q_V2["VBGMB1207N 200V/20A"]
Q_W2["VBGMB1207N 200V/20A"]
end
I --> Q_U1
I --> Q_V1
I --> Q_W1
I --> Q_U2
I --> Q_V2
I --> Q_W2
Q_U1 --> J["Pump Motor Phase U"]
Q_V1 --> K["Pump Motor Phase V"]
Q_W1 --> L["Pump Motor Phase W"]
Q_U2 --> GROUND
Q_V2 --> GROUND
Q_W2 --> GROUND
M["Motor Controller"] --> N["Gate Driver"]
N --> Q_U1
N --> Q_V1
N --> Q_W1
N --> Q_U2
N --> Q_V2
N --> Q_W2
end
subgraph "Thermal Management"
O["Cold Plate Attachment"] --> Q_SR_H1
O --> Q_U1
P["Temperature Sensors"] --> Q["Thermal Controller"]
Q --> R["Pump Speed Control"]
R --> S["Cooling Pump"]
end
style Q_SR_H1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style Q_U1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
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