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Smart Power Management Solution for High-End Data Lake Storage: Efficient and Reliable Power Delivery System Adaptation Guide
Smart Power Management for High-End Data Lake Storage

High-End Data Lake Storage Power Management System Overall Topology

graph LR %% Input Power Distribution subgraph "AC Input & Primary Power Distribution" AC_IN["3-Phase 480VAC/277VAC
Data Center Input"] --> MAIN_BREAKER["Main Circuit Breaker"] MAIN_BREAKER --> PDU["Power Distribution Unit (PDU)"] PDU --> RACK_INPUT["Storage Rack Power Input"] end %% AC-DC Front-End Power Supply subgraph "AC-DC Front-End / Server PSU" RACK_INPUT --> AC_DC_FRONTend["AC-DC Front-End Power Supply"] subgraph "PFC Stage & Primary Conversion" PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> PFC_MOSFET["VBMB165R12
650V/12A
PFC MOSFET"] AC_DC_FRONTend --> PFC_MOSFET PFC_MOSFET --> HV_DC_BUS["High Voltage DC Bus
~400VDC"] end subgraph "DC-DC Isolation Stage" HV_DC_BUS --> LLC_TRANSFORMER["LLC Resonant Transformer"] LLC_TRANSFORMER --> SYNC_RECT["Synchronous Rectification"] SYNC_RECT --> INTERMEDIATE_BUS["Intermediate Bus
48V/54V"] end end %% Intermediate Bus to Point-of-Load subgraph "Intermediate Bus Distribution & POL Conversion" INTERMEDIATE_BUS --> BACKPLANE_DIST["Backplane Power Distribution"] subgraph "Hot-Swap & Power Path Management" HOTSWAP_CONTROLLER["Hot-Swap Controller"] --> HS_DRIVER["Driver Circuit"] HS_DRIVER --> HOTSWAP_MOSFET["VBE2605
-60V/-140A
Hot-Swap MOSFET"] BACKPLANE_DIST --> HOTSWAP_MOSFET HOTSWAP_MOSFET --> POL_INPUT["POL Module Input"] end subgraph "High-Current Point-of-Load Conversion" POL_CONTROLLER["POL Controller"] --> POL_DRIVER["High-Current Driver"] POL_DRIVER --> POL_MOSFET["VBGQE11506
150V/100A
POL MOSFET"] POL_INPUT --> POL_MOSFET POL_MOSFET --> FINAL_OUTPUT["Final Output
12V/5V/3.3V"] FINAL_OUTPUT --> COMPUTE_NODE["Compute Nodes"] FINAL_OUTPUT --> STORAGE_ARRAY["HDD/SSD Storage Array"] end end %% System Loads & Management subgraph "System Loads & Intelligent Management" COMPUTE_NODE --> CPU_GPU["CPU/GPU Compute Units"] STORAGE_ARRAY --> STORAGE_CONTROLLER["Storage Controllers"] subgraph "Cooling System Power" COOLING_CONTROLLER["Cooling Controller"] --> FAN_DRIVER["Fan Driver"] FAN_DRIVER --> COOLING_MOSFET["VBE2605
Fan Control MOSFET"] INTERMEDIATE_BUS --> COOLING_MOSFET COOLING_MOSFET --> COOLING_FANS["Cooling Fans"] COOLING_MOSFET --> LIQUID_PUMPS["Liquid Cooling Pumps"] end subgraph "System Management" MGMT_MCU["Management MCU"] --> SENSORS["Temperature/Current Sensors"] MGMT_MCU --> PMBUS["PMBus Communication"] MGMT_MCU --> ALERT_SYSTEM["Alert & Monitoring System"] end end %% Protection & Monitoring subgraph "Protection & Reliability Systems" subgraph "Electrical Protection" TVS_ARRAY["TVS Surge Protection"] --> AC_DC_FRONTend SNUBBER_CIRCUITS["Snubber Circuits"] --> PFC_MOSFET OVP_OCP["OVP/OCP Protection"] --> POL_MOSFET CURRENT_LIMIT["Current Limiting"] --> HOTSWAP_MOSFET end subgraph "Thermal Management" TEMP_SENSORS["Temperature Sensors"] --> MGMT_MCU HEATSINK_COOLING["Heatsink Cooling"] --> PFC_MOSFET PCB_COPPER_POUR["PCB Copper Pour"] --> POL_MOSFET FORCED_AIR["Forced Air Cooling"] --> COOLING_FANS end subgraph "Monitoring & Diagnostics" POWER_MONITOR["Power Monitor IC"] --> MGMT_MCU FAULT_DETECT["Fault Detection"] --> ALERT_SYSTEM HEALTH_MONITOR["Health Monitoring"] --> PMBUS end end %% Communication & Control MGMT_MCU --> RACK_MANAGER["Rack Management Controller"] RACK_MANAGER --> DATA_CENTER_MGMT["Data Center Management"] PMBUS --> CLOUD_MONITORING["Cloud Monitoring & Analytics"] %% Style Definitions style PFC_MOSFET fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style POL_MOSFET fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style HOTSWAP_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px style COOLING_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MGMT_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the exponential growth of global data volume, high-end data lake storage systems have become the core infrastructure for big data and AI applications. Their power delivery units, serving as the "heart" of the entire system, must provide efficient, stable, and highly reliable power conversion for critical loads such as high-performance compute nodes, massive HDD/SSD arrays, and advanced cooling systems. The selection of power semiconductor devices directly determines the system's power efficiency, power density, thermal performance, and operational uptime. Addressing the stringent requirements of data centers for efficiency, scalability, reliability, and total cost of ownership (TCO), this article centers on scenario-based adaptation to reconstruct the power device selection logic, providing an optimized solution ready for direct implementation.
I. Core Selection Principles and Scenario Adaptation Logic
Core Selection Principles
Voltage and Current Margin: For 12V/48V/54V bus architectures and high-voltage AC inputs (e.g., 277Vac, 480Vac), device ratings must provide substantial derating to handle transients, surges, and ensure long-term reliability.
Ultra-Low Loss is Paramount: Prioritize devices with minimal conduction loss (low Rds(on)) and switching loss (low Qg, Qrr) to maximize PSU efficiency (e.g., Titanium/Platinum standards) and reduce thermal load.
Package and Thermal Compatibility: Select packages (e.g., DFN, TO220F, TO247) based on power stage, thermal management strategy (heatsink, forced air), and required power density.
High Reliability and Ruggedness: Devices must withstand 24/7 continuous operation, exhibit excellent thermal stability, and possess robust immunity against voltage spikes and transients common in datacenter environments.
Scenario Adaptation Logic
Based on the power architecture within a data lake storage rack, device applications are divided into three primary scenarios: High-Current Point-of-Load (POL) Conversion, AC-DC Front-End / PSU, and Hot-Swap & Orbital Power Path Management. Device parameters are matched accordingly to balance performance, cost, and reliability.
II. MOSFET/IGBT Selection Solutions by Scenario
Scenario 1: High-Current, High-Density Point-of-Load (POL) Conversion (48V/54V to 12V/3.3V) – Core Power Stage Device
Recommended Model: VBGQE11506 (N-MOS, 150V, 100A, DFN8x8)
Key Parameter Advantages: Utilizes advanced SGT (Shielded Gate Trench) technology, achieving an ultra-low Rds(on) of 5.7mΩ at 10V Vgs. The 150V rating offers ample margin for 48V/54V intermediate bus applications. A continuous current rating of 100A supports high-power ASICs, memory banks, and multi-drive backplanes.
Scenario Adaptation Value: The compact DFN8x8 package offers extremely low parasitic inductance and excellent thermal performance via a large exposed pad, enabling high switching frequency and power density crucial for space-constrained server blades or storage nodes. Ultra-low conduction loss minimizes heat generation, simplifying thermal design and improving system efficiency.
Scenario 2: AC-DC Front-End / Server PSU Primary Side & PFC Stage – High-Voltage Conversion Device
Recommended Model: VBMB165R12 (N-MOS, 650V, 12A, TO220F)
Key Parameter Advantages: 650V voltage rating is ideal for universal AC input (85-265Vac) and PFC stages. Rds(on) of 680mΩ at 10V Vgs provides a good balance between conduction loss and cost. The Planar technology offers proven reliability and robustness.
Scenario Adaptation Value: The TO220F (fully insulated) package simplifies heatsink mounting and improves isolation safety. Its voltage and current ratings are well-suited for mid-power PSU units (e.g., 1-2kW) within storage enclosures, contributing to high-efficiency power conversion at the rack level.
Scenario 3: Hot-Swap, Backplane Power Distribution, and Fan Drive – High-Current Switching & Control Device
Recommended Model: VBE2605 (P-MOS, -60V, -140A, TO252)
Key Parameter Advantages: Exceptionally low Rds(on) of 4mΩ at 10V Vgs, with a massive continuous current rating of -140A. The -60V rating is perfect for controlling 12V/48V power rails.
Scenario Adaptation Value: The low Rds(on) minimizes voltage drop and power loss in high-current paths like backplane distribution or hot-swap circuits, enhancing overall efficiency. Its high current capability allows it to manage power for entire groups of drives or high-wattage cooling fans. The TO252 package balances current handling with PCB space, suitable for redundant power supply OR-ing or intelligent fan speed control modules.
III. System-Level Design Implementation Points
Drive Circuit Design
VBGQE11506: Requires a dedicated high-current gate driver with adequate peak current capability. Careful layout to minimize power loop and gate loop inductance is critical for stable high-frequency operation.
VBMB165R12: In PFC or bridge topologies, use isolated or high-side drivers with appropriate dead-time control. Snubber networks may be necessary to dampen voltage ringing.
VBE2605: Can be driven by a dedicated hot-swap controller or a driver stage using level-shifted N-MOSFETs. Ensure fast turn-off to limit inrush current during hot-plug events.
Thermal Management Design
Graded Strategy: VBGQE11506 requires a significant PCB copper pour (possibly multi-layer) connected to the thermal pad. VBMB165R12 typically requires an external heatsink. VBE2605 needs a well-designed copper area on the PCB, considering its high current.
Derating & Monitoring: Operate devices at ≤70-80% of their rated current under max ambient temperature (e.g., 40-50°C inlet). Implement temperature monitoring for critical power stages.
EMC and Reliability Assurance
EMI Suppression: Use low-ESR/ESL capacitors very close to the drain-source of switching devices. Properly designed snubbers and input filters are essential for VBM series in AC-DC stages.
Protection Measures: Implement comprehensive OCP, OVP, and OTP using dedicated controllers. Use TVS diodes for surge protection on input lines and gate pins. For VBE2605 in hot-swap, integrate current limiting and circuit breaker functions.
IV. Core Value of the Solution and Optimization Suggestions
The power device selection solution for high-end data lake storage proposed in this article, based on scenario adaptation logic, achieves coverage from high-voltage AC input to low-voltage, high-current POL, and critical power path management. Its core value is reflected in:
Maximized Power Efficiency and Density: The combination of VBGQE11506 for high-frequency, high-current DC-DC conversion and VBMB165R12 for efficient AC-DC front-end minimizes losses at every stage. This contributes directly to lower PUE, reduced operational costs, and enables higher compute/storage density per rack.
Enhanced System Reliability and Availability: The use of robust, derated devices like VBMB165R12 and the high-current capability of VBE2605 for power distribution ensures stable operation under varying loads and transients. This design philosophy minimizes single points of failure in the power delivery network, supporting the high-availability requirements of data lake storage.
Optimal Balance of Performance and TCO: The selected devices represent mature, cost-effective technologies (SGT, Planar, Trench) that deliver high performance without the premium cost of nascent wide-bandgap solutions. This approach provides a superior performance-to-cost ratio, crucial for scaling large-scale data lake deployments.
In the design of power delivery systems for high-end data lake storage, semiconductor device selection is a cornerstone for achieving efficiency, density, and unwavering reliability. This scenario-based solution, by precisely matching device characteristics to specific power chain requirements—from bulk power conversion to precise point-of-load—provides a comprehensive, actionable technical roadmap. As storage systems evolve towards higher rack-level power, liquid cooling, and AI-driven power management, device selection will further emphasize integration with digital control and advanced thermal strategies. Future exploration could focus on the adoption of Silicon Carbide (SiC) MOSFETs for ultra-high-efficiency PFC stages and the integration of smart power stages with PMBus for predictive health monitoring, laying the hardware foundation for the next generation of autonomous, hyper-efficient, and scalable data lake infrastructure.

Detailed Topology Diagrams

AC-DC Front-End & PFC Stage Detail

graph LR subgraph "Three-Phase AC Input Stage" AC_PHASE1["Phase A 480VAC"] --> EMI_FILTER1["EMI Filter"] AC_PHASE2["Phase B 480VAC"] --> EMI_FILTER2["EMI Filter"] AC_PHASE3["Phase C 480VAC"] --> EMI_FILTER3["EMI Filter"] EMI_FILTER1 --> RECTIFIER_BRIDGE["3-Phase Rectifier Bridge"] EMI_FILTER2 --> RECTIFIER_BRIDGE EMI_FILTER3 --> RECTIFIER_BRIDGE end subgraph "PFC Boost Converter Stage" RECTIFIER_BRIDGE --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SWITCH_NODE["PFC Switch Node"] PFC_SWITCH_NODE --> PFC_MOS["VBMB165R12
650V/12A"] PFC_MOS --> HV_BUS["HV DC Bus ~400V"] PFC_CONTROLLER["PFC Controller IC"] --> GATE_DRIVER["Gate Driver IC"] GATE_DRIVER --> PFC_MOS HV_BUS --> VOLTAGE_FEEDBACK["Voltage Feedback"] VOLTAGE_FEEDBACK --> PFC_CONTROLLER end subgraph "DC-DC Isolation & Regulation" HV_BUS --> LLC_RESONANT["LLC Resonant Tank"] LLC_RESONANT --> HF_TRANSFORMER["High-Freq Transformer"] HF_TRANSFORMER --> SYNC_RECT_STAGE["Sync Rectification Stage"] SYNC_RECT_STAGE --> INTER_BUS["48V/54V Intermediate Bus"] LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["LLC Driver"] LLC_DRIVER --> LLC_MOSFETS["LLC MOSFETs"] end subgraph "Protection Circuits" TVS_SUPPRESSORS["TVS Surge Suppressors"] --> AC_PHASE1 RC_SNUBBER["RC Snubber Network"] --> PFC_MOS OVP_CIRCUIT["Over Voltage Protection"] --> HV_BUS CURRENT_SENSE["Current Sense Circuit"] --> PFC_CONTROLLER end style PFC_MOS fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Point-of-Load Conversion & Hot-Swap Management Detail

graph LR subgraph "Hot-Swap Power Path Management" BACKPLANE_48V["48V Backplane"] --> HOTSWAP_IN["Hot-Swap Input"] HOTSWAP_IN --> HS_SENSE["Current Sense Resistor"] HS_SENSE --> HS_MOSFET["VBE2605
-60V/-140A"] HS_MOSFET --> POL_INPUT["POL Input"] HOTSWAP_IC["Hot-Swap Controller"] --> HS_DRIVER["Driver Circuit"] HS_DRIVER --> HS_MOSFET POL_INPUT --> VOLTAGE_MONITOR["Voltage Monitor"] VOLTAGE_MONITOR --> HOTSWAP_IC end subgraph "High-Current POL Buck Converter" POL_INPUT --> INPUT_CAPS["Input Capacitors"] INPUT_CAPS --> POL_MOSFET_HIGH["VBGQE11506
High-Side Switch"] POL_MOSFET_HIGH --> SWITCH_NODE["Switch Node"] SWITCH_NODE --> POL_INDUCTOR["Power Inductor"] POL_INDUCTOR --> OUTPUT_CAPS["Output Capacitors"] OUTPUT_CAPS --> POL_OUTPUT["12V/5V/3.3V Output"] SWITCH_NODE --> POL_MOSFET_LOW["VBGQE11506
Low-Side Sync Rect"] POL_MOSFET_LOW --> GND_POL["POL Ground"] POL_CONTROLLER["POL Controller"] --> POL_GATE_DRIVER["Gate Driver"] POL_GATE_DRIVER --> POL_MOSFET_HIGH POL_GATE_DRIVER --> POL_MOSFET_LOW POL_OUTPUT --> FEEDBACK["Voltage Feedback"] FEEDBACK --> POL_CONTROLLER end subgraph "Load Distribution" POL_OUTPUT --> COMPUTE_LOAD["Compute ASIC/CPU"] POL_OUTPUT --> MEMORY_BANK["Memory Bank"] POL_OUTPUT --> STORAGE_CONTROLLER["Storage Controller"] POL_OUTPUT --> NETWORK_IF["Network Interface"] end subgraph "Thermal Management" POL_MOSFET_HIGH --> THERMAL_PAD["DFN8x8 Thermal Pad"] THERMAL_PAD --> PCB_COPPER["Multi-Layer Copper Pour"] POL_MOSFET_LOW --> THERMAL_PAD TEMP_SENSOR_POL["Temperature Sensor"] --> POL_CONTROLLER end style HS_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px style POL_MOSFET_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style POL_MOSFET_LOW fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Cooling System & Power Distribution Detail

graph LR subgraph "Cooling System Power Distribution" COOLING_BUS["48V Cooling Bus"] --> FAN_CONTROLLER["Fan Speed Controller"] FAN_CONTROLLER --> FAN_DRIVER_STAGE["Driver Stage"] FAN_DRIVER_STAGE --> FAN_MOSFET["VBE2605
Fan Control MOSFET"] FAN_MOSFET --> FAN_ARRAY["High-Speed Fan Array"] COOLING_BUS --> PUMP_CONTROLLER["Pump Controller"] PUMP_CONTROLLER --> PUMP_DRIVER["Pump Driver"] PUMP_DRIVER --> PUMP_MOSFET["VBE2605
Pump Control MOSFET"] PUMP_MOSFET --> LIQUID_PUMP["Liquid Cooling Pump"] end subgraph "Thermal Management Hierarchy" subgraph "Level 1: Critical Components" POL_MOSFETS["POL MOSFETs"] --> LIQUID_COLD_PLATE["Liquid Cold Plate"] CPU_GPU_UNITS["CPU/GPU Units"] --> DIRECT_LIQUID["Direct Liquid Cooling"] end subgraph "Level 2: Power Components" PFC_MOSFETS["PFC/LLC MOSFETs"] --> FORCED_AIR_HEATSINK["Forced Air Heatsink"] HS_MOSFETS["Hot-Swap MOSFETs"] --> PCB_HEATSINK["PCB Mounted Heatsink"] end subgraph "Level 3: Control & Support" CONTROL_ICS["Control ICs"] --> NATURAL_CONVECTION["Natural Convection"] SENSOR_CIRCUITS["Sensor Circuits"] --> AIRFLOW_COOLING["Airflow Cooling"] end end subgraph "Temperature Monitoring & Control" TEMP_SENSOR_1["Inlet Air Sensor"] --> MGMT_MCU["Management MCU"] TEMP_SENSOR_2["Component Temp Sensor"] --> MGMT_MCU TEMP_SENSOR_3["Exhaust Air Sensor"] --> MGMT_MCU MGMT_MCU --> PWM_CONTROL["PWM Control Signals"] PWM_CONTROL --> FAN_CONTROLLER PWM_CONTROL --> PUMP_CONTROLLER MGMT_MCU --> ALERT_OUTPUT["Temperature Alerts"] ALERT_OUTPUT --> DCIM_SYSTEM["DCIM System"] end subgraph "Power Monitoring & Efficiency" POWER_METER["Power Meter IC"] --> MGMT_MCU CURRENT_SENSE_LOOP["Current Sense Loops"] --> POWER_METER VOLTAGE_MONITOR_POINTS["Voltage Monitor Points"] --> POWER_MCU["Power MCU"] POWER_MCU --> EFFICIENCY_CALC["Efficiency Calculation"] EFFICIENCY_CALC --> PUE_REPORTING["PUE Reporting"] end style FAN_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px style PUMP_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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