Data Storage

Your present location > Home page > Data Storage
Intelligent Power MOSFET Selection Solution for High-End Data Storage Systems – Design Guide for High-Efficiency, High-Density, and High-Reliability Power Architectures
Data Storage System Power MOSFET Topology Diagram

High-End Data Storage System Power Architecture Overall Topology

graph LR %% AC-DC Front-End Conversion subgraph "AC-DC Front-End & PFC/LLC Stage" AC_IN["AC Input 85-264VAC"] --> EMI_FILTER["EMI Filter & Surge Protection"] EMI_FILTER --> RECTIFIER["Three-Phase/Bridge Rectifier"] RECTIFIER --> HV_DC["High-Voltage DC Bus 400-800V"] HV_DC --> PFC_STAGE["PFC Boost Converter"] subgraph "PFC Stage MOSFETs" Q_PFC1["VBM16R11S
600V/11A
TO-220"] Q_PFC2["VBM16R11S
600V/11A
TO-220"] end PFC_STAGE --> Q_PFC1 PFC_STAGE --> Q_PFC2 Q_PFC1 --> PFC_OUT["PFC Output ~400VDC"] Q_PFC2 --> PFC_OUT PFC_OUT --> LLC_STAGE["LLC Resonant Converter"] subgraph "LLC Primary MOSFETs" Q_LLC1["VBM16R11S
600V/11A
TO-220"] Q_LLC2["VBM16R11S
600V/11A
TO-220"] end LLC_STAGE --> Q_LLC1 LLC_STAGE --> Q_LLC2 Q_LLC1 --> GND_PRI Q_LLC2 --> GND_PRI end %% Intermediate Bus & Distribution subgraph "Intermediate Bus & Synchronous Rectification" LLC_XFMR["LLC High-Frequency Transformer"] --> SR_NODE["Synchronous Rectification Node"] subgraph "Synchronous Rectification MOSFETs" Q_SR1["VBGE1256N
250V/25A
TO-252"] Q_SR2["VBGE1256N
250V/25A
TO-252"] end SR_NODE --> Q_SR1 SR_NODE --> Q_SR2 Q_SR1 --> INT_FILTER["Intermediate Filter"] Q_SR2 --> INT_FILTER INT_FILTER --> INT_BUS["Intermediate Bus
12V/48V"] INT_BUS --> DC_DC_CONVERTERS["Multiple DC-DC Converters"] end %% Point-of-Load Power Delivery subgraph "Point-of-Load & Load Power Rails" subgraph "CPU/ASIC Power Rails" POL_CPU["PoL Buck Converter"] --> Q_CPU1["VBR9N1219
20V/4.8A
TO-92"] Q_CPU1 --> CPU_RAIL["CPU Core Voltage
0.8-1.8V"] end subgraph "Memory Power Rails" POL_MEM["PoL Buck Converter"] --> Q_MEM1["VBR9N1219
20V/4.8A
TO-92"] Q_MEM1 --> MEM_RAIL["Memory Voltage
1.2-3.3V"] end subgraph "Storage Drive Power" POL_SSD["PoL Buck Converter"] --> Q_SSD1["VBR9N1219
20V/4.8A
TO-92"] Q_SSD1 --> SSD_RAIL["SSD Power
3.3V/5V"] POL_HDD["Load Switch"] --> Q_HDD1["VBR9N1219
20V/4.8A
TO-92"] Q_HDD1 --> HDD_RAIL["HDD Power
12V"] end end %% Control & Monitoring subgraph "System Control & Management" MAIN_MCU["System Management Controller"] --> PFC_CTRL["PFC Controller"] MAIN_MCU --> LLC_CTRL["LLC Controller"] MAIN_MCU --> POL_CTRL["PoL Controller Array"] subgraph "Monitoring & Protection" VOLT_SENSE["Voltage Monitoring"] CURR_SENSE["Current Sensing"] TEMP_SENSE["Temperature Sensors"] OCP_OVP["OCP/OVP Circuits"] end VOLT_SENSE --> MAIN_MCU CURR_SENSE --> MAIN_MCU TEMP_SENSE --> MAIN_MCU OCP_OVP --> MAIN_MCU MAIN_MCU --> FAN_CTRL["Fan Speed Control"] MAIN_MCU --> ALARM["System Alarms"] end %% Thermal Management subgraph "Tiered Thermal Management" TIER1["Tier 1: Forced Air + Heatsinks"] --> Q_PFC1 TIER1 --> Q_LLC1 TIER2["Tier 2: PCB Thermal Design"] --> Q_SR1 TIER2 --> POL_CTRL TIER3["Tier 3: Natural Convection"] --> Q_CPU1 TIER3 --> Q_MEM1 COOLING_FANS["Cooling Fans"] --> TIER1 HEATSINKS["Heatsinks"] --> TIER1 end %% Communication & Redundancy subgraph "Communication & Redundancy" MAIN_MCU --> I2C_BUS["I2C/PMBus"] MAIN_MCU --> REDUNDANCY["Redundant Power Control"] I2C_BUS --> PSU_MON["PSU Monitoring"] I2C_BUS --> FAN_MON["Fan Monitoring"] REDUNDANCY --> PSU_SYNC["PSU Sync & Load Share"] end %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_CPU1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MAIN_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the explosive growth of global data and the increasing demands of cloud computing, high-end data storage systems require power architectures that deliver exceptional efficiency, power density, and unwavering reliability. The power MOSFET, as the fundamental switching element within server power supplies (PSUs), point-of-load (PoL) converters, and active cooling subsystems, is critical for minimizing energy loss, managing thermal loads, and ensuring 24/7 operational integrity. Addressing the multi-rail, high-current, and stringent availability requirements of modern storage arrays and servers, this article presents a targeted MOSFET selection and implementation strategy based on a scenario-driven, system-optimized approach.
I. Overall Selection Principles: Performance, Density, and Reliability Balance
Selection must prioritize a holistic balance between electrical performance, thermal capability, and package footprint to match the specific voltage domain and power stage requirements.
Voltage and Current Margin Design: For AC-DC stages (PFC, LLC), voltage rating must withstand rectified high-voltage lines with >30-40% margin. For DC-DC stages, select based on intermediate bus voltage (e.g., 12V, 48V) with similar margin. Current rating must support both continuous and peak loads (e.g., HDD spin-up), with derating applied based on thermal conditions.
Ultra-Low Loss Priority: Conduction loss (Rds(on)) is paramount in high-current paths. Switching loss (influenced by Qg, Coss) dominates in high-frequency switching nodes. The optimal device minimizes total loss (conduction + switching) for its target frequency.
Package and Thermal Co-Design: High-power stages require packages with excellent thermal performance (e.g., TO-220, TO-263) often paired with heatsinks. For PoL and board-mounted PSUs, space-constrained packages (e.g., SOP8, TO-252) with low thermal resistance are essential for achieving high power density.
Ruggedness and Longevity: Data center environments demand components with high avalanche energy rating, strong body diode robustness, and stable parameters over extended operation to meet MTBF targets.
II. Scenario-Specific MOSFET Selection Strategies
The power tree of a high-end storage system is segmented into primary AC-DC conversion, intermediate DC-DC distribution, and final load power delivery, each requiring tailored MOSFET solutions.
Scenario 1: Primary-Side High-Voltage Conversion & PFC Stage (450-800V)
This stage handles rectified AC input and power factor correction, requiring high-voltage blocking capability and good switching performance.
Recommended Model: VBM16R11S (Single-N, 600V, 11A, TO-220)
Parameter Advantages:
Utilizes Super Junction Multi-EPI technology, offering an excellent balance of low specific on-resistance (380 mΩ @10V) and low gate charge for its voltage class.
600V rating provides solid margin for universal AC input (85-264VAC) applications.
TO-220 package facilitates robust thermal management via heatsinking.
Scenario Value:
Ideal for PFC boost converters and LLC resonant converter primary switches, enabling high-efficiency (>95% Platinum/Titanium PSU standards) first-stage power conversion.
High voltage capability ensures reliability against line transients.
Scenario 2: Intermediate Bus & High-Current Synchronous Rectification (100-250V)
This stage converts the high-voltage DC to an intermediate bus (e.g., 12V/48V) or performs synchronous rectification in LLC converters, demanding very low conduction loss.
Recommended Model: VBGE1256N (Single-N, 250V, 25A, TO-252)
Parameter Advantages:
Features advanced Shielded Gate Trench (SGT) technology, achieving an exceptionally low Rds(on) of 60 mΩ @10V.
High continuous current (25A) supports high power throughput.
TO-252 (DPAK) package offers a compact footprint with good power dissipation capability.
Scenario Value:
Excellent choice for the synchronous rectification MOSFETs in LLC resonant converters or for high-current DC-DC converter switches, directly boosting full-load efficiency.
Compact package supports higher power density designs in board-mounted power modules.
Scenario 3: Point-of-Load (PoL) & Low-Voltage High-Current Rails (≤20V)
This stage powers core loads like CPUs, ASICs, memory, and storage devices (SSDs/HDDs), requiring ultra-low Rds(on) for minimal voltage drop and loss at low voltages.
Recommended Model: VBR9N1219 (Single-N, 20V, 4.8A, TO-92)
Parameter Advantages:
Extremely low Rds(on) down to 18 mΩ @10V (21 mΩ @4.5V), minimizing conduction loss even at lower gate drive voltages.
Low gate threshold voltage (Vth=0.6V) enables efficient drive from low-voltage logic.
TO-92 package provides a through-hole option for prototyping or cost-sensitive, space-allowed designs in auxiliary low-power rails.
Scenario Value:
Perfect for low-voltage, high-current buck converters (e.g., 12V to 1.8V, 5V to 3.3V) where conduction loss is dominant.
Suitable for power switching and load distribution on backplanes or drive carrier boards, enhancing overall system efficiency.
III. Key Implementation Points for System Design
Drive Circuit Optimization:
For high-voltage/high-current MOSFETs (VBM16R11S, VBGE1256N), use dedicated high-speed gate driver ICs to minimize switching loss and prevent shoot-through.
For low-voltage PoL MOSFETs (VBR9N1219), ensure clean, low-impedance gate drive traces from the PWM controller.
Thermal Management Design:
Implement a tiered strategy: forced-air cooling with heatsinks for primary-side TO-220 devices; optimized PCB copper pours (≥2 oz.) with thermal vias for DPAK and SOP packages; natural convection for low-power devices.
EMC and Reliability Enhancement:
Employ snubber circuits and careful layout to manage high dv/dt nodes in primary-side circuits.
Implement comprehensive protection: OCP, OVP, OTP at all power stages. Use TVS diodes for surge protection on input/output ports.
IV. Solution Value and Expansion Recommendations
Core Value:
Maximized Power Efficiency: The combination of SJ, SGT, and low-voltage Trench MOSFETs optimizes losses across the entire power chain, supporting data center PUE goals.
High-Density Power Delivery: Selected packages enable compact PSU and PoL designs, allowing for greater storage capacity or compute resources within the same rack unit.
Enterprise-Grade Reliability: High-voltage margins, robust technologies, and targeted thermal design ensure operation in demanding 24/7 environments.
Optimization and Adjustment Recommendations:
Higher Power: For 3kW+ server PSUs, consider higher-current variants or parallel devices.
Higher Density: For next-generation blade storage, migrate to advanced surface-mount packages (e.g., DFN, PowerFLAT) for all stages.
Advanced Topologies: For 48V direct conversion architectures, select MOSFETs optimized for this specific voltage range (e.g., 80-100V rated).
The strategic selection of power MOSFETs is a cornerstone in building efficient, dense, and reliable power systems for high-end data storage. The tiered, scenario-based approach outlined here provides a clear pathway to optimize performance from the AC inlet to the silicon load. As storage densities and processor demands escalate, future designs will increasingly adopt wide-bandgap semiconductors (GaN/SiC) for the highest frequency and efficiency stages, with advanced silicon MOSFETs like those selected here continuing to play a vital role in the broader power delivery network.

Detailed Topology Diagrams

Primary-Side High-Voltage PFC/LLC Stage Detail

graph LR subgraph "Three-Phase PFC Boost Converter" AC_IN["AC Input"] --> RECT["Rectifier Bridge"] RECT --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] PFC_SW_NODE --> Q_PFC_H["VBM16R11S High-Side"] PFC_SW_NODE --> Q_PFC_L["VBM16R11S Low-Side"] Q_PFC_H --> PFC_OUTPUT["PFC Output 400VDC"] Q_PFC_L --> PFC_GND PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> Q_PFC_H PFC_DRIVER --> Q_PFC_L PFC_OUTPUT --> VOLT_FB["Voltage Feedback"] VOLT_FB --> PFC_CONTROLLER end subgraph "LLC Resonant Converter Primary" PFC_OUTPUT --> LLC_RES_TANK["LLC Resonant Tank
Lr, Cr, Lm"] LLC_RES_TANK --> LLC_XFMR_PRI["Transformer Primary"] LLC_XFMR_PRI --> LLC_SW_NODE["LLC Switching Node"] LLC_SW_NODE --> Q_LLC_H["VBM16R11S High-Side"] LLC_SW_NODE --> Q_LLC_L["VBM16R11S Low-Side"] Q_LLC_H --> LLC_BUS Q_LLC_L --> LLC_GND LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["Gate Driver"] LLC_DRIVER --> Q_LLC_H LLC_DRIVER --> Q_LLC_L CS_TRANSFORMER["Current Sense Transformer"] --> LLC_CONTROLLER end subgraph "Protection Circuits" SNUBBER["RCD Snubber Circuit"] --> Q_PFC_H SNUBBER --> Q_LLC_H TVS_ARRAY["TVS Protection"] --> PFC_DRIVER TVS_ARRAY --> LLC_DRIVER OVP_CIRCUIT["OVP Circuit"] --> PFC_CONTROLLER OVP_CIRCUIT --> LLC_CONTROLLER end style Q_PFC_H fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LLC_H fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Synchronous Rectification & Intermediate Bus Detail

graph LR subgraph "LLC Synchronous Rectification Stage" LLC_XFMR_SEC["Transformer Secondary"] --> SR_CENTER_TAP["Center Tap"] SR_CENTER_TAP --> SR_HIGH_SIDE["High-Side SR Node"] SR_CENTER_TAP --> SR_LOW_SIDE["Low-Side SR Node"] SR_HIGH_SIDE --> Q_SR_HS["VBGE1256N
High-Side SR"] SR_LOW_SIDE --> Q_SR_LS["VBGE1256N
Low-Side SR"] Q_SR_HS --> OUTPUT_INDUCTOR["Output Inductor"] Q_SR_LS --> OUTPUT_INDUCTOR OUTPUT_INDUCTOR --> FILTER_CAP["Filter Capacitors"] FILTER_CAP --> INT_BUS_OUT["Intermediate Bus 12V/48V"] SR_CONTROLLER["SR Controller"] --> SR_DRIVER["Synchronous Driver"] SR_DRIVER --> Q_SR_HS SR_DRIVER --> Q_SR_LS end subgraph "Intermediate Bus Distribution" INT_BUS_OUT --> DISTRIBUTION_BUS["Distribution Bus"] DISTRIBUTION_BUS --> POL_MODULE1["PoL Module 1"] DISTRIBUTION_BUS --> POL_MODULE2["PoL Module 2"] DISTRIBUTION_BUS --> POL_MODULE3["PoL Module 3"] DISTRIBUTION_BUS --> POL_MODULE4["PoL Module 4"] POL_MODULE1 --> LOAD1["CPU/ASIC Load"] POL_MODULE2 --> LOAD2["Memory Load"] POL_MODULE3 --> LOAD3["SSD Array"] POL_MODULE4 --> LOAD4["HDD Array"] end subgraph "Current Sharing & Protection" CURRENT_SHARING["Current Sharing Circuit"] --> Q_SR_HS CURRENT_SHARING --> Q_SR_LS BALANCE_CONTROL["Balance Controller"] --> CURRENT_SHARING OCP_CIRCUIT["OCP Circuit"] --> SR_CONTROLLER THERMAL_SENSOR["Thermal Sensor"] --> SR_CONTROLLER end style Q_SR_HS fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Point-of-Load & Low-Voltage Rails Detail

graph LR subgraph "Multi-Phase CPU/ASIC Buck Converter" INPUT_12V["12V Input"] --> PHASE1["Phase 1 Buck"] INPUT_12V --> PHASE2["Phase 2 Buck"] INPUT_12V --> PHASE3["Phase 3 Buck"] subgraph "Phase 1 Power Stage" HS1["VBR9N1219 High-Side"] --> SW_NODE1["Switching Node"] LS1["VBR9N1219 Low-Side"] --> SW_NODE1 end subgraph "Phase 2 Power Stage" HS2["VBR9N1219 High-Side"] --> SW_NODE2["Switching Node"] LS2["VBR9N1219 Low-Side"] --> SW_NODE2 end subgraph "Phase 3 Power Stage" HS3["VBR9N1219 High-Side"] --> SW_NODE3["Switching Node"] LS3["VBR9N1219 Low-Side"] --> SW_NODE3 end SW_NODE1 --> INDUCTOR1["Output Inductor"] SW_NODE2 --> INDUCTOR2["Output Inductor"] SW_NODE3 --> INDUCTOR3["Output Inductor"] INDUCTOR1 --> CPU_OUT["CPU Core Voltage"] INDUCTOR2 --> CPU_OUT INDUCTOR3 --> CPU_OUT CPU_OUT --> FILTER_CAP["MLCC & Polymer Caps"] MULTI_PHASE_CTRL["Multi-Phase Controller"] --> DRIVER1["Gate Driver"] DRIVER1 --> HS1 DRIVER1 --> LS1 MULTI_PHASE_CTRL --> DRIVER2["Gate Driver"] DRIVER2 --> HS2 DRIVER2 --> LS2 MULTI_PHASE_CTRL --> DRIVER3["Gate Driver"] DRIVER3 --> HS3 DRIVER3 --> LS3 end subgraph "Memory & Storage Power Rails" MEM_BUCK["Memory Buck Converter"] --> Q_MEM_HS["VBR9N1219 High-Side"] MEM_BUCK --> Q_MEM_LS["VBR9N1219 Low-Side"] Q_MEM_HS --> MEM_OUT["Memory Power 1.2V/3.3V"] SSD_BUCK["SSD Buck Converter"] --> Q_SSD_HS["VBR9N1219 High-Side"] SSD_BUCK --> Q_SSD_LS["VBR9N1219 Low-Side"] Q_SSD_HS --> SSD_OUT["SSD Power 3.3V/5V"] HDD_SWITCH["HDD Load Switch"] --> Q_HDD["VBR9N1219"] Q_HDD --> HDD_OUT["HDD Power 12V"] end subgraph "Voltage Monitoring & Sequencing" VOLTAGE_MON["Voltage Monitor IC"] --> CPU_OUT VOLTAGE_MON --> MEM_OUT VOLTAGE_MON --> SSD_OUT VOLTAGE_MON --> HDD_OUT SEQUENCER["Power Sequencer"] --> MEM_BUCK SEQUENCER --> SSD_BUCK SEQUENCER --> HDD_SWITCH end style HS1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_MEM_HS fill:#fff3e0,stroke:#ff9800,stroke-width:2px
Download PDF document
Download now:VBM16R11S

Sample Req

Online

Telephone

400-655-8788

WeChat

Topping

Sample Req
Online
Telephone
WeChat