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Preface: Powering the Uninterrupted Data Pulse – Systems Thinking for SAN Power Integrity
SAN Power System Topology Diagram

SAN Power System Overall Topology Diagram

graph LR %% Input Power Stage subgraph "Input Power Conversion Stage" AC_IN["3-Phase 400VAC Input
Data Center Power"] --> PFC_IN["EMI Filter & Rectifier"] PFC_IN --> PFC_STAGE["Totem-Pole PFC Stage"] subgraph "Primary Side SiC MOSFET Array" Q_PFC1["VBP165C70-4L
650V/70A SiC"] Q_PFC2["VBP165C70-4L
650V/70A SiC"] end PFC_STAGE --> Q_PFC1 PFC_STAGE --> Q_PFC2 Q_PFC1 --> HV_BUS["High-Voltage DC Bus
~800VDC"] Q_PFC2 --> HV_BUS HV_BUS --> LLC_STAGE["LLC Resonant Converter"] LLC_STAGE --> ISO_TRANS["High-Frequency Transformer"] end %% Intermediate Bus Distribution subgraph "Intermediate Bus Distribution & Control" ISO_TRANS --> DC_DC["Isolated DC-DC Converter"] DC_DC --> INT_BUS["Intermediate Bus
12V/5V"] subgraph "Intelligent Power Switches" SW_CTRL1["VBE2308A
12V Rail Control"] SW_CTRL2["VBE2308A
5V Rail Control"] SW_SSD["VBE2308A
SSD Shelf Power"] SW_MEM["VBE2308A
Memory Module Power"] end INT_BUS --> SW_CTRL1 INT_BUS --> SW_CTRL2 INT_BUS --> SW_SSD INT_BUS --> SW_MEM SW_CTRL1 --> POL_12V["12V PoL Rails"] SW_CTRL2 --> POL_5V["5V PoL Rails"] SW_SSD --> SSD_ARRAY["SSD Storage Array"] SW_MEM --> MEM_MODULES["Memory Modules"] end %% Point-of-Load Regulation subgraph "Point-of-Load (PoL) Voltage Regulation" POL_12V --> BUCK_CONVERTERS["Synchronous Buck Converters"] subgraph "Dual N-MOSFET Array" Q_BUCK1["VBI3638
Dual 60V/7A"] Q_BUCK2["VBI3638
Dual 60V/7A"] Q_BUCK3["VBI3638
Dual 60V/7A"] Q_BUCK4["VBI3638
Dual 60V/7A"] end BUCK_CONVERTERS --> Q_BUCK1 BUCK_CONVERTERS --> Q_BUCK2 BUCK_CONVERTERS --> Q_BUCK3 BUCK_CONVERTERS --> Q_BUCK4 Q_BUCK1 --> CPU_PWR["CPU/ASIC Power
0.8V-1.2V"] Q_BUCK2 --> IO_PWR["I/O Power Rails
1.8V-3.3V"] Q_BUCK3 --> MEM_PWR["Memory Power
1.2V-2.5V"] Q_BUCK4 --> PHY_PWR["PHY Interface Power
0.9V-1.0V"] end %% Control & Management System subgraph "Digital Power Management System" MGMT_MCU["System Management MCU"] --> PMBUS["PMBus/I2C Interface"] PMBUS --> PFC_CTRL["PFC/LLC Controller"] PMBUS --> SW_SEQ["Power Sequencing Controller"] PMBUS --> POL_CTRL["PoL Controller Array"] PFC_CTRL --> GATE_DRV_PFC["High-Speed SiC Gate Driver"] SW_SEQ --> GATE_DRV_SW["Logic-Level Gate Driver"] POL_CTRL --> GATE_DRV_POL["Synchronous Buck Driver"] GATE_DRV_PFC --> Q_PFC1 GATE_DRV_SW --> SW_CTRL1 GATE_DRV_POL --> Q_BUCK1 TELEMETRY["Power Telemetry"] --> MGMT_MCU TEMP_SENSORS["Temperature Sensors"] --> TELEMETRY CURRENT_SENSE["Current Monitoring"] --> TELEMETRY VOLT_MON["Voltage Monitoring"] --> TELEMETRY end %% Thermal Management subgraph "Hierarchical Thermal Management" COOLING_LEVEL1["Level 1: Forced Air Cooling"] --> HEATSINK_SIC["SiC MOSFET Heatsink"] COOLING_LEVEL2["Level 2: PCB Conduction"] --> THERMAL_VIAS["Thermal Vias & Copper Pours"] COOLING_LEVEL3["Level 3: System Airflow"] --> ENCLOSURE["Rack Airflow Management"] HEATSINK_SIC --> Q_PFC1 THERMAL_VIAS --> Q_BUCK1 ENCLOSURE --> SW_CTRL1 end %% Protection Circuits subgraph "Protection & Reliability Circuits" RC_SNUBBER["RC Snubber Network"] --> Q_PFC1 TVS_ARRAY["TVS Protection"] --> GATE_DRV_PFC INRUSH_LIM["Inrush Current Limiter"] --> SW_CTRL1 GATE_CLAMP["Gate Protection Clamp"] --> Q_BUCK1 FAULT_DETECT["Fault Detection"] --> MGMT_MCU FAULT_DETECT --> SHUTDOWN["System Shutdown Control"] end %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SW_CTRL1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_BUCK1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style MGMT_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the mission-critical realm of high-end Fiber Channel Storage Area Networks (SAN), the power delivery system is far more than a simple utility converter. It is the silent, unwavering "digital heart pacemaker" for data storage and retrieval. Its core mandates—extreme reliability, pinnacle efficiency, high power density, and intelligent power management—are fundamentally anchored in the performance of its power conversion and distribution chain. This article adopts a holistic, co-design approach to address the core challenge within a SAN power shelf: how to select the optimal power MOSFET combination for key nodes—including high-efficiency DC-DC conversion, intelligent intermediate bus distribution, and point-of-load (PoL) regulation—under the strict constraints of 99.999%+ availability, thermal management in confined racks, and stringent noise immunity.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The Efficiency Core: VBP165C70-4L (650V SiC MOSFET, 70A, TO-247-4L) – High-Frequency Isolated DC-DC Primary Side / PFC Stage Switch
Core Positioning & Topology Deep Dive: Engineered for the critical first power conversion stage, such as in a 3-Phase Totem-Pole PFC or a high-frequency LLC resonant converter. Its Silicon Carbide (SiC) technology is pivotal for achieving ultra-high switching frequencies (e.g., 200kHz-500kHz+), enabling dramatic shrinkage of magnetics and capacitors. The 650V rating with low Rds(on) (30mΩ) is ideal for 400VAC three-phase input or high-voltage DC bus architectures.
Key Technical Parameter Analysis:
SiC Superiority: Extremely low Qg and Qrr compared to Si superjunction MOSFETs, minimizing switching losses at high frequencies. This directly translates to higher system efficiency (>98% target) and reduced thermal stress.
Kelvin Source (4-Lead) Advantage: The TO-247-4L package separates power source and driver source connections, eliminating common source inductance. This is critical for harnessing SiC's ultimate switching speed, reducing voltage overshoot, and improving EMI performance.
Selection Trade-off: While premium, the investment in this SiC device is justified by the system-level gains in power density and efficiency, reducing cooling requirements and operating costs (OPEX) in 24/7 data center environments.
2. The Intelligent Distribution Hub: VBE2308A (-30V P-MOS, -70A, TO-252) – Intermediate Bus (e.g., 12V/5V) High-Side Intelligent Power Switch
Core Positioning & System Benefit: Serves as the master high-side switch for intelligent power sequencing, fault isolation, and hot-swap control of secondary power rails. Its exceptionally low Rds(on) of 7mΩ @10V minimizes voltage drop and conduction loss on the critical power path to downstream PoL converters.
Application & PCB Value:
Sequencing & Fault Management: Enables controlled power-up/power-down of different storage controller zones or SSD shelves to avoid inrush current issues. Can be swiftly shut down by management controllers during fault conditions.
P-Channel Simplification: As a high-side switch on the positive bus, it is controlled directly by low-voltage logic (active-low), eliminating the need for charge pumps or level translators. This results in a simple, robust, and space-efficient control circuit for multi-rail management.
Thermal Performance: The low Rds(on) combined with the TO-252 package's thermal capability ensures cool operation even under high continuous loads, enhancing long-term reliability.
3. The Point-of-Load Supply Expert: VBI3638 (Dual 60V N-MOS, 7A, SOT89-6) – Synchronous Buck Converter Low-Side / High-Side Pair
Core Positioning & System Integration Advantage: The dual N-MOSFETs in an ultra-compact SOT89-6 package are the ideal building block for high-density, multi-phase synchronous buck converters powering ASICs, CPUs, and memory within storage controllers and adapters.
Key Technical Parameter Analysis:
Dual Integration for Space Savings: Replaces two discrete MOSFETs, drastically saving PCB area in densely populated PoL regions, which is crucial for add-in cards and mezzanine boards.
Optimized for Low Voltage, High Frequency: With Rds(on) of 33mΩ @10V and 60V rating, it offers excellent performance for input rails from 12V down to 5V, operating at high PWM frequencies (500kHz-1MHz+) to achieve fast transient response and further reduce output filter size.
Matched Characteristics: Being from the same die lot in one package, the dual MOSFETs typically have well-matched switching and conduction parameters, leading to more balanced current sharing and optimized converter performance.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Loop Synergy
SiC Driver & Control: Driving the VBP165C70-4L requires a dedicated, high-speed, high-current gate driver with negative turn-off voltage capability to ensure reliable operation and mitigate crosstalk. Its switching must be tightly synchronized with the digital PWM controller (e.g., for LLC or PFC).
PoL Controller Coordination: The dual VBI3638 must be driven by a synchronous buck controller with adaptive dead-time control to prevent shoot-through, maximizing efficiency.
Digital Power Management (PMBus): The gate of the VBE2308A should be controlled by a system management controller via PMBus/I2C, enabling programmable sequencing, current monitoring, and telemetry for predictive health analysis.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Air Cooling): The VBP165C70-4L (SiC), though efficient, handles high power and may be the primary heat source in the PFC/LLC stage, requiring a dedicated heatsink within the power supply unit's air stream.
Secondary Heat Source (PCB Conduction + Airflow): The VBE2308A and VBI3638 arrays will dissipate heat through large copper pours and thermal vias on the PCB into the overall system airflow. Careful layout is essential to avoid hot spots on controller boards.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
SiC Switching: Utilize low-inductance power loops and optimized RC snubbers for the VBP165C70-4L to manage voltage overshoot from parasitic inductance.
Hot-Swap & Inrush: For circuits involving VBE2308A, implement inrush current limiting (e.g., with a series NTC or active circuit) to protect against capacitive load charging.
Enhanced Gate Protection: All gate drives should be physically close to the MOSFETs. Use gate resistors to fine-tune switching speed vs. EMI. TVS diodes or Zener clamps on the gates of VBI3638 are recommended for PoL environments sensitive to noise.
Derating Practice:
Voltage Derating: Ensure VDS stress on VBP165C70-4L remains below 80% of 650V under worst-case line transients. For VBI3638, ensure sufficient margin above the input rail (e.g., 12V rail uses 60V part).
Thermal Derating: Design for a maximum junction temperature (Tj) well below 125°C for all devices, using thermal simulation based on actual power loss and system airflow to ensure lifetime reliability.
III. Quantifiable Perspective on Scheme Advantages
Quantifiable Efficiency Gain: Employing VBP165C70-4L (SiC) in the front-end PFC/LLC stage can improve efficiency by 1-2% absolute compared to best-in-class Si solutions. For a 3kW power shelf, this reduces power loss by 30-60W, lowering cooling demands and operating costs.
Quantifiable Power Density Improvement: Using the integrated dual VBI3638 for PoL converters can save over 40% PCB area per phase compared to discrete SOT-23/SOP-8 solutions, enabling more phases or functionality in the same board space.
Quantifiable Reliability & Management Enhancement: The intelligent switch VBE2308A provides a hardware-enforced point of control and isolation, allowing for rapid fault containment and sophisticated power management policies, improving overall system availability (MTBF).
IV. Summary and Forward Look
This scheme constructs a robust, efficient, and intelligent power chain for high-end SAN equipment, addressing conversion, distribution, and delivery with optimized devices.
Energy Conversion Level – Focus on "Cutting-Edge Efficiency": Leverage SiC technology to push efficiency and frequency limits, reducing system size and loss.
Power Distribution Level – Focus on "Intelligent Control & Robustness": Utilize low-loss P-MOS for simple, reliable, and manageable power routing on critical intermediate buses.
Point-of-Load Level – Focus on "High-Density Integration": Adopt highly integrated dual MOSFETs to achieve compact, high-performance voltage regulation for sensitive loads.
Future Evolution Directions:
Integrated Power Stages (IPS): Migration to PoL modules that integrate the VBI3638-type MOSFETs with drivers, protection, and digital telemetry, further simplifying design.
GaN for Ultra-High Density: For next-generation, blade-level storage servers, GaN HEMTs could be considered for even higher frequency PoL and front-end conversion, pushing power density to new extremes.
AI-Driven Power Management: Deeper integration of power switch telemetry with system management software for dynamic, predictive optimization of power allocation and cooling based on real-time workload.

Detailed Topology Diagrams

SiC PFC/LLC Primary Side Power Topology Detail

graph LR subgraph "Three-Phase Totem-Pole PFC Stage" AC_IN["3-Phase 400VAC"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> BRIDGE["3-Phase Bridge"] BRIDGE --> PFC_INDUCTOR["PFC Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] subgraph "SiC MOSFET Half-Bridge" Q1["VBP165C70-4L
High-Side"] Q2["VBP165C70-4L
Low-Side"] end PFC_SW_NODE --> Q1 PFC_SW_NODE --> Q2 Q1 --> HV_BUS["800VDC Bus"] Q2 --> PFC_GND["Ground"] PFC_CONTROLLER["PFC Controller"] --> SIC_DRIVER["SiC Gate Driver"] SIC_DRIVER --> Q1 SIC_DRIVER --> Q2 HV_BUS -->|Voltage Feedback| PFC_CONTROLLER end subgraph "LLC Resonant Converter Stage" HV_BUS --> LLC_RESONANT["LLC Resonant Tank"] LLC_RESONANT --> LLC_TRANS["HF Transformer Primary"] subgraph "LLC Half-Bridge" Q3["VBP165C70-4L
High-Side"] Q4["VBP165C70-4L
Low-Side"] end LLC_TRANS --> LLC_SW_NODE["LLC Switch Node"] LLC_SW_NODE --> Q3 LLC_SW_NODE --> Q4 Q3 --> HV_BUS Q4 --> LLC_GND["Ground"] LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["LLC Gate Driver"] LLC_DRIVER --> Q3 LLC_DRIVER --> Q4 LLC_TRANS -->|Current Sense| LLC_CONTROLLER end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q3 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intermediate Bus & Intelligent Switch Topology Detail

graph LR subgraph "Intermediate Bus Generation" ISO_SEC["Transformer Secondary"] --> SR["Synchronous Rectification"] SR --> INT_BUS_CAP["Bus Capacitors"] INT_BUS_CAP --> INT_BUS_12V["12V Intermediate Bus"] INT_BUS_CAP --> INT_BUS_5V["5V Intermediate Bus"] end subgraph "Intelligent Power Switching Channels" subgraph "12V Rail Management" INT_BUS_12V --> SW_12V["VBE2308A
High-Side Switch"] SW_12V --> LOAD_12V["12V Loads"] MGMT_CTRL["Management MCU"] --> DRV_12V["Logic Driver"] DRV_12V --> SW_12V LOAD_12V --> CURRENT_SENSE["Current Monitor"] CURRENT_SENSE --> MGMT_CTRL end subgraph "5V Rail Management" INT_BUS_5V --> SW_5V["VBE2308A
High-Side Switch"] SW_5V --> LOAD_5V["5V Loads"] MGMT_CTRL --> DRV_5V["Logic Driver"] DRV_5V --> SW_5V end subgraph "SSD Shelf Power Control" INT_BUS_12V --> SW_SSD["VBE2308A
SSD Power Switch"] SW_SSD --> SSD_ARRAY["SSD Array"] MGMT_CTRL --> DRV_SSD["Sequencing Driver"] DRV_SSD --> SW_SSD end subgraph "Memory Module Power" INT_BUS_5V --> SW_MEM["VBE2308A
Memory Power Switch"] SW_MEM --> DIMMS["DIMM Modules"] MGMT_CTRL --> DRV_MEM["Sequencing Driver"] DRV_MEM --> SW_MEM end end subgraph "Protection & Sequencing" INRUSH["Inrush Limiter"] --> SW_12V OCP["Over-Current Protection"] --> MGMT_CTRL OVP["Over-Voltage Protection"] --> MGMT_CTRL UVP["Under-Voltage Protection"] --> MGMT_CTRL SEQ_CONTROLLER["Sequencing Controller"] --> MGMT_CTRL SEQ_CONTROLLER --> DRV_12V SEQ_CONTROLLER --> DRV_5V SEQ_CONTROLLER --> DRV_SSD SEQ_CONTROLLER --> DRV_MEM end style SW_12V fill:#fff3e0,stroke:#ff9800,stroke-width:2px style SW_5V fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Point-of-Load Synchronous Buck Converter Topology Detail

graph LR subgraph "Multi-Phase Synchronous Buck Converter" VIN["12V Input"] --> INPUT_CAP["Input Capacitors"] INPUT_CAP --> BUCK_CONTROLLER["Multi-Phase Controller"] subgraph "Phase 1: CPU Core Power" BUCK_CONTROLLER --> DRIVER_PH1["Gate Driver"] DRIVER_PH1 --> Q_HIGH1["VBI3638
High-Side N-MOS"] DRIVER_PH1 --> Q_LOW1["VBI3638
Low-Side N-MOS"] Q_HIGH1 --> SW_NODE1["Switch Node"] Q_LOW1 --> SW_NODE1 SW_NODE1 --> INDUCTOR1["Output Inductor"] INDUCTOR1 --> CPU_VCC["0.9V CPU Core"] end subgraph "Phase 2: I/O Power" BUCK_CONTROLLER --> DRIVER_PH2["Gate Driver"] DRIVER_PH2 --> Q_HIGH2["VBI3638
High-Side N-MOS"] DRIVER_PH2 --> Q_LOW2["VBI3638
Low-Side N-MOS"] Q_HIGH2 --> SW_NODE2["Switch Node"] Q_LOW2 --> SW_NODE2 SW_NODE2 --> INDUCTOR2["Output Inductor"] INDUCTOR2 --> IO_RAIL["1.8V I/O"] end subgraph "Phase 3: Memory Power" BUCK_CONTROLLER --> DRIVER_PH3["Gate Driver"] DRIVER_PH3 --> Q_HIGH3["VBI3638
High-Side N-MOS"] DRIVER_PH3 --> Q_LOW3["VBI3638
Low-Side N-MOS"] Q_HIGH3 --> SW_NODE3["Switch Node"] Q_LOW3 --> SW_NODE3 SW_NODE3 --> INDUCTOR3["Output Inductor"] INDUCTOR3 --> MEM_RAIL["1.2V DDR"] end CPU_VCC --> OUTPUT_CAP["Output Capacitors"] IO_RAIL --> OUTPUT_CAP MEM_RAIL --> OUTPUT_CAP OUTPUT_CAP --> FEEDBACK["Voltage Feedback"] FEEDBACK --> BUCK_CONTROLLER end subgraph "Protection & Monitoring" GATE_CLAMP1["Gate Clamp"] --> Q_HIGH1 GATE_CLAMP2["Gate Clamp"] --> Q_LOW1 CURRENT_MON["Current Monitor"] --> BUCK_CONTROLLER TEMP_MON["Temperature Monitor"] --> BUCK_CONTROLLER OCP_CIRCUIT["Over-Current Protection"] --> BUCK_CONTROLLER end subgraph "PCB Layout Considerations" THERMAL_PAD["Thermal Pad"] --> PCB_VIAS["Thermal Vias"] POWER_LOOP["Minimized Power Loop"] --> Q_HIGH1 GATE_LOOP["Minimized Gate Loop"] --> DRIVER_PH1 SYMM_LAYOUT["Symmetrical Layout"] --> Q_HIGH2 end style Q_HIGH1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOW1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
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