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Preface: Forging the "Power Spine" of Computational Giants – Systems Thinking in Power Device Selection for High-Density AI Training Servers
AI Training Server Power Module System Topology Diagram

AI Training Server Power System Overall Topology Diagram

graph LR %% AC Input & Front-End Power Supply Section subgraph "AC-DC Power Supply Unit (PSU)" AC_IN["Three-Phase/Universal AC Input"] --> EMI_FILTER["EMI Input Filter"] EMI_FILTER --> PFC_BRIDGE["Three-Phase/Universal Rectifier"] PFC_BRIDGE --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] subgraph "Primary Side High-Voltage MOSFETs (PFC/LLC)" Q_PFC1["VBP165R47S
650V/47A
SJ Multi-EPI"] Q_PFC2["VBP165R47S
650V/47A
SJ Multi-EPI"] Q_LLC1["VBP165R47S
650V/47A
SJ Multi-EPI"] Q_LLC2["VBP165R47S
650V/47A
SJ Multi-EPI"] end PFC_SW_NODE --> Q_PFC1 PFC_SW_NODE --> Q_PFC2 Q_PFC1 --> HV_BUS["High-Voltage DC Bus"] Q_PFC2 --> HV_BUS HV_BUS --> LLC_RES_TANK["LLC Resonant Tank"] LLC_RES_TANK --> LLC_TRANS["LLC Transformer
Primary"] LLC_TRANS --> LLC_SW_NODE["LLC Switching Node"] LLC_SW_NODE --> Q_LLC1 LLC_SW_NODE --> Q_LLC2 Q_LLC1 --> GND_PRI Q_LLC2 --> GND_PRI LLC_TRANS_SEC["LLC Transformer
Secondary"] --> SR_BRIDGE["Synchronous Rectification"] SR_BRIDGE --> OUTPUT_FILTER["Output Filter"] OUTPUT_FILTER --> PS_OUT_12V["PSU Output
12VDC"] end %% GPU VRM (Multi-Phase Buck) Section subgraph "GPU Voltage Regulator Module (Multi-Phase Buck)" PS_OUT_12V --> VRM_IN["VRM Input 12V"] subgraph "Multi-Phase Buck High-Side MOSFETs" Q_HS1["High-Side MOSFET"] Q_HS2["High-Side MOSFET"] end subgraph "Multi-Phase Buck Low-Side MOSFETs (VBN1101N)" Q_LS1["VBN1101N
100V/100A"] Q_LS2["VBN1101N
100V/100A"] Q_LS3["VBN1101N
100V/100A"] Q_LS4["VBN1101N
100V/100A"] end VRM_IN --> Q_HS1 VRM_IN --> Q_HS2 Q_HS1 --> PHASE_NODE1["Phase Node 1"] Q_HS2 --> PHASE_NODE2["Phase Node 2"] PHASE_NODE1 --> Q_LS1 PHASE_NODE1 --> INDUCTOR1["Output Inductor"] PHASE_NODE2 --> Q_LS2 PHASE_NODE2 --> INDUCTOR2["Output Inductor"] INDUCTOR1 --> GPU_VCC["GPU Core Voltage
~1V"] INDUCTOR2 --> GPU_VCC Q_LS1 --> GND_VRM Q_LS2 --> GND_VRM Q_LS3 --> GND_VRM Q_LS4 --> GND_VRM VRM_CONTROLLER["Multi-Phase PWM Controller"] --> GATE_DRIVER["Gate Driver Array"] GATE_DRIVER --> Q_HS1 GATE_DRIVER --> Q_HS2 GATE_DRIVER --> Q_LS1 GATE_DRIVER --> Q_LS2 GPU_VCC --> GPU_LOAD["AI GPU
Compute Load"] end %% Auxiliary Power Distribution & Intelligent Management Section subgraph "Auxiliary Power Distribution & Management" AUX_12V["12V Auxiliary Rail"] --> INTELLIGENT_SWITCH["Intelligent Load Switch Array"] subgraph "High-Current Auxiliary Load Switches (VBA1405)" SW_PUMP["VBA1405
40V/18A"] SW_FANS1["VBA1405
40V/18A"] SW_FANS2["VBA1405
40V/18A"] SW_STORAGE["VBA1405
40V/18A"] end INTELLIGENT_SWITCH --> SW_PUMP INTELLIGENT_SWITCH --> SW_FANS1 INTELLIGENT_SWITCH --> SW_FANS2 INTELLIGENT_SWITCH --> SW_STORAGE SW_PUMP --> PUMP_UNIT["Liquid Cooling Pump"] SW_FANS1 --> FAN_BANK1["Fan Bank 1"] SW_FANS2 --> FAN_BANK2["Fan Bank 2"] SW_STORAGE --> STORAGE_BACKUP["Backup Storage Array"] BMC["Baseboard Management Controller (BMC)"] --> PMBUS_INTERFACE["PMBus/I2C Interface"] PMBUS_INTERFACE --> SW_PUMP PMBUS_INTERFACE --> SW_FANS1 PMBUS_INTERFACE --> SW_FANS2 PMBUS_INTERFACE --> SW_STORAGE end %% Thermal Management System subgraph "Three-Level Thermal Management Architecture" COOLING_LEVEL1["Level 1: Direct Cooling
GPU VRM MOSFETs"] --> Q_LS1 COOLING_LEVEL1 --> Q_LS2 COOLING_LEVEL1 --> Q_LS3 COOLING_LEVEL1 --> Q_LS4 COOLING_LEVEL2["Level 2: Forced Air Cooling
PSU Primary MOSFETs"] --> Q_PFC1 COOLING_LEVEL2 --> Q_LLC1 COOLING_LEVEL3["Level 3: PCB Conduction & Airflow
Control ICs & Auxiliary Switches"] --> VRM_CONTROLLER COOLING_LEVEL3 --> SW_PUMP THERMAL_SENSORS["NTC Temperature Sensors"] --> BMC BMC --> FAN_PWM["Fan PWM Control"] BMC --> PUMP_CTRL["Pump Speed Control"] FAN_PWM --> FAN_BANK1 PUMP_CTRL --> PUMP_UNIT end %% Protection & Monitoring subgraph "System Protection & Monitoring" PROTECTION_CIRCUITS["Snubber Networks & TVS Arrays"] --> Q_PFC1 PROTECTION_CIRCUITS --> Q_LLC1 CURRENT_SENSE["High-Precision Current Sensing"] --> BMC VOLTAGE_MON["Voltage Monitoring"] --> BMC FAULT_LATCH["Fault Detection & Latch"] --> SHUTDOWN_LOGIC["System Shutdown Logic"] SHUTDOWN_LOGIC --> Q_PFC1 SHUTDOWN_LOGIC --> Q_LLC1 SHUTDOWN_LOGIC --> Q_LS1 SHUTDOWN_LOGIC --> SW_PUMP end %% Communication & Control BMC --> SYSTEM_MGMT["System Management Interface"] BMC --> CLOUD_MON["Cloud Monitoring"] VRM_CONTROLLER --> DIGITAL_INTERFACE["Digital Interface (PMBus/I2C)"] DIGITAL_INTERFACE --> BMC %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SW_PUMP fill:#fff3e0,stroke:#ff9800,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the era of large-scale AI model training, the performance of an 8-GPU server cluster is fundamentally bounded by its power delivery and management infrastructure. This system is not merely a collection of voltage regulators and switches; it is a meticulously engineered "power spine" that must simultaneously deliver kilowatts of clean, stable energy to voracious GPUs while ensuring faultless operation for auxiliary loads. Its core mandates—ultra-high conversion efficiency, exceptional power density, and unwavering reliability under dynamic loads—are all anchored in the strategic selection and application of power semiconductor devices at key nodal points.
This article adopts a holistic, system-centric design philosophy to address the core challenges within the power chain of an 8-GPU AI server: how to select the optimal power MOSFETs for the critical roles of high-voltage AC/DC front-end conversion, low-voltage high-current GPU VRM (Voltage Regulator Module) output, and intelligent auxiliary power distribution, under the stringent constraints of thermal density, transient response, and signal integrity.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Efficiency Front-End Sentinel: VBP165R47S (650V, 47A, TO-247) – PFC/LLC Primary-Side or Isolated DC-DC High-Voltage Switch
Core Positioning & Topology Synergy: This Super Junction Multi-EPI MOSFET is engineered for the high-voltage switching node in the server's power supply unit (PSU), such as the primary side of an LLC resonant converter or the switch in a Boost PFC stage. Its 650V rating provides robust margin for universal AC input (85-264VAC) and associated voltage spikes. The low Rds(on) of 50mΩ directly minimizes conduction loss, a critical factor for 80Plus Titanium or Platinum efficiency standards.
Key Technical Parameter Analysis:
Super Junction Advantage: The SJ_Multi-EPI technology delivers an optimal figure-of-merit (FOM) by drastically reducing switching losses (Eoss, Qgd) while maintaining low on-resistance. This is paramount for high-frequency (e.g., 100-300kHz) soft-switching topologies like LLC, enabling higher power density through smaller magnetics.
Current Handling & Package: The 47A continuous rating and robust TO-247 package make it suitable for multi-kilowatt PSUs powering an 8-GPU system. Its high current capability ensures de-rating headroom, enhancing long-term reliability.
Selection Rationale: Compared to standard planar MOSFETs, it offers significantly lower total loss. Compared to GaN HEMTs, it presents a more cost-effective and mature solution with easier gate drive requirements for this power level, representing the sweet spot for high-performance, volume server PSUs.
2. The GPU Power Workhorse: VBN1101N (100V, 100A, TO-262) – Multi-Phase Synchronous Buck Converter Low-Side / Synchronous Rectifier
Core Positioning & System Impact: Positioned as the core switch in the multi-phase VRM supplying the GPU (typically converting 12V to ~1V or lower). Its exceptionally low Rds(on) of 9mΩ @10V is the single most critical parameter for minimizing conduction loss in the high-current path, where currents can exceed 500A per GPU socket.
System-Level Benefits:
Peak Efficiency & Thermal Management: The ultra-low Rds(on) directly translates to higher full-load efficiency, reducing the thermal burden on the server's cooling system. Lower junction temperature rise improves MOSFET reliability and allows for more aggressive power delivery settings.
Transient Response Support: The low parasitic capacitance (relative to its current rating) and fast body diode enable clean, fast switching essential for the VRM to respond to the GPU's microsecond-scale load steps (di/dt), preventing voltage droop and ensuring computational stability.
Drive Considerations: While its gate charge (Qg) needs careful evaluation, modern multi-phase PWM controllers and integrated drivers are designed to drive such high-current MOSFETs effectively. Attention to gate loop inductance is critical to realize its fast switching potential.
3. The Intelligent Peripheral Arbiter: VBA1405 (40V, 18A, SOP8) – High-Current Auxiliary Rail & Fan Management Switch
Core Positioning & Integration Value: This single N-channel MOSFET in a compact SOP8 package is the ideal solution for intelligent, high-side switching of auxiliary 12V/5V rails powering high-current peripherals such as pump units for liquid cooling, bank of fans, or backup storage arrays. Its remarkably low Rds(on) of 4mΩ @10V ensures negligible voltage drop even at full 18A load.
Application Scenarios: Enables precise power sequencing, load shedding based on thermal telemetry, and fault isolation for non-essential loads during peak GPU compute cycles. It can be used for hot-swap control or as a solid-state circuit breaker.
Design Elegance: The use of an N-channel MOSFET for high-side switching, driven by a compact charge pump or bootstrap circuit, is preferred over P-channel for its superior Rds(on)Area ratio. The SOP8 package maximizes board space utilization in dense server motherboards or power distribution boards (PDBs), facilitating localized power control.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Synchronization
Front-End & Digital PSU Controller: The switching of VBP165R47S must be tightly synchronized with the PSU's digital controller (e.g., for LLC frequency modulation or PFC current shaping). Its gate drive should be optimized for soft-switching transitions to maximize the SJ-MOSFET's benefits.
Multi-Phase VRM Precision Control: The VBN1101Ns, deployed in parallel across multiple phases, require perfectly matched gate drive timing and current sharing to minimize output ripple and thermal imbalance. Use of dedicated phase doublers/triplers and current-sense amplifiers is essential.
PMBus-Based Intelligent Switching: The VBA1405 gates should be controlled by a Baseboard Management Controller (BMC) or a dedicated power management IC via PMBus/I2C, enabling programmable slew rate (soft-start), current limit, and real-time status monitoring for each auxiliary channel.
2. Hierarchical Thermal Management Strategy
Tier-1 Hotspot (Forced Air/Liquid Cooling): The VBN1101Ns in the GPU VRM are the primary heat sources, often mounted on a dedicated heatsink with direct airflow from system fans or connected to a cold plate in liquid-cooled designs.
Tier-2 Heat Source (Forced Air Cooling): The VBP165R47S within the PSU benefits from the PSU's internal fan and dedicated heatsinking. Its thermal performance directly impacts PSU form factor and fan acoustics.
Tier-3 Heat Source (PCB Conduction & Airflow): The VBA1405, while efficient, may still dissipate significant heat when switching high currents. Liberal use of thermal vias under its SOP8 package to inner ground planes and exposure to general chassis airflow are crucial.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Mitigation:
VBP165R47S: In LLC or PFC circuits, snubber networks or clamping circuits are vital to suppress voltage overshoot caused by transformer leakage inductance or circuit parasitics.
Inductive Load Control: For fan or pump motors switched by VBA1405, external freewheeling diodes or TVS arrays are necessary to handle back-EMF during turn-off.
Gate Integrity: All gate drives must be designed with low-inductance loops. Series gate resistors should be optimized for switching speed vs. EMI. Gate-source Zener diodes (e.g., ±15V) are mandatory for protection against transients.
De-rating Discipline:
Voltage De-rating: For VBP165R47S, operational VDS should not exceed 80% of 650V (520V) under worst-case line transients. For VBN1101N, VDS must have ample margin above the input bus voltage (12V).
Current & Thermal De-rating: Continuous and pulse current ratings must be derated based on the actual measured or simulated junction temperature, targeting Tj(max) < 125°C during sustained full-load operation. The high ambient temperature inside a server chassis must be accounted for.
III. Quantifiable Perspective on Scheme Advantages and Competitor Comparison
Quantifiable Efficiency Gains: In a 12V to 1V, 600A GPU VRM, using VBN1101N (9mΩ) versus a typical 15mΩ alternative can reduce total conduction loss by approximately 40%, directly lowering VRM temperatures by 15-20°C and improving server power usage effectiveness (PUE).
Quantifiable Power Density & Reliability Improvement: Using VBA1405 in SOP8 for auxiliary switching saves over 60% board area compared to a TO-220 discrete solution per channel, enabling more features on the PDB. The reduced component count and solder joints improve mean time between failures (MTBF).
Total Cost of Ownership (TCO) Optimization: The selected devices, through superior efficiency and robustness, reduce energy consumption, cooling requirements, and potential downtime due to power-related failures, offering a compelling TCO advantage over generic solutions.
IV. Summary and Forward Look
This scheme constructs a robust, high-performance power chain for 8-GPU AI training servers, addressing efficiency from the AC inlet to the GPU core and intelligent auxiliary control. The philosophy is "right-device, right-place, system-optimized":
Power Conversion Tier – Focus on "High-Frequency Efficiency": Leverage Super Junction technology at the front-end for the best balance of switching and conduction loss at elevated frequencies.
Power Delivery Tier – Focus on "Ultra-Low Loss Conduction": Invest in the lowest possible Rds(on) for the high-current GPU power path, as conduction loss dominates here.
Power Management Tier – Focus on "Intelligent Density": Utilize highly integrated, low-Rds(on) switches in minimal packages to achieve granular, software-defined power control without sacrificing performance.
Future Evolution Directions:
Adoption of Gallium Nitride (GaN): For the next frontier in PSU density and efficiency, GaN HEMTs could replace SJ-MOSFETs in the front-end, pushing switching frequencies into the MHz range and further shrinking magnetics.
Fully Integrated Power Stages: For GPU VRMs, the move towards fully integrated power stages (FIPS) that combine the driver, MOSFETs, and sensing into a single module simplifies design and optimizes parasitics for the ultimate transient response.
Silicon Carbide (SiC) for High-Voltage Bus: In systems exploring 48V or higher intermediate bus architectures, SiC MOSFETs could become the preferred choice for subsequent conversion stages due to their superior high-temperature performance.
Engineers can tailor this framework based on specific server specifications: PSU wattage (e.g., 3kW+), GPU power budget (e.g., 400W+ per GPU), cooling strategy (air vs. liquid), and redundancy requirements to architect a server power system that fully unleashes AI computational potential.

Detailed Topology Diagrams

Front-End PFC/LLC Power Topology Detail

graph LR subgraph "Three-Phase/Universal PFC Stage" AC_IN["AC Input"] --> EMI["EMI Filter"] EMI --> RECTIFIER["Rectifier Bridge"] RECTIFIER --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switch Node"] PFC_SW_NODE --> Q_PFC["VBP165R47S
650V/47A"] Q_PFC --> HV_BUS["HV DC Bus"] PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> Q_PFC end subgraph "LLC Resonant Conversion Stage" HV_BUS --> LLC_RESONANT["LLC Resonant Tank
Lr, Cr, Lm"] LLC_RESONANT --> LLC_TRANS["High-Freq Transformer"] LLC_TRANS --> LLC_SW_NODE["LLC Switch Node"] LLC_SW_NODE --> Q_LLC["VBP165R47S
650V/47A"] Q_LLC --> GND LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["Gate Driver"] LLC_DRIVER --> Q_LLC LLC_TRANS_SEC["Transformer Secondary"] --> SR_BRIDGE["Synchronous Rectifier"] SR_BRIDGE --> OUTPUT_FILTER["LC Output Filter"] OUTPUT_FILTER --> OUTPUT_12V["12VDC Output"] end subgraph "Protection Circuits" SNUBBER["RCD Snubber Network"] --> Q_PFC CLAMP["Voltage Clamp Circuit"] --> Q_LLC TVS["TVS Array"] --> PFC_DRIVER TVS --> LLC_DRIVER end style Q_PFC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LLC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

GPU Multi-Phase VRM & Auxiliary Management Topology

graph LR subgraph "Multi-Phase Buck Converter for GPU Core" VRM_IN["12V Input"] --> HIGH_SIDE["High-Side MOSFET"] HIGH_SIDE --> PHASE_NODE["Phase Node"] PHASE_NODE --> LOW_SIDE["VBN1101N
100V/100A"] LOW_SIDE --> GND PHASE_NODE --> OUTPUT_INDUCTOR["Output Inductor"] OUTPUT_INDUCTOR --> OUTPUT_CAP["Output Capacitors"] OUTPUT_CAP --> GPU_VCC["GPU Core Voltage"] MULTI_PHASE_CTRL["Multi-Phase PWM Controller"] --> GATE_DRIVERS["Gate Driver Array"] GATE_DRIVERS --> HIGH_SIDE GATE_DRIVERS --> LOW_SIDE CURRENT_SENSE["Current Sense Amplifiers"] --> MULTI_PHASE_CTRL VOLTAGE_SENSE["Voltage Feedback"] --> MULTI_PHASE_CTRL end subgraph "Intelligent Auxiliary Load Switches" BMC["BMC/PMIC"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> GATE_CTRL["Gate Control"] subgraph "VBA1405 Load Switch Channel" VCC_12V["12V Auxiliary"] --> DRAIN["Drain"] GATE_CTRL --> GATE["Gate"] SOURCE["Source"] --> LOAD["Auxiliary Load"] LOAD --> GND2["Ground"] end FREE_WHEELING["Freewheeling Diode"] --> LOAD TVS_PROTECTION["TVS Protection"] --> DRAIN end subgraph "Current Sharing & Monitoring" PHASE_CURRENT1["Phase 1 Current"] --> SHARING_CTRL["Current Sharing Controller"] PHASE_CURRENT2["Phase 2 Current"] --> SHARING_CTRL SHARING_CTRL --> BALANCE_ADJ["Balance Adjustment"] BALANCE_ADJ --> GATE_DRIVERS TELEMETRY["Power Telemetry"] --> BMC end style LOW_SIDE fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style VCC_12V fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Thermal Management & System Protection Topology

graph LR subgraph "Three-Level Cooling Architecture" LEVEL1["Level 1: Direct Cooling"] --> TARGET1["GPU VRM MOSFETs
VBN1101N"] LEVEL2["Level 2: Forced Air Cooling"] --> TARGET2["PSU Primary MOSFETs
VBP165R47S"] LEVEL3["Level 3: PCB & Airflow"] --> TARGET3["Control ICs & VBA1405"] TEMP_SENSORS["Temperature Sensors
(NTC, Digital)"] --> BMC_TEMP["BMC Thermal Management"] BMC_TEMP --> FAN_PWM_CTRL["Fan PWM Controller"] BMC_TEMP --> PUMP_SPEED_CTRL["Pump Speed Controller"] FAN_PWM_CTRL --> FAN_ARRAY["Fan Array"] PUMP_SPEED_CTRL --> LIQUID_PUMP["Liquid Cooling Pump"] end subgraph "Electrical Protection Network" OVERVOLTAGE["Overvoltage Protection"] --> CLAMP_CIRCUIT["Clamping Circuit"] OVERCURRENT["Overcurrent Protection"] --> CURRENT_LIMIT["Current Limit Circuit"] OVERTEMP["Overtemperature Protection"] --> SHUTDOWN_LOGIC["Shutdown Logic"] SNUBBER_NET["Snubber Network"] --> POWER_MOSFETS["Power MOSFETs"] TVS_ARRAY["TVS Array"] --> GATE_DRIVERS["Gate Driver ICs"] SHUTDOWN_LOGIC --> SYSTEM_DISABLE["System Disable"] SYSTEM_DISABLE --> POWER_MOSFETS end subgraph "Monitoring & Fault Management" VOLTAGE_MON["Voltage Monitors"] --> ADC["ADC Multiplexer"] CURRENT_MON["Current Monitors"] --> ADC TEMP_MON["Temperature Monitors"] --> ADC ADC --> FAULT_DETECT["Fault Detection Logic"] FAULT_DETECT --> FAULT_LOG["Fault Logging"] FAULT_DETECT --> SYSTEM_RESPONSE["System Response"] SYSTEM_RESPONSE --> ALERT["Alert Generation"] SYSTEM_RESPONSE --> THROTTLING["Power Throttling"] end subgraph "De-rating & Reliability" VOLTAGE_DERATE["Voltage De-rating
(<80% Rating)"] --> MOSFETS["All MOSFETs"] THERMAL_DERATE["Thermal De-rating
(Tj < 125°C)"] --> MOSFETS CURRENT_DERATE["Current De-rating
(Based on Tj)"] --> MOSFETS end style TARGET1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style TARGET2 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style TARGET3 fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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