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MOSFET/IGBT Selection Strategy and Device Adaptation Handbook for Hybrid Storage Array (SSD+HDD) Power Systems with High-Efficiency and Reliability Requirements
Hybrid Storage Array Power System MOSFET/IGBT Selection Topology Diagram

Hybrid Storage Array (SSD+HDD) Power System Overall Topology

graph LR %% AC-DC Input & Power Distribution Section subgraph "AC-DC Input & Primary Power Distribution" AC_IN["AC Input 85-265VAC"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> PFC_STAGE["PFC Boost Stage"] subgraph "PFC Stage MOSFET" PFC_MOSFET["VBPB165R15S
650V/15A (TO3P)"] end PFC_STAGE --> PFC_MOSFET PFC_MOSFET --> HV_BUS["High-Voltage DC Bus
~400VDC"] HV_BUS --> DC_DC_CONVERTER["DC-DC Converter"] end %% HDD Motor Drive Section subgraph "HDD Spindle & VCM Motor Drive" subgraph "Spindle Motor Driver" SPINDLE_DRIVER["HDD Spindle Driver IC"] SPINDLE_MOSFET["VBP1104N
100V/85A (TO-247)"] end subgraph "Voice Coil Motor (VCM) Driver" VCM_DRIVER["VCM Driver IC"] VCM_MOSFET["VBP1104N
100V/85A (TO-247)"] end DC_DC_CONVERTER --> SPINDLE_DRIVER DC_DC_CONVERTER --> VCM_DRIVER SPINDLE_DRIVER --> SPINDLE_MOSFET VCM_DRIVER --> VCM_MOSFET SPINDLE_MOSFET --> HDD_SPINDLE["HDD Spindle Motor
(12V, 10-30W)"] VCM_MOSFET --> HDD_VCM["HDD Voice Coil Motor"] end %% SSD Power Management Section subgraph "SSD & System Power Rail Switching" subgraph "SSD Power Path" SSD_POWER_SWITCH["SSD Power Switch"] SSD_MOSFET["VBMB1302
30V/180A (TO-220F)"] end subgraph "System Power Rails" POL_CONVERTER["Point-of-Load Converter"] RAIL_SWITCH["3.3V/5V Rail Switch"] end DC_DC_CONVERTER --> SSD_POWER_SWITCH DC_DC_CONVERTER --> POL_CONVERTER SSD_POWER_SWITCH --> SSD_MOSFET SSD_MOSFET --> SSD_ARRAY["SSD Controller & NAND Array"] POL_CONVERTER --> RAIL_SWITCH RAIL_SWITCH --> SYSTEM_RAILS["System Power Rails
3.3V/5V/12V"] end %% Cooling & Protection Section subgraph "Cooling System & Protection" subgraph "Cooling Fan Control" FAN_CONTROLLER["Fan Speed Controller"] FAN_MOSFET["VBG3638
Fan Drive MOSFET"] end subgraph "Protection Circuits" OVERVOLTAGE_PROT["Overvoltage Protection"] OVERCURRENT_PROT["Overcurrent Protection"] TEMPERATURE_SENSOR["Temperature Sensors"] end SYSTEM_RAILS --> FAN_CONTROLLER FAN_CONTROLLER --> FAN_MOSFET FAN_MOSFET --> COOLING_FAN["Cooling Fans"] TEMPERATURE_SENSOR --> SYSTEM_CONTROL["System Controller"] OVERVOLTAGE_PROT --> SYSTEM_CONTROL OVERCURRENT_PROT --> SYSTEM_CONTROL end %% System Control & Communication subgraph "System Control & Communication" SYSTEM_CONTROL["System Controller MCU"] --> COMM_INTERFACE["Communication Interface"] SYSTEM_CONTROL --> MONITORING["System Monitoring"] MONITORING --> STATUS_DISPLAY["Status Display"] COMM_INTERFACE --> EXTERNAL_SYSTEM["External Management System"] end %% Thermal Management subgraph "Thermal Management Architecture" subgraph "Level 1: Primary Cooling" PRIMARY_HEATSINK["Primary Heatsink"] --> PFC_MOSFET PRIMARY_HEATSINK --> SPINDLE_MOSFET end subgraph "Level 2: Secondary Cooling" SECONDARY_COOLING["PCB Copper Planes"] --> SSD_MOSFET SECONDARY_COOLING --> RAIL_SWITCH end subgraph "Level 3: System Airflow" SYSTEM_AIRFLOW["System Airflow Management"] --> STORAGE_DEVICES["HDD/SSD Arrays"] SYSTEM_AIRFLOW --> PRIMARY_HEATSINK end end %% Style Definitions style PFC_MOSFET fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SPINDLE_MOSFET fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SSD_MOSFET fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style FAN_MOSFET fill:#fff3e0,stroke:#ff9800,stroke-width:2px style SYSTEM_CONTROL fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the exponential growth of data-centric applications and the evolution of storage architectures, hybrid storage arrays (combining SSDs and HDDs) have become critical for balancing performance, capacity, and cost. The power delivery and motor drive systems, serving as the "lifeblood" of the array, provide stable and efficient power conversion for diverse loads such as SSD controller/ NAND clusters, HDD spindle/voice coil motors (VCM), and system cooling fans. The selection of power MOSFETs and IGBTs directly dictates power rail efficiency, thermal management, power density, and overall system reliability. Addressing the stringent requirements of data centers for 24/7 operation, high efficiency, low noise, and high reliability, this article develops a practical and optimized device selection strategy based on scenario-specific adaptation.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Multi-Dimensional Co-optimization
Device selection requires a holistic approach across key dimensions—voltage rating, conduction & switching losses, package thermal performance, and ruggedness—ensuring precise alignment with operational profiles:
Adequate Voltage & Current Margin: For 12V/5V/3.3V power rails and HDD motor voltages, maintain a voltage derating ≥50% to handle inductive spikes and bulk capacitor switching transients. Current ratings must sustain peak loads (e.g., SSD burst writes, HDD startup).
Loss Minimization Priority: Prioritize low Rds(on) (minimizing conduction loss in power paths) and optimized gate/drain charge (reducing switching loss in PWM converters). For HDD spindle drives, low VCEsat is critical for IGBTs.
Package & Thermal Matching: Select high-current packages (TO-247, TO-263, TO3P) with low thermal resistance for primary power stages and motor drives. Use compact packages (DFN, TO-220F) for secondary switches and point-of-load (POL) applications, balancing power density and thermal dissipation.
Reliability & Ruggedness: Meet datasheet 24/7 operational life expectations. Focus on wide junction temperature range (Tj), robust gate oxide integrity, and intrinsic diode/body diode characteristics for hard-switching applications.
(B) Scenario Adaptation Logic: Categorization by Load Type
Divide loads into three primary scenarios: First, HDD Motor Drive (Spindle & VCM) – requiring robust medium-voltage switching with high current capability. Second, SSD & System Power Rail Switching – demanding high-current, low-voltage switching with ultra-low Rds(on) for maximum efficiency. Third, System-Level Power Conversion & Protection – involving AC-DC front-end, DC-DC conversion, and hot-swap circuits requiring high-voltage devices.
II. Detailed Device Selection Scheme by Scenario
(A) Scenario 1: HDD Spindle Motor Drive (12V Rail, ~10-30W per HDD) – Robust Medium-Power Switch
HDD spindle motors are inductive loads requiring reliable 12V switching, handling start-up current surges (3-5x nominal) and continuous operation.
Recommended Model: VBP1104N (N-MOS, 100V, 85A, TO-247)
Parameter Advantages: 100V rating provides ample margin on 12V rail (>700%). Low Rds(on) of 35mΩ @10V minimizes conduction loss. High current rating (85A) easily handles multiple HDDs in parallel or high-startup currents. Trench technology offers a good balance of Rds(on) and gate charge.
Adaptation Value: Enables efficient, compact motor driver design for multi-bay backplanes. Low conduction loss reduces heatsink requirements. The TO-247 package facilitates excellent thermal coupling to chassis or heatsink for heat dissipation.
Selection Notes: Verify total concurrent start-up current for multiple HDDs. Implement proper gate drive (≥2A sink/source) for fast switching. Include TVS diodes and snubbers to clamp voltage spikes from motor inductance.
(B) Scenario 2: SSD & Low-Voltage Power Rail Switching (3.3V/5V, High Current) – High-Efficiency Power Path
SSD controllers and NAND arrays demand high-current, low-voltage power with stringent ripple requirements. POL converters and load switches require minimal voltage drop.
Recommended Model: VBMB1302 (N-MOS, 30V, 180A, TO-220F)
Parameter Advantages: Extremely low Rds(on) of 2mΩ @10V (3mΩ @4.5V). Very high continuous current rating (180A). 30V rating is ideal for 5V/12V intermediate bus applications with good margin. TO-220F package offers isolated tab for easier thermal management.
Adaptation Value: Ideal as a synchronous rectifier in high-current DC-DC converters (e.g., 12V to 5V/3.3V) or as a high-side load switch for SSD power planes. Ultra-low Rds(on) maximizes efficiency (>97% for power stages) and minimizes thermal stress.
Selection Notes: Ensure gate drive voltage meets Vgs spec (10V recommended for lowest Rds(on)). PCB layout is critical—use wide copper pours and multiple vias to minimize parasitic resistance and inductance. Consider parallel devices for currents beyond 150A.
(C) Scenario 3: AC-DC Front-End / PFC Stage & System Protection (High Voltage)
The AC input stage (PFC) and protection circuits require high-voltage devices capable of handling 400V DC bus voltages and surge events.
Recommended Model: VBPB165R15S (N-MOS, 650V, 15A, TO3P)
Parameter Advantages: 650V rating suitable for universal AC input (85-265VAC) PFC and flyback converters. Super Junction (SJ) Multi-EPI technology offers excellent Rds(on) (300mΩ) vs. voltage rating trade-off, reducing conduction losses. TO3P package provides superior thermal performance for high-power dissipation stages.
Adaptation Value: Enables high-efficiency (>95%) PFC circuit design, meeting 80 PLUS Titanium requirements for server PSUs. Can also be used in high-voltage OR-ing circuits for redundant power supplies. Robust package handles higher dissipation in continuous conduction mode (CCM) PFC.
Selection Notes: Must be paired with optimized gate drive to manage switching losses due to high voltage. Pay careful attention to drain-source voltage slew rates (dV/dt) and parasitic oscillations. Use snubbers or RC networks if needed.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBP1104N (HDD Drive): Pair with dedicated motor driver ICs or half-bridge drivers (e.g., IRS21844) with sufficient current capability. Use gate resistors to control slew rate and minimize EMI from motor cables.
VBMB1302 (SSD Power): Use high-speed, low-impedance gate drivers (e.g., LM5113) located close to the MOSFET. A small gate-source capacitor (1-2.2nF) may enhance stability in parallel configurations.
VBPB165R15S (PFC Stage): Use isolated or high-side gate drivers (e.g., Si823x) with negative voltage bias capability for robust noise immunity in high-voltage environments. Implement active clamp or snubber circuits.
(B) Thermal Management Design: Tiered Approach
VBPB165R15S (TO3P): Primary heat source. Mount on a main heatsink, using thermal interface material. Ensure adequate airflow from system fans.
VBP1104N (TO-247): Can be mounted on a secondary heatsink or, for lower power counts, rely on PCB copper plane (≥500mm², 2oz) with thermal vias.
VBMB1302 (TO-220F): Leverage its isolated package to mount directly on a chassis member or dedicated heatsink for high-current paths. For lower currents, a substantial copper plane is sufficient.
System-Level: Design airflow to pass over the primary heatsinks (PFC, motor drives) first, then over the storage devices (HDDs/SSDs).
(C) EMC and Reliability Assurance
EMC Suppression:
VBMB1302/VBP1104N: Use low-ESR ceramic capacitors (X7R) very close to drain-source terminals. Implement ferrite beads on gate drive and power output lines.
VBPB165R15S: Utilize an EMI filter at AC input. Incorporate an RC snubber across the drain-source. Ensure tight layout of the high-current switching loop.
Reliability Protection:
Derating: Operate devices at ≤80% of rated voltage and ≤70% of rated current at maximum expected ambient temperature.
Overcurrent Protection: Implement current sensing (shunt resistor or hall-effect) on critical power rails with fast-response comparators or dedicated ICs.
Surge/ESD Protection: Place TVS diodes (e.g., SMCJ) at AC input, 12V input, and on motor driver outputs. Use ESD protection diodes on gate pins sensitive to handling.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Optimized Performance per Watt: High-efficiency device selection minimizes power losses across the storage array, reducing total cost of ownership (TCO) and data center PUE.
High-Density & Reliable Design: The selected packages allow for compact power subsystem design while ensuring reliable 24/7 operation under data center workloads.
Scalable Architecture: The chosen devices support scaling from small business arrays to large enterprise JBOD/EBOD enclosures by paralleling or adjusting driver design.
(B) Optimization Suggestions
Higher Power HDD Arrays: For arrays with a very high count of HDDs, consider using VBM2403 (P-MOS, -40V, -130A) in high-side switch configurations for simpler gate drive.
High-Voltage Intermediate Bus (e.g., 48V): For emerging 48V rack architectures, select VBL17R10S (700V, 10A) or VBM165R22 (650V, 22A) for subsequent DC-DC conversion stages.
Space-Constrained SSD Power: For ultra-dense all-flash arrays, consider VBGQA2303 (P-MOS, -30V, -160A, DFN8) for its extremely low Rds(on) and compact footprint in load switch applications.
Legacy or High-Power Motor Control: For arrays using higher voltage or higher torque motors, the VBPB112MI50 (1200V IGBT+FRD) offers a robust, cost-effective solution.

Detailed Device Selection Topology Diagrams

HDD Motor Drive (Spindle & VCM) Topology Detail

graph LR subgraph "HDD Spindle Motor Drive Circuit" A["12V Power Rail"] --> B["Motor Driver IC
(e.g., IRS21844)"] B --> C["Gate Driver"] C --> D["VBP1104N
100V/85A (TO-247)"] D --> E["HDD Spindle Motor
12V, 10-30W"] F["Current Sense
Resistor"] --> B G["TVS Diode Array"] --> E H["Snubber Circuit"] --> D end subgraph "Voice Coil Motor (VCM) Drive Circuit" I["12V Power Rail"] --> J["VCM Driver IC"] J --> K["Gate Driver"] K --> L["VBP1104N
100V/85A (TO-247)"] L --> M["Voice Coil Motor"] N["Position Feedback"] --> J O["Current Limit"] --> J end subgraph "Multi-HDD Backplane" P["Backplane Power
Distribution"] --> Q["HDD Bay 1"] P --> R["HDD Bay 2"] P --> S["HDD Bay 3"] P --> T["HDD Bay N"] Q --> U["VBP1104N per HDD"] R --> V["VBP1104N per HDD"] S --> W["VBP1104N per HDD"] T --> X["VBP1104N per HDD"] end style D fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style L fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

SSD & Low-Voltage Power Rail Switching Topology Detail

graph LR subgraph "SSD Power Path & Load Switch" A["12V Intermediate Bus"] --> B["Synchronous Buck Converter"] subgraph "Synchronous Rectification" C["VBMB1302
30V/180A (High-side)"] D["VBMB1302
30V/180A (Low-side)"] end B --> C B --> D C --> E["5V/3.3V Output"] D --> F["Ground"] E --> G["SSD Power Plane"] subgraph "SSD Load Switch Configuration" H["MCU GPIO Control"] --> I["Level Shifter"] I --> J["Gate Driver
(e.g., LM5113)"] J --> K["VBMB1302
Load Switch"] K --> L["SSD Controller Power"] K --> M["NAND Array Power"] end subgraph "Parallel Configuration for High Current" N["Current Sharing Bus"] --> O["VBMB1302
Device 1"] N --> P["VBMB1302
Device 2"] N --> Q["VBMB1302
Device 3"] O --> R["Combined Output"] P --> R Q --> R end end subgraph "System Power Rail Distribution" S["12V Input"] --> T["Multi-Phase Buck Converter"] T --> U["5V Rail"] T --> V["3.3V Rail"] subgraph "Point-of-Load Switches" W["VBG3638
5V Rail Switch"] X["VBG3638
3.3V Rail Switch"] Y["VBG3638
1.8V Rail Switch"] end U --> W V --> X W --> Z["Peripheral Power"] X --> AA["Logic Power"] Y --> AB["Memory Power"] end style C fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style K fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style W fill:#fff3e0,stroke:#ff9800,stroke-width:2px

AC-DC Front-End & Protection Circuit Topology Detail

graph LR subgraph "PFC Stage with High-Voltage MOSFET" A["AC Input 85-265V"] --> B["Bridge Rectifier"] B --> C["PFC Inductor"] C --> D["PFC Switching Node"] D --> E["VBPB165R15S
650V/15A (TO3P)"] E --> F["400VDC Bus"] G["PFC Controller"] --> H["Isolated Gate Driver
(e.g., Si823x)"] H --> E F -->|Voltage Feedback| G end subgraph "Protection Circuits Network" subgraph "Overvoltage Protection" I["TVS Diode Array
SMCJ Series"] --> J["AC Input"] K["Voltage Clamp"] --> L["Gate Driver ICs"] end subgraph "Overcurrent Protection" M["Current Sense
Shunt Resistor"] --> N["High-Speed Comparator"] O["Hall-Effect Sensor"] --> P["Current Monitor IC"] N --> Q["Fault Signal"] P --> Q Q --> R["System Shutdown"] end subgraph "Thermal Protection" S["NTC Thermistor"] --> T["Temperature Monitor"] U["Thermal Diode"] --> V["Digital Temp Sensor"] T --> W["Fan Control PWM"] V --> W W --> X["Cooling Fan"] end end subgraph "Redundant Power Supply Configuration" Y["Primary AC Input"] --> Z["OR-ing MOSFET"] AA["Secondary AC Input"] --> Z subgraph "OR-ing Circuit" BB["VBPB165R15S
OR-ing Switch"] end Z --> BB BB --> CC["Common DC Bus"] DD["Current Balance"] --> Z end subgraph "EMC Suppression Components" EE["X7R Ceramic Capacitors"] --> FF["VBMB1302 Drain-Source"] GG["Ferrite Beads"] --> HH["Gate Drive Lines"] II["RC Snubber Network"] --> JJ["VBPB165R15S Drain-Source"] KK["EMI Filter"] --> LL["AC Input Lines"] end style E fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style BB fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
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