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Practical Design of the Power Chain for Server Remote Operation and Maintenance Systems: Balancing Power Density, Efficiency, and Ultimate Reliability
Server Remote O&M Power Chain System Topology Diagram

Server Remote O&M Power Chain System Overall Topology Diagram

graph LR %% Primary Power Conversion Section subgraph "Primary DC-DC Conversion & High-Current POL" AC_DC["AC Input
Power Supply"] --> RECT["AC-DC Rectifier & PFC"] RECT --> HV_BUS["High-Voltage DC Bus
48VDC"] HV_BUS --> BUCK_PRIMARY["Primary Synchronous Buck Converter"] subgraph "Primary Side High-Current MOSFET Array" Q_PRIMARY1["VBGQT1801
80V/350A"] Q_PRIMARY2["VBGQT1801
80V/350A"] end BUCK_PRIMARY --> Q_PRIMARY1 BUCK_PRIMARY --> Q_PRIMARY2 Q_PRIMARY1 --> INT_BUS["Intermediate Bus
12V/5V"] Q_PRIMARY2 --> INT_BUS end %% Intermediate Voltage Distribution Section subgraph "Intermediate Voltage Distribution & Fan/Pump Drive" INT_BUS --> DISTRIBUTION["Voltage Distribution Network"] subgraph "Distribution MOSFET Array" Q_DIST1["VBQF1104N
100V/21A"] Q_DIST2["VBQF1104N
100V/21A"] Q_DIST3["VBQF1104N
100V/21A"] end DISTRIBUTION --> Q_DIST1 DISTRIBUTION --> Q_DIST2 DISTRIBUTION --> Q_DIST3 Q_DIST1 --> FAN_DRIVE["Cooling Fan Drive"] Q_DIST2 --> PUMP_DRIVE["Liquid Pump Drive"] Q_DIST3 --> BACKUP_PWR["Backup Power Circuit"] FAN_DRIVE --> FAN["Cooling Fan"] PUMP_DRIVE --> PUMP["Liquid Cooling Pump"] BACKUP_PWR --> UPS["Uninterruptible Power"] end %% Motherboard-Level POL Section subgraph "Motherboard-Level POL & Precision Load Switching" INT_BUS --> POL_CONVERTER["POL DC-DC Converter"] subgraph "POL MOSFET Array" Q_POL1["VBQG7313
30V/12A"] Q_POL2["VBQG7313
30V/12A"] Q_POL3["VBQG7313
30V/12A"] Q_POL4["VBQG7313
30V/12A"] end POL_CONVERTER --> Q_POL1 POL_CONVERTER --> Q_POL2 POL_CONVERTER --> Q_POL3 POL_CONVERTER --> Q_POL4 Q_POL1 --> CPU_VRM["CPU/GPU VRM"] Q_POL2 --> MEM_PWR["Memory Module Power"] Q_POL3 --> STORAGE_PWR["Storage Controller"] Q_POL4 --> PERIPH_PWR["Peripheral ICs"] end %% Control & Management Section subgraph "Baseboard Management Controller (BMC) & Monitoring" BMC["BMC Controller"] --> POWER_SEQ["Power Sequencing Logic"] BMC --> FAULT_MGMT["Fault Management"] BMC --> TELEMETRY["System Telemetry"] subgraph "Monitoring Sensors" TEMP_SENSOR["Temperature Sensors"] CURRENT_SENSE["Current Sense Amplifiers"] VOLT_MON["Voltage Monitors"] end TEMP_SENSOR --> BMC CURRENT_SENSE --> BMC VOLT_MON --> BMC BMC --> PMBUS["PMBus/I2C Interface"] end %% Thermal Management Section subgraph "Hierarchical Thermal Management Architecture" COOLING_LEVEL1["Level 1: Liquid/Air Cooling"] --> Q_PRIMARY1 COOLING_LEVEL1 --> Q_PRIMARY2 COOLING_LEVEL2["Level 2: Forced Air Cooling"] --> Q_DIST1 COOLING_LEVEL2 --> Q_DIST2 COOLING_LEVEL3["Level 3: PCB Thermal Design"] --> Q_POL1 COOLING_LEVEL3 --> Q_POL2 FAN --> COOLING_LEVEL2 PUMP --> COOLING_LEVEL1 end %% Protection & EMI Section subgraph "Protection & EMC Design" SNUBBER["RC Snubber Circuit"] --> Q_PRIMARY1 TVS_ARRAY["TVS Protection"] --> GATE_DRIVER["Gate Driver ICs"] subgraph "EMC Filtering" EMI_FILTER["EMI Input Filter"] DECOUPLING["High-Frequency Decoupling"] SHIELDING["Partitioned Ground & Shielding"] end EMI_FILTER --> RECT DECOUPLING --> Q_POL1 SHIELDING --> HIGH_SPEED_BUS["PCIe/Ethernet"] end %% Connections BMC --> POWER_SEQ --> Q_PRIMARY1 BMC --> POWER_SEQ --> Q_POL1 FAULT_MGMT --> SHUTDOWN["System Shutdown"] TELEMETRY --> CLOUD["Cloud O&M Interface"] PMBUS --> DIGITAL_CTRL["Digital Power Management"] %% Style Definitions style Q_PRIMARY1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_DIST1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_POL1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px

As data centers and server farms evolve towards higher compute density, greater energy efficiency, and stringent reliability requirements for 24/7 operation, their internal power delivery and management systems are the critical backbone. A well-designed power chain is the physical foundation for servers and their support infrastructure to achieve stable voltage rails, high-efficiency power conversion, and resilient operation under fluctuating loads and harsh thermal conditions.
Building such a chain presents multi-dimensional challenges: How to maximize power density without compromising thermal performance? How to ensure the long-term reliability of power semiconductors in environments with limited cooling and continuous operation? How to intelligently manage power sequencing, fault protection, and efficiency across multiple voltage domains? The answers lie within the strategic selection and application of key power components.
I. Three Dimensions for Core Power Component Selection: Coordinated Consideration of Voltage, Current, and Topology
1. Primary DC-DC Conversion & High-Current POL (Point-of-Load): The Engine of Power Density
The key device is the VBGQT1801 (80V/350A/TOLL, SGT MOSFET).
Voltage Stress & Current Handling Analysis: With a VDS of 80V, it is ideally suited for intermediate bus architectures (e.g., 48V to 12V/5V) common in modern servers. Its ultra-low RDS(on) of 1mΩ (@10V) and staggering current rating of 350A make it a cornerstone for high-power, high-efficiency synchronous buck converters. This enables extremely high current handling in a compact footprint, directly increasing power density.
Efficiency and Thermal Design Relevance: The exceptionally low conduction loss (P_cond = I² × RDS(on)) is paramount for multi-kilowatt power stages. The TOLL package offers an excellent thermal path to the heatsink. In a high-frequency switching topology (e.g., 300-500kHz), its SGT (Shielded Gate Trench) technology ensures low switching losses. Thermal design must focus on managing the high absolute power dissipation, requiring high-performance thermal interface materials and forced air or liquid cooling on the shared heatsink.
System Impact: Using this device in the primary conversion stage or for high-current CPU/GPU VRMs minimizes voltage drop and thermal hotspots, directly contributing to system-level efficiency targets (e.g., Titanium or Platinum PSU ratings) and enabling more compact, higher-rack-unit density designs.
2. Intermediate Voltage Distribution & Fan/ Pump Drive: The Workhorse for System Support
The key device is the VBQF1104N (100V/21A/DFN8(3x3), Trench MOSFET).
Role in Power Chain: This component is perfect for secondary power distribution, such as converting 12V to lower voltage rails, or driving higher-power auxiliary systems like cooling fans, pumps, and backup power circuits. Its 100V rating provides ample margin in 48V or 12V systems.
Balance of Performance and Size: With an RDS(on) of 36mΩ (@10V) and a current capability of 21A, it offers a excellent balance between low conduction loss and the space-saving benefits of the DFN8 (3x3) package. This allows for decentralized power management close to the load, reducing distribution losses.
Reliability in Constant Operation: The robust Trench technology and compact package are suitable for always-on applications. Its low gate charge facilitates efficient high-frequency switching for DC-DC conversion stages dedicated to memory, storage, or network controllers.
3. Motherboard-Level POL & Precision Load Switching: The Nerve Endings for Digital Control
The key device is the VBQG7313 (30V/12A/DFN6(2x2), Trench MOSFET).
Ultimate Integration for Fine-Grained Control: This MOSFET is engineered for the final stage of power delivery—directly powering ASICs, memory modules, and peripheral ICs from low-voltage rails (e.g., 5V, 3.3V, 1.8V). Its extremely low RDS(on) of 20mΩ (@10V) in a minuscule DFN6 (2x2) package is critical for minimizing losses at the point of load.
Intelligent Power Management Execution: It acts as the perfect execution unit for the Baseboard Management Controller (BMC). The BMC can use these MOSFETs for sequenced power-up/down of various subsystems, individual voltage rail enabling/disabling for fault isolation, and dynamic voltage scaling. The low Vth of 1.7V ensures compatibility with low-voltage logic signals from management ICs.
PCB Layout and Thermal Considerations: While its power dissipation is lower, the tiny package demands careful PCB layout. Adequate copper pouring and thermal vias under the package are essential to conduct heat into the inner layers of the motherboard, preventing local overheating and ensuring long-term reliability.
II. System Integration Engineering Implementation
1. Hierarchical Thermal Management Architecture
Level 1 (High-Power): For devices like the VBGQT1801, implement direct-attachment to a liquid-cooled cold plate or a high-performance finned heatsink with forced air from system fans.
Level 2 (Medium-Power): For components like the VBQF1104N on daughter cards, use localized heatsinks or rely on optimized board-level copper areas and airflow from adjacent fans.
Level 3 (Low-Power/Board-Level): For VBQG7313 MOSFETs on the motherboard, thermal management is primarily achieved through intelligent PCB stack-up design—using thick internal copper planes and thermal vias to spread heat—coupled with the overall server airflow.
2. Electromagnetic Compatibility (EMC) and Signal Integrity Design
Switching Loop Minimization: For converters using VBGQT1801 and VBQF1104N, employ an ultra-compact power loop layout with low-ESR/ESL ceramic capacitors placed as close as possible to the switch nodes. This is critical to contain high di/dt noise.
Decoupling and Filtering: Place high-frequency decoupling capacitors near the VBQG7313 devices to provide clean power to sensitive digital loads and prevent noise propagation.
Shielding and Grounding: Use partitioned ground planes and, where necessary, shielding cans over noisy power circuits to prevent interference with sensitive high-speed data lines (PCIe, Ethernet).
3. Reliability Enhancement and Predictive Health
Electrical Stress Protection: Implement RC snubbers across switch nodes and use TVS diodes on gate drives to protect against voltage transients.
Fault Diagnosis: Utilize the server's BMC to monitor:
Temperature: Via NTC thermistors on heatsinks and key PCB locations.
Current: Using high-side current sense amplifiers on critical rails.
Voltage: Precision monitoring of all output rails for under/over-voltage events.
Predictive Maintenance: The BMC can trend parameters like MOSFET case temperature and power supply efficiency over time. Advanced systems could correlate increased thermal resistance or gradual efficiency drop with potential failure modes, enabling proactive component replacement during scheduled maintenance.
III. Performance Verification and Testing Protocol
1. Key Test Items and Standards
Efficiency Mapping: Test power conversion stages from input to output across the entire load range (10%-100%) at nominal and extreme temperatures.
Thermal Cycling and High-Temperature Operating Life (HTOL): Subject subsystems to extended periods at elevated temperatures (e.g., 85°C ambient) to accelerate aging and validate thermal design.
Power Cycling and Transient Response Test: Simulate rapid load changes typical of CPU workload shifts to verify stability and response time of the POL converters.
Electromagnetic Compatibility (EMC) Test: Ensure compliance with relevant ITE standards (e.g., FCC Part 15, CISPR 32) for conducted and radiated emissions.
Reliability Demonstration Test (RDT): Perform accelerated life testing on the complete power delivery system to statistically demonstrate Mean Time Between Failures (MTBF) targets.
2. Design Verification Example
Test data from a 3kW server power shelf (48V to 12V intermediate bus, 25°C ambient) might show:
The primary conversion stage using VBGQT1801 achieves peak efficiency of >98%.
A motherboard POL converter using VBQG7313 for a 1.8V/10A rail maintains efficiency above 92% and a case temperature below 65°C under full load.
The system passes 1000-hour continuous burn-in testing at 50°C chamber temperature with no performance degradation.
IV. Solution Scalability
1. Adjustments for Different Server Tiers
High-Density Compute/GPU Servers: Maximize the use of VBGQT1801 in parallel configurations for 1kW+ VRMs. Increase the count of VBQG7313 devices for fine-grained power management of numerous memory and accelerator chips.
Storage Servers: Prioritize efficiency in the intermediate distribution (VBQF1104N) and drive motor control circuits. Power density may be slightly less critical than in compute nodes.
Edge Computing/Telecom Servers: Focus on ruggedness and wide temperature range operation. The robust packages of VBQF1104N (DFN8) and VBQG7313 (DFN6) are advantageous in potentially less-controlled environments.
2. Integration of Cutting-Edge Technologies
Digital Power Management: Integrate drivers and controllers with PMBus/I2C interfaces, allowing the BMC to digitally tune voltages, monitor telemetry, and control power sequencing in real-time.
Gallium Nitride (GaN) Roadmap: For the next generation of ultra-high power density and efficiency:
Phase 1: Maintain core Silicon-based solution (VBGQT1801, VBQF1104N) for proven reliability.
Phase 2: Introduce GaN HEMTs in the primary 48V-12V conversion stage to push switching frequencies into the MHz range, dramatically reducing magnetic component size.
AI-Optimized Power Management: Use BMC and system-level analytics to predict workload patterns and dynamically adjust power supply operating points (e.g., phase shedding, frequency dithering) for optimal energy efficiency across varying utilization.
Conclusion
The power chain design for server remote operation and maintenance systems is a critical exercise in balancing extreme power density, unwavering efficiency, and bulletproof reliability. The tiered optimization scheme proposed—employing ultra-high-current devices like the VBGQT1801 at the primary conversion level, versatile medium-power components like the VBQF1104N for distribution, and highly integrated low-voltage switches like the VBQG7313 at the point-of-load—provides a scalable and robust foundation for modern server architectures.
As server management becomes increasingly autonomous and data-driven, the power chain evolves from a passive supplier to an intelligent, monitored, and optimized subsystem. By adhering to rigorous design and validation standards while leveraging this component framework, engineers can build power infrastructures that deliver not only the watts needed for computation but also the resilience and insight required for truly remote, reliable, and efficient operation. This is the engineering imperative for powering the always-on digital world.

Detailed Topology Diagrams

Primary DC-DC Conversion & High-Current POL Topology Detail

graph LR subgraph "48V to 12V Intermediate Bus Converter" INPUT["48V DC Input"] --> BUCK["Synchronous Buck Converter"] subgraph "High-Current MOSFET Pair" Q_HIGH["VBGQT1801
High-Side MOSFET"] Q_LOW["VBGQT1801
Low-Side MOSFET"] end BUCK --> Q_HIGH BUCK --> Q_LOW Q_HIGH --> SW_NODE["Switching Node"] Q_LOW --> GND SW_NODE --> INDUCTOR["Power Inductor"] INDUCTOR --> OUTPUT_CAP["Output Capacitor Bank"] OUTPUT_CAP --> INT_BUS["12V Intermediate Bus"] CONTROLLER["Buck Controller"] --> DRIVER["Gate Driver"] DRIVER --> Q_HIGH DRIVER --> Q_LOW end subgraph "High-Current CPU/GPU VRM" INT_BUS --> VRM_CONVERTER["Multi-Phase VRM"] subgraph "Parallel MOSFET Array" Q_VRM1["VBGQT1801"] Q_VRM2["VBGQT1801"] Q_VRM3["VBGQT1801"] Q_VRM4["VBGQT1801"] end VRM_CONVERTER --> Q_VRM1 VRM_CONVERTER --> Q_VRM2 VRM_CONVERTER --> Q_VRM3 VRM_CONVERTER --> Q_VRM4 Q_VRM1 --> CPU_OUT["CPU/GPU Power Rail"] Q_VRM2 --> CPU_OUT Q_VRM3 --> CPU_OUT Q_VRM4 --> CPU_OUT VRM_CTRL["Digital VRM Controller"] --> PHASE_DRIVER["Multi-Phase Driver"] PHASE_DRIVER --> Q_VRM1 end style Q_HIGH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_VRM1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intermediate Voltage Distribution & Fan Drive Topology Detail

graph LR subgraph "Secondary Power Distribution (12V to 5V/3.3V)" INPUT_12V["12V Input"] --> DIST_BUCK["Synchronous Buck Converter"] subgraph "Distribution MOSFET Pair" Q_DIST_H["VBQF1104N
High-Side"] Q_DIST_L["VBQF1104N
Low-Side"] end DIST_BUCK --> Q_DIST_H DIST_BUCK --> Q_DIST_L Q_DIST_H --> DIST_SW["Switching Node"] Q_DIST_L --> GND DIST_SW --> DIST_INDUCTOR["Inductor"] DIST_INDUCTOR --> DIST_CAP["Output Caps"] DIST_CAP --> LOWER_RAIL["5V/3.3V Rail"] DIST_CTRL["Distribution Controller"] --> DIST_DRIVER["Driver"] DIST_DRIVER --> Q_DIST_H DIST_DRIVER --> Q_DIST_L end subgraph "Fan & Pump Drive Circuit" FAN_PWR["12V Fan Power"] --> FAN_SWITCH["Fan Control Switch"] subgraph "Fan Control MOSFET" Q_FAN["VBQF1104N"] end FAN_SWITCH --> Q_FAN Q_FAN --> FAN_LOAD["Cooling Fan"] BMC_GPIO["BMC PWM Signal"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> Q_FAN FAN_LOAD --> FAN_GND end subgraph "Backup Power Switching" MAIN_PWR["Main Power"] --> BACKUP_SW["Power Switch"] BACKUP_PWR["Backup Power"] --> BACKUP_SW subgraph "Backup Switch MOSFET" Q_BACKUP["VBQF1104N"] end BACKUP_SW --> Q_BACKUP Q_BACKUP --> CRITICAL_LOAD["Critical Load"] POWER_MGMT["Power Management IC"] --> Q_BACKUP end style Q_DIST_H fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_FAN fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Motherboard-Level POL & Intelligent Switching Topology Detail

graph LR subgraph "Precision POL Converter (3.3V to 1.8V)" POL_IN["3.3V Input"] --> POL_BUCK["POL Buck Converter"] subgraph "POL MOSFET Pair" Q_POL_H["VBQG7313
High-Side"] Q_POL_L["VBQG7313
Low-Side"] end POL_BUCK --> Q_POL_H POL_BUCK --> Q_POL_L Q_POL_H --> POL_SW["Switching Node"] Q_POL_L --> POL_GND POL_SW --> POL_INDUCTOR["Small Inductor"] POL_INDUCTOR --> POL_CAP["MLCC Caps"] POL_CAP --> ASIC_PWR["ASIC Power Rail"] POL_CTRL["POL Controller"] --> POL_DRIVER["Driver"] POL_DRIVER --> Q_POL_H POL_DRIVER --> Q_POL_L end subgraph "Intelligent Load Switching & Sequencing" BMC_SEQ["BMC Sequencing Logic"] --> LOAD_SWITCH["Load Switch Control"] subgraph "Load Switch MOSFETs" Q_LOAD1["VBQG7313
Memory Power"] Q_LOAD2["VBQG7313
Storage Power"] Q_LOAD3["VBQG7313
Peripheral Power"] end LOAD_SWITCH --> Q_LOAD1 LOAD_SWITCH --> Q_LOAD2 LOAD_SWITCH --> Q_LOAD3 Q_LOAD1 --> MEM_PWR["DDR Memory"] Q_LOAD2 --> SSD_PWR["NVMe SSD"] Q_LOAD3["VBQG7313
Peripheral Power"] --> NIC_PWR["Network Interface"] end subgraph "Dynamic Voltage Scaling" DVS_CONTROLLER["DVS Controller"] --> Q_DVS["VBQG7313"] Q_DVS --> CPU_CORE["CPU Core Rail"] VOLTAGE_DAC["Voltage DAC"] --> Q_DVS BMC["BMC"] --> VOLTAGE_DAC end style Q_POL_H fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOAD1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
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