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Power MOSFET Selection Analysis for High-Density, High-Efficiency Data Lake Storage Power Systems – A Case Study on Server Power Supplies, PoL Converters, and Intelligent Power Management
Data Lake Storage Power System Topology Diagram

Data Lake Storage Power System Overall Topology Diagram

graph LR %% AC Input & Primary Power Conversion subgraph "AC-DC Input & PFC Stage" AC_IN["Three-Phase 400VAC Input
Data Center Grid"] --> EMI_FILTER["EMI Filter
Class B Compliance"] EMI_FILTER --> PFC_BRIDGE["Three-Phase Rectifier"] PFC_BRIDGE --> PFC_INDUCTOR["PFC Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] subgraph "PFC Primary MOSFET Array" Q_PFC1["VBP16R67S
600V/67A"] Q_PFC2["VBP16R67S
600V/67A"] end PFC_SW_NODE --> Q_PFC1 PFC_SW_NODE --> Q_PFC2 Q_PFC1 --> HV_BUS["High-Voltage DC Bus
~400VDC"] Q_PFC2 --> HV_BUS PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> Q_PFC1 PFC_DRIVER --> Q_PFC2 end %% Isolation & Intermediate Bus Conversion subgraph "Isolated DC-DC & Intermediate Bus Converter" HV_BUS --> LLC_TANK["LLC Resonant Tank"] LLC_TANK --> ISO_TRANS["Isolation Transformer"] ISO_TRANS --> LLC_SW_NODE["LLC Switching Node"] subgraph "LLC Primary MOSFET Array" Q_LLC1["VBP16R67S
600V/67A"] Q_LLC2["VBP16R67S
600V/67A"] end LLC_SW_NODE --> Q_LLC1 LLC_SW_NODE --> Q_LLC2 Q_LLC1 --> GND_PRI Q_LLC2 --> GND_PRI ISO_TRANS_SEC["Transformer Secondary"] --> SYNC_RECT["Synchronous Rectification"] SYNC_RECT --> INTER_BUS["Intermediate Bus
12V/48V"] LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["Gate Driver"] LLC_DRIVER --> Q_LLC1 LLC_DRIVER --> Q_LLC2 end %% Point-of-Load Conversion subgraph "Multi-Phase PoL Converters" INTER_BUS --> PHASE1["Phase 1 Buck Converter"] INTER_BUS --> PHASE2["Phase 2 Buck Converter"] INTER_BUS --> PHASE3["Phase 3 Buck Converter"] INTER_BUS --> PHASE4["Phase 4 Buck Converter"] subgraph "PoL Synchronous Buck MOSFETs" Q_POL_HIGH["VBL1602
60V/270A
High Side"] Q_POL_LOW["VBL1602
60V/270A
Low Side"] end PHASE1 --> Q_POL_HIGH PHASE1 --> Q_POL_LOW PHASE2 --> Q_POL_HIGH PHASE2 --> Q_POL_LOW PHASE3 --> Q_POL_HIGH PHASE3 --> Q_POL_LOW PHASE4 --> Q_POL_HIGH PHASE4 --> Q_POL_LOW Q_POL_HIGH --> V_CORE["Core Voltage
0.8-1.2V"] Q_POL_LOW --> GND_POL POL_CONTROLLER["Multi-Phase PWM Controller"] --> POL_DRIVER["High-Current Driver"] POL_DRIVER --> Q_POL_HIGH POL_DRIVER --> Q_POL_LOW V_CORE --> CPU_LOAD["CPU/ASIC Load"] V_CORE --> MEMORY_LOAD["Memory Load"] V_CORE --> STORAGE_CTRL["Storage Controller"] end %% Intelligent Power Management subgraph "Intelligent Power Distribution & Management" AUX_POWER["Auxiliary Power Supply
12V/5V/3.3V"] --> BMC["Baseboard Management Controller"] BMC --> SW_SEQUENCE["Power Sequencing Logic"] subgraph "Hot-Swap & Load Switch Channels" SW_CPU["VBQF2305
CPU Power Enable"] SW_MEM["VBQF2305
Memory Power Enable"] SW_STORAGE["VBQF2305
Storage Blade Enable"] SW_FAN["VBQF2305
Fan Tray Enable"] SW_PSU["VBQF2305
PSU Redundancy Control"] end SW_SEQUENCE --> SW_CPU SW_SEQUENCE --> SW_MEM SW_SEQUENCE --> SW_STORAGE SW_SEQUENCE --> SW_FAN SW_SEQUENCE --> SW_PSU SW_CPU --> CPU_MODULE["CPU Module"] SW_MEM --> MEMORY_MODULE["Memory Module"] SW_STORAGE --> STORAGE_BLADE["Storage Blade"] SW_FAN --> COOLING_FAN["Cooling Fan Tray"] SW_PSU --> PSU_REDUNDANCY["Redundant PSU"] end %% System Monitoring & Protection subgraph "System Monitoring & Protection Circuits" CURRENT_SENSE["High-Precision Current Sensors"] --> ADC["Analog-to-Digital Converter"] VOLTAGE_MON["Voltage Monitoring"] --> ADC TEMP_SENSORS["Temperature Sensors
(NTC/RTD)"] --> ADC ADC --> BMC subgraph "Protection Circuits" OVP["Over-Voltage Protection"] OCP["Over-Current Protection"] OTP["Over-Temperature Protection"] UVP["Under-Voltage Protection"] end BMC --> OVP BMC --> OCP BMC --> OTP BMC --> UVP OVP --> SHUTDOWN_SIGNAL["System Shutdown"] OCP --> SHUTDOWN_SIGNAL OTP --> SHUTDOWN_SIGNAL UVP --> SHUTDOWN_SIGNAL end %% Communication & Control subgraph "System Communication Network" BMC --> IPMI["IPMI Interface"] BMC --> I2C_BUS["I2C Bus"] BMC --> PMBUS["PMBus Interface"] I2C_BUS --> PSU_MON["PSU Monitoring"] I2C_BUS --> FAN_CONTROLLER["Fan Speed Controller"] I2C_BUS --> TEMP_SENSORS PMBUS --> DIGITAL_POT["Digital Potentiometers"] PMBUS --> MARGINING["Voltage Margining"] BMC --> NETWORK["Ethernet Network"] NETWORK --> DCIM["Data Center Infrastructure Management"] end %% Thermal Management subgraph "Hierarchical Thermal Management" COLD_PLATE["Liquid Cold Plate"] --> Q_POL_HIGH COLD_PLATE --> Q_POL_LOW HEATSINK_FORCED["Forced Air Heatsink"] --> Q_PFC1 HEATSINK_FORCED --> Q_LLC1 PCB_COPPER["PCB Thermal Planes"] --> CONTROL_ICS["Control ICs"] TEMP_SENSORS --> THERMAL_CONTROLLER["Thermal Management Controller"] THERMAL_CONTROLLER --> FAN_SPEED["Fan Speed PWM"] THERMAL_CONTROLLER --> PUMP_SPEED["Pump Speed Control"] FAN_SPEED --> COOLING_FANS["System Fans"] PUMP_SPEED --> LIQUID_PUMP["Liquid Cooling Pump"] end %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_POL_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SW_CPU fill:#fff3e0,stroke:#ff9800,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the era of big data and cloud computing, data lake storage infrastructure forms the critical backbone for massive-scale data processing and archiving. The performance, uptime, and operational cost of these facilities are directly governed by the capabilities of their power delivery and management systems. High-efficiency server power supply units (PSUs), point-of-load (PoL) converters, and rack-level intelligent power distribution units act as the facility's "energy heart and arteries," responsible for providing stable, high-density, and precisely managed power to storage arrays, compute nodes, and networking gear. The selection of power MOSFETs profoundly impacts system power density, conversion efficiency, thermal management, and overall reliability. This article, targeting the demanding application scenario of data lake storage—characterized by stringent requirements for 24/7 operation, high power density, exceptional efficiency, and intelligent power sequencing—conducts an in-depth analysis of MOSFET selection considerations for key power nodes, providing a complete and optimized device recommendation scheme.
Detailed MOSFET Selection Analysis
1. VBP16R67S (N-MOS, 600V, 67A, TO-247)
Role: Primary-side main switch in high-efficiency server PFC (Power Factor Correction) or high-voltage DC-DC conversion stage (e.g., 48V to 12V intermediate bus converter).
Technical Deep Dive:
Voltage Stress & Topology Suitability: In a 3-phase 400VAC input or a high-voltage DC bus (e.g., 380VDC) architecture common in data centers, the 600V rating provides a robust safety margin. Utilizing SJ_Multi-EPI (Super-Junction Multi-Epitaxial) technology, this device offers an exceptional balance of low on-resistance (34mΩ @10V) and high voltage capability. Its 67A continuous current rating makes it ideal for high-power server PSUs (e.g., 3kW+) or high-power density bus converters, enabling high-frequency operation to reduce magnetic component size and achieve critical power density targets for rack-mounted equipment.
Efficiency & Thermal Performance: The low Rds(on) directly minimizes conduction losses in the primary power stage. The TO-247 package facilitates excellent thermal coupling to heatsinks or cold plates, which is essential for managing heat in tightly packed, forced-air or liquid-cooled server racks, thereby ensuring long-term reliability of the core AC-DC or isolation stage.
2. VBL1602 (N-MOS, 60V, 270A, TO-263)
Role: Synchronous rectifier or primary switch in high-current, low-voltage DC-DC PoL converters (e.g., 12V/48V to sub-1V for CPUs/ASICs, or 48V to 12V for storage drives).
Extended Application Analysis:
Ultimate Efficiency for Core Power Delivery: The final power delivery to storage controllers, compute processors, and memory requires very low voltage at extremely high currents. The 60V-rated VBL1602 provides ample margin for 12V or 48V intermediate bus voltages. Featuring advanced Trench technology, its Rds(on) is as low as 2.5mΩ at 10V drive, combined with a massive 270A continuous current capability. This minimizes conduction losses, which is the dominant loss factor in high-current PoL converters.
Power Density Enabler: The TO-263 (D2PAK) package offers superior power handling and heat dissipation in a compact footprint. Its extremely low on-resistance and gate charge allow for high-frequency multiphase buck converter designs, drastically reducing the size and volume of output inductors and capacitors. This is paramount for fitting power delivery solutions directly on server motherboards or storage controller boards within strict spatial constraints.
Dynamic Response: Excellent switching characteristics ensure fast transient response to the rapid load steps typical of modern compute and storage workloads, maintaining tight voltage regulation essential for data integrity and component lifespan.
3. VBQF2305 (P-MOS, -30V, -52A, DFN8(3X3))
Role: Intelligent hot-swap control, rail sequencing, and module power enable/disable for storage blades, fan trays, or peripheral modules.
Precision Power & Safety Management:
High-Density Intelligent Control: This P-channel MOSFET in an ultra-compact DFN8(3X3) package combines a low on-resistance (4mΩ @10V) with a -52A current rating. Its -30V rating is perfectly suited for controlling 12V or 5V auxiliary/distribution rails within a server or storage enclosure. It can serve as a high-side load switch, enabling compact, digitally controlled power sequencing and soft-start for various sub-systems, which is critical for preventing inrush currents and ensuring reliable boot-up of complex storage systems.
Efficient & Simple Drive: The low gate threshold (Vth: -3V) and excellent Rds(on) allow for direct and efficient driving by low-voltage system management controllers (BMC, CPLD) or GPIOs, simplifying control circuitry. The small package saves valuable board space on crowded backplanes or system management boards.
Reliability & Protection: The device enables the implementation of electronic fusing, current limiting, and fault isolation at the module level. In case of a fault in a specific storage blade or fan module, it can be quickly disabled, isolating the fault and preventing cascading failures, thereby enhancing overall system availability—a non-negotiable requirement for data lake storage.
System-Level Design and Application Recommendations
Drive Circuit Design Key Points:
High-Voltage Switch Drive (VBP16R67S): Requires a dedicated gate driver capable of handling the Miller plateau effectively. Consider active Miller clamping or a negative turn-off voltage to ensure robust switching and prevent shoot-through in bridge configurations.
High-Current PoL Switch Drive (VBL1602): Must be paired with a high-current drive stage or a dedicated multi-phase PWM controller driver. Careful layout to minimize power loop and gate loop inductance is critical to achieve clean switching, minimize ringing, and prevent voltage spikes that could stress the device.
Intelligent Load Switch (VBQF2305): Can be driven directly by management ICs with level translation if needed. Implementing RC filtering at the gate and TVS protection is recommended to enhance immunity to noise in the complex EMI environment of a server rack.
Thermal Management and EMC Design:
Tiered Thermal Design: VBP16R67S requires a dedicated heatsink, often part of a forced-air tunnel in a PSU. VBL1602 demands careful thermal vias and possibly a coupled inductor heatsink on the motherboard. VBQF2305 can dissipate heat through a well-designed PCB copper plane.
EMI Suppression: Employ snubbers or ferrite beads at switching nodes for VBP16R67S. Use high-frequency decoupling capacitors very close to the drain-source of VBL1602 in PoL circuits. Maintain a clean, low-inductance power plane design for all high-current paths.
Reliability Enhancement Measures:
Adequate Derating: Operate VBP16R67S at no more than 70-80% of its rated voltage in steady state. Monitor the junction temperature of VBL1602 in PoL applications, especially during worst-case compute loads.
Comprehensive Protection: Implement current sensing and fast-trip electronic fusing using the VBQF2305 or its companion controller. Ensure all power stages feature overtemperature and overcurrent protection interlocked with the system manager.
Enhanced Robustness: Use TVS diodes on input power rails and gates where appropriate. Maintain proper creepage and clearance for high-voltage sections to meet safety standards for IT equipment.
Conclusion
In the design of high-density, high-efficiency power systems for data lake storage infrastructure, power MOSFET selection is key to achieving optimal performance per rack unit, maximizing energy efficiency (PUE), and ensuring "always-on" availability. The three-tier MOSFET scheme recommended in this article embodies the design philosophy of high power density, high efficiency, and intelligent management.
Core value is reflected in:
End-to-End Efficiency & Density: From high-efficiency AC-DC conversion (VBP16R67S), to ultra-low loss power delivery at the point of load (VBL1602), and down to intelligent module-level power control (VBQF2305), a complete, efficient, and compact power delivery network from the facility input to the silicon is constructed.
Intelligent Operation & High Availability: The intelligent load switch enables granular power control, fault isolation, and sequenced power-up/down, providing the hardware foundation for remote management, predictive failure analysis, and non-disruptive maintenance, significantly enhancing data center operational efficiency.
Scalability & Future-Readiness: The modular design approach and selected devices allow for power scaling through multiphase interleaving or parallelization, adapting to the continuously increasing power demands of future compute, memory, and storage technologies.
Future Trends:
As data lake storage evolves towards higher rack power densities (30kW+), direct liquid cooling, and advanced power management with AI, power device selection will trend towards:
Wider adoption of SiC MOSFETs in PFC and high-voltage isolation stages for even higher efficiency and power density.
Integrated DrMOS or Smart Power Stages that combine controllers, drivers, and MOSFETs for PoL applications, simplifying design and improving performance.
GaN devices enabling MHz-frequency switching in very high-density intermediate bus converters and PoL regulators, pushing the boundaries of power density and transient response.
This recommended scheme provides a complete power device solution for data lake storage power systems, spanning from the AC input to the silicon load, and from bulk power conversion to intelligent distribution. Engineers can refine and adjust it based on specific rack power levels, cooling architectures (air/liquid), and redundancy requirements to build robust, efficient, and manageable power infrastructure that supports the relentless growth of the data-driven world.

Detailed Topology Diagrams

Server PFC & Primary Side Power Topology Detail

graph LR subgraph "Three-Phase PFC Boost Converter" AC_IN["Three-Phase 400VAC"] --> EMI["EMI Filter"] EMI --> RECT["Three-Phase Rectifier"] RECT --> L_PFC["PFC Boost Inductor"] L_PFC --> SW_NODE["Switching Node"] subgraph "High-Voltage MOSFET Array" Q1["VBP16R67S
600V/67A"] Q2["VBP16R67S
600V/67A"] end SW_NODE --> Q1 SW_NODE --> Q2 Q1 --> HV_BUS["400VDC Bus"] Q2 --> HV_BUS HV_CAP["High-Voltage Bus Capacitors"] --> HV_BUS CONTROLLER["PFC Controller"] --> DRIVER["Gate Driver"] DRIVER --> Q1 DRIVER --> Q2 HV_BUS -->|Voltage Feedback| CONTROLLER end subgraph "LLC Resonant Isolated Converter" HV_BUS --> RES_TANK["LLC Resonant Tank
Lr, Lm, Cr"] RES_TANK --> TRANS_PRI["Transformer Primary"] TRANS_PRI --> LLC_SW["LLC Switch Node"] subgraph "Primary Side Switches" Q3["VBP16R67S
600V/67A"] Q4["VBP16R67S
600V/67A"] end LLC_SW --> Q3 LLC_SW --> Q4 Q3 --> GND Q4 --> GND TRANS_SEC["Transformer Secondary"] --> SYNC_RECT["Synchronous Rectifier"] SYNC_RECT --> INT_BUS["Intermediate Bus
12V/48V"] LLC_CTRL["LLC Controller"] --> LLC_DRV["Gate Driver"] LLC_DRV --> Q3 LLC_DRV --> Q4 CURRENT_SENSE["Current Transformer"] -->|Resonant Current| LLC_CTRL end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q3 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Multi-Phase PoL Converter Topology Detail

graph LR subgraph "Multi-Phase Buck Converter Channel" VIN["12V/48V Intermediate Bus"] --> PHASE_IN["Phase Input"] subgraph "Synchronous Buck MOSFET Pair" Q_HIGH["VBL1602
High Side
60V/270A"] Q_LOW["VBL1602
Low Side
60V/270A"] end PHASE_IN --> Q_HIGH Q_HIGH --> SW_NODE["Switch Node"] SW_NODE --> Q_LOW Q_LOW --> GND SW_NODE --> FILTER_INDUCTOR["Output Inductor"] FILTER_INDUCTOR --> OUTPUT_CAP["Output Capacitors"] OUTPUT_CAP --> VOUT["Core Voltage
0.8-1.2V"] end subgraph "4-Phase Interleaved Operation" PHASE1["Phase 1
0°"] --> VOUT PHASE2["Phase 2
90°"] --> VOUT PHASE3["Phase 3
180°"] --> VOUT PHASE4["Phase 4
270°"] --> VOUT end subgraph "Controller & Driver Section" MULTI_PHASE_CTRL["Multi-Phase PWM Controller"] --> CURRENT_BALANCE["Current Balancing Logic"] CURRENT_BALANCE --> DRIVER_ARRAY["Driver Array"] DRIVER_ARRAY --> Q_HIGH DRIVER_ARRAY --> Q_LOW VOUT -->|Voltage Feedback| MULTI_PHASE_CTRL CURRENT_SENSE["Inductor Current Sensing"] -->|Current Feedback| CURRENT_BALANCE end subgraph "Load Distribution" VOUT --> CPU_CORES["CPU Cores"] VOUT --> ASIC_ARRAY["ASIC Array"] VOUT --> MEMORY_POWER["Memory Power"] VOUT --> STORAGE_CTRL["Storage Controllers"] end style Q_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOW fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Intelligent Power Management Topology Detail

graph LR subgraph "Hot-Swap & Load Switch Control" BMC["Baseboard Management Controller"] --> GPIO["GPIO Expander"] GPIO --> LEVEL_SHIFTER["Level Shifter"] subgraph "P-Channel Load Switch Array" SW1["VBQF2305
Channel 1"] SW2["VBQF2305
Channel 2"] SW3["VBQF2305
Channel 3"] SW4["VBQF2305
Channel 4"] end LEVEL_SHIFTER --> SW1 LEVEL_SHIFTER --> SW2 LEVEL_SHIFTER --> SW3 LEVEL_SHIFTER --> SW4 VIN_12V["12V Auxiliary Rail"] --> SW1 VIN_12V --> SW2 VIN_12V --> SW3 VIN_12V --> SW4 SW1 --> LOAD1["CPU Module Power"] SW2 --> LOAD2["Memory Module Power"] SW3 --> LOAD3["Storage Blade Power"] SW4 --> LOAD4["Fan Tray Power"] end subgraph "Current Limiting & Protection" CURRENT_SENSE_AMP["Current Sense Amplifier"] --> COMPARATOR["Comparator"] COMPARATOR --> FAULT_LATCH["Fault Latch"] FAULT_LATCH --> SHUTDOWN["Shutdown Signal"] SHUTDOWN --> SW1 SHUTDOWN --> SW2 SHUTDOWN --> SW3 SHUTDOWN --> SW4 end subgraph "Power Sequencing Logic" SEQ_CONTROLLER["Sequencing Controller"] --> DELAY1["Delay 1"] SEQ_CONTROLLER --> DELAY2["Delay 2"] SEQ_CONTROLLER --> DELAY3["Delay 3"] SEQ_CONTROLLER --> DELAY4["Delay 4"] DELAY1 --> SW1 DELAY2 --> SW2 DELAY3 --> SW3 DELAY4 --> SW4 end subgraph "System Monitoring" VOLTAGE_MON["Voltage Monitors"] --> ADC["ADC"] CURRENT_MON["Current Monitors"] --> ADC TEMP_MON["Temperature Sensors"] --> ADC ADC --> BMC BMC --> ALERT["System Alerts"] BMC --> LOGGING["Event Logging"] end style SW1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px
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