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Power MOSFET Selection Analysis for Dual-Socket Virtualization Server Power Supply Units – A Case Study on High Power Density, High Efficiency, and High Reliability
Dual-Socket Virtualization Server PSU System Topology Diagram

Dual-Socket Virtualization Server PSU Overall Topology Diagram

graph LR %% Input & Primary Conversion Section subgraph "AC Input & Totem-Pole PFC Stage" AC_IN["AC Input
85-265VAC Wide Range"] --> EMI_FILTER["EMI Filter
Line Filter & X/Y Caps"] EMI_FILTER --> PFC_BRIDGE["Totem-Pole Bridgeless PFC"] subgraph "PFC High-Voltage MOSFET Array" Q_PFC1["VBP18R47S
800V/47A TO-247"] Q_PFC2["VBP18R47S
800V/47A TO-247"] Q_PFC3["VBP18R47S
800V/47A TO-247"] Q_PFC4["VBP18R47S
800V/47A TO-247"] end PFC_BRIDGE --> Q_PFC1 PFC_BRIDGE --> Q_PFC2 PFC_BRIDGE --> Q_PFC3 PFC_BRIDGE --> Q_PFC4 Q_PFC1 --> HV_BUS["High-Voltage DC Bus
~400VDC"] Q_PFC2 --> HV_BUS Q_PFC3 --> HV_BUS Q_PFC4 --> HV_BUS end %% LLC Resonant Conversion Section subgraph "LLC Resonant DC-DC Stage" HV_BUS --> LLC_RESONANT["LLC Resonant Tank
Lr, Cr, Lm"] LLC_RESONANT --> HF_TRANS["High-Frequency Transformer"] HF_TRANS --> LLC_SEC["Transformer Secondary"] subgraph "Primary Side LLC Switches" Q_LLC1["VBP18R47S
800V/47A TO-247"] Q_LLC2["VBP18R47S
800V/47A TO-247"] end HF_TRANS --> Q_LLC1 HF_TRANS --> Q_LLC2 Q_LLC1 --> GND_PRI Q_LLC2 --> GND_PRI end %% Synchronous Rectification Section subgraph "Synchronous Rectification & Output" LLC_SEC --> SR_NODE["Synchronous Rectification Node"] subgraph "Secondary Side SR MOSFET Array" Q_SR1["VBGM1102
100V/180A TO-220"] Q_SR2["VBGM1102
100V/180A TO-220"] Q_SR3["VBGM1102
100V/180A TO-220"] Q_SR4["VBGM1102
100V/180A TO-220"] end SR_NODE --> Q_SR1 SR_NODE --> Q_SR2 SR_NODE --> Q_SR3 SR_NODE --> Q_SR4 Q_SR1 --> OUTPUT_FILTER["Output Filter
Low-ESR Capacitors"] Q_SR2 --> OUTPUT_FILTER Q_SR3 --> OUTPUT_FILTER Q_SR4 --> OUTPUT_FILTER OUTPUT_FILTER --> DC_OUT["DC Output
12V/48V High Current"] end %% Intermediate Bus & POL Conversion subgraph "Intermediate Bus & Point-of-Load" DC_OUT --> IBC["Intermediate Bus Converter
48V to 12V/5V"] subgraph "IBC MOSFET Array" Q_IBC1["VBGP1252N
250V/100A TO-247"] Q_IBC2["VBGP1252N
250V/100A TO-247"] Q_IBC3["VBGP1252N
250V/100A TO-247"] Q_IBC4["VBGP1252N
250V/100A TO-247"] end IBC --> Q_IBC1 IBC --> Q_IBC2 IBC --> Q_IBC3 IBC --> Q_IBC4 Q_IBC1 --> POL["Multiphase Buck Converters"] Q_IBC2 --> POL Q_IBC3 --> POL Q_IBC4 --> POL POL --> CPU_VRM["CPU/GPU VRM"] POL --> MEM_VRM["Memory VRM"] POL --> STORAGE_PWR["Storage Power"] end %% Control & Management Section subgraph "Digital Control & Management" MCU["Main Controller
Digital PWM Controller"] --> PFC_DRV["PFC Gate Driver"] MCU --> LLC_DRV["LLC Gate Driver"] MCU --> SR_CTRL["Synchronous Rectification Controller"] MCU --> IBC_CTRL["IBC Controller"] MCU --> BMC["Baseboard Management Controller
BMC"] BMC --> PMBUS["PMBus Interface"] BMC --> I2C_SENSORS["I2C Temperature/Current Sensors"] BMC --> FAN_CTRL["Fan Speed Control"] BMC --> ALERT["Fault Alert System"] end %% Protection & Monitoring subgraph "Protection & Monitoring Circuits" subgraph "Protection Network" RCD_SNUBBER["RCD Snubber
PFC Stage"] RC_SNUBBER["RC Absorption
LLC Stage"] TVS_ARRAY["TVS Protection
Gate Drivers"] OCP_CIRCUIT["Over-Current Protection"] OTP_CIRCUIT["Over-Temperature Protection"] OVP_CIRCUIT["Over-Voltage Protection"] end OCP_CIRCUIT --> MCU OTP_CIRCUIT --> MCU OVP_CIRCUIT --> MCU CURRENT_SENSE["High-Precision Current Sensing"] --> MCU VOLTAGE_SENSE["Voltage Monitoring"] --> MCU TEMP_SENSORS["NTC Thermistors"] --> MCU end %% Thermal Management subgraph "Three-Level Thermal Management" COOLING_LEVEL1["Level 1: Primary Heatsink
Forced Air Cooling"] --> Q_PFC1 COOLING_LEVEL1 --> Q_LLC1 COOLING_LEVEL1 --> Q_IBC1 COOLING_LEVEL2["Level 2: Secondary Heatsink
Forced Air Cooling"] --> Q_SR1 COOLING_LEVEL2 --> Q_SR2 COOLING_LEVEL3["Level 3: PCB Thermal Design
Natural Convection"] --> MCU COOLING_LEVEL3 --> BMC FAN_CTRL --> COOLING_FANS["High-Performance Fans"] end %% Power Sequencing & Redundancy subgraph "Power Sequencing & N+1 Redundancy" PWR_SEQ["Power Sequencing Controller"] --> PFC_STAGE PWR_SEQ --> LLC_STAGE PWR_SEQ --> IBC_STAGE REDUNDANT_PSU["Redundant PSU Module"] --> ORING_MOSFETS["OR-ing MOSFETs"] ORING_MOSFETS --> LOAD_BUS["Load Bus"] LOAD_BUS --> SERVER_LOAD["Dual-Socket Server
CPU, Memory, PCIe"] end %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_IBC1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the era of cloud computing and dense data center deployment, the power supply unit (PSU) for dual-socket virtualization servers acts as the critical "heart" of computational infrastructure. Its performance directly determines server availability, operational cost (via efficiency), and rack-level power density. High-efficiency, high-power-density server PSUs, typically employing advanced topologies like totem-pole PFC and LLC resonant conversion, face stringent demands for power rating, switching frequency, thermal performance, and lifecycle reliability. The selection of power MOSFETs is pivotal in achieving these goals. This article, targeting the demanding application of next-generation server PSUs, conducts an in-depth analysis of MOSFET selection considerations for key power stages, providing an optimized device recommendation scheme.
Detailed MOSFET Selection Analysis
1. VBP18R47S (N-MOS, 800V, 47A, TO-247)
Role: Main switch for high-efficiency totem-pole PFC or primary-side bridge in high-power LLC resonant converters (e.g., for 2kW+ Platinum/Titanium PSUs).
Technical Deep Dive:
Voltage Stress & Efficiency: In a 230VAC or wide-range input (85-265VAC) PFC stage, the DC bus can reach ~400V. The 800V rating provides ample margin for voltage spikes and ensures robustness. Utilizing SJ_Multi-EPI technology, it achieves an excellent balance between breakdown voltage and specific on-resistance (Rds(on) as low as 90mΩ @10V). This directly reduces conduction losses in the critical PFC stage, contributing to higher system efficiency under heavy loads, which is paramount for data center energy savings.
Power Density & Topology Suitability: Its high continuous current rating (47A) makes it suitable for high-power single-phase or interleaved PFC designs. The low Rds(on) and TO-247 package facilitate effective heat dissipation when mounted on a shared heatsink, supporting the pursuit of high wattage per cubic inch in redundant PSU form factors.
2. VBGM1102 (N-MOS, 100V, 180A, TO-220)
Role: Synchronous rectifier (SR) or secondary-side low-voltage, high-current switch in isolated DC-DC stages (e.g., 12V/48V output LLC converter).
Extended Application Analysis:
Ultimate Efficiency Core for Output Stage: The secondary side of a server PSU requires extremely low-loss switching to deliver high output currents (often hundreds of Amps). The VBGM1102, with its super-low Rds(on) of 2.4mΩ @10V and massive 180A current capability, is engineered for this task. Its SGT (Shielded Gate Trench) technology minimizes conduction losses, which is the dominant loss component in SRs.
Power Density Enabler: While in a TO-220 package, its exceptional current handling allows for fewer parallel devices to achieve the required output current, simplifying PCB layout and gate drive. This contributes to a more compact secondary-side design. Its low gate charge also supports higher switching frequencies, enabling the use of smaller magnetic components.
Thermal Management: Despite the high current, the very low Rds(on) keeps junction temperatures manageable. Proper mounting on a thermally coupled heatsink or cold plate is essential to leverage its full potential and ensure long-term reliability under server workloads.
3. VBGP1252N (N-MOS, 250V, 100A, TO-247)
Role: Main switch for high-current intermediate bus converters (IBC) or post-regulator stages (e.g., 48V to 12V/5V non-isolated point-of-load conversion).
Precision Power Delivery & Scalability:
High-Current Intermediate Bus Handling: As server racks adopt 48V power distribution, efficient step-down conversion is critical. The 250V rating of the VBGP1252N provides significant overhead for 48V bus applications. Its outstanding combination of 100A continuous current and 16mΩ Rds(on) (SGT technology) makes it ideal for high-phase-count multiphase buck converters, minimizing losses in this power-dense conversion stage.
Dynamic Response & Power Density: The low on-resistance and high current capability allow for high-frequency operation, improving the transient response of the voltage regulator module (VRM) feeding the server CPUs/GPUs—a key requirement for virtualization workloads. This performance supports higher power density at the board level.
Scalability for Redundancy: The robust TO-247 package and high power handling facilitate designs where multiple converter modules operate in parallel for N+1 redundancy, a common feature in high-availability server PSUs.
System-Level Design and Application Recommendations
Drive Circuit Design Key Points:
High-Voltage Switch Drive (VBP18R47S): Requires a high-performance gate driver capable of fast switching to minimize transition losses in PFC. Attention must be paid to managing the Miller plateau effect with proper gate resistance and, if needed, active Miller clamping.
High-Current Synchronous Rectifier Drive (VBGM1102): Demands a dedicated SR controller or driver with strong sink/source capability to ensure fast and precise turn-on/off, preventing cross-conduction and body diode conduction losses. Layout must minimize common source inductance.
Intermediate Bus Switch Drive (VBGP1252N): A multi-phase PWM controller with integrated high-current drivers is typically used. Tight layout of the power stage is crucial to minimize parasitic inductance and ensure clean switching, which is vital for stable operation under fast load transients.
Thermal Management and EMC Design:
Tiered Cooling Strategy: VBP18R47S and VBGP1252N in TO-247 packages should be mounted on a primary heatsink, often with forced air cooling. VBGM1102 (TO-220) may be placed on a separate or extended heatsink. Thermal interface material quality is critical.
EMI Suppression: Employ snubber networks across the drains of PFC switches (VBP18R47S) to dampen high-frequency ringing. Use high-frequency decoupling capacitors very close to the drain and source of VBGM1102 and VBGP1252N. A well-designed planar or laminated busbar for high-current paths is recommended to reduce loop area and radiated noise.
Reliability Enhancement Measures:
Adequate Derating: Operational voltage for VBP18R47S should not exceed 70-80% of 800V. Junction temperatures for all devices, especially the high-current VBGM1102 and VBGP1252N, must be monitored/derated to ensure a significant safety margin under maximum ambient temperature and workload.
Protection Circuits: Implement comprehensive over-current protection (OCP) and over-temperature protection (OTP) for each power stage, with fault signals feeding back to the system management controller (BMC) for intelligent response.
Enhanced Robustness: Utilize TVS diodes on gate pins for ESD and voltage spike protection. Maintain proper creepage and clearance distances to meet safety standards for IT equipment.
Conclusion
In the design of high-efficiency, high-density power supplies for mission-critical dual-socket virtualization servers, strategic MOSFET selection is fundamental. The three-tier MOSFET scheme recommended here embodies the design philosophy of maximizing efficiency, power density, and reliability.
Core value is reflected in:
Full-Link Efficiency Optimization: From high-efficiency AC-DC conversion in the PFC stage (VBP18R47S), through low-loss secondary-side rectification (VBGM1102), to efficient intermediate bus and point-of-load regulation (VBGP1252N), this selection creates an optimized, low-loss power delivery path from grid to processor.
High Power Density Support: The combination of high current ratings, low Rds(on), and packages suitable for effective cooling allows for a more compact PSU design, enabling higher compute density per rack unit.
Reliability for 24/7 Operation: The selected devices, with their voltage margins and robust technologies (SJ_Multi-EPI, SGT), when coupled with sound thermal and protection design, ensure the PSU can withstand continuous heavy workloads and transient demands, maximizing server uptime.
Future Trends:
As server power demands escalate with next-generation CPUs/GPUs and rack-scale power approaches 100kW+, power device selection will trend towards:
Wider adoption of SiC MOSFETs (like 650V/1200V) in the PFC and primary stages for even higher frequency and efficiency.
Integration of DrMOS or Smart Power Stages that combine MOSFETs, drivers, and protection for the POL stages, simplifying design and improving monitoring.
Exploration of GaN HEMTs in critical high-frequency paths (e.g., auxiliary power supplies, very high-frequency LLC) to push power density boundaries further.
This recommended scheme provides a robust power device foundation for high-performance dual-socket server PSUs. Engineers can refine the selection based on specific output power targets (e.g., 1600W, 2400W), efficiency certifications, and thermal management strategies to build the reliable power backbone essential for modern virtualized data centers.

Detailed Topology Diagrams

Totem-Pole PFC Stage Topology Detail

graph LR subgraph "Totem-Pole Bridgeless PFC Topology" AC_IN["AC Input"] --> L1["PFC Inductor"] L1 --> NODE1["Switching Node 1"] NODE1 --> Q1["VBP18R47S
High-Side MOSFET"] Q1 --> HV_BUS["400VDC Bus"] NODE1 --> Q2["VBP18R47S
Low-Side MOSFET"] Q2 --> GND1 AC_IN --> L2["PFC Inductor"] L2 --> NODE2["Switching Node 2"] NODE2 --> Q3["VBP18R47S
High-Side MOSFET"] Q3 --> HV_BUS NODE2 --> Q4["VBP18R47S
Low-Side MOSFET"] Q4 --> GND2 end subgraph "Control & Drive Circuit" CTRL["PFC Controller"] --> DRIVER["High-Speed Gate Driver"] DRIVER --> Q1_GATE["Q1 Gate"] DRIVER --> Q2_GATE["Q2 Gate"] DRIVER --> Q3_GATE["Q3 Gate"] DRIVER --> Q4_GATE["Q4 Gate"] HV_BUS --> VOLTAGE_FB["Voltage Feedback"] AC_IN --> CURRENT_FB["Current Feedback"] VOLTAGE_FB --> CTRL CURRENT_FB --> CTRL end subgraph "Protection Circuits" SNUBBER1["RCD Snubber"] --> Q1 SNUBBER2["RCD Snubber"] --> Q3 TVS1["TVS Protection"] --> DRIVER TVS2["TVS Protection"] --> CTRL end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q2 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Synchronous Rectification & IBC Topology Detail

graph LR subgraph "LLC Secondary Synchronous Rectification" TRANS_SEC["Transformer Secondary"] --> SR_NODE["Center-Tap Node"] SR_NODE --> SR_Q1["VBGM1102
Synchronous Rectifier"] SR_NODE --> SR_Q2["VBGM1102
Synchronous Rectifier"] SR_Q1 --> OUT_FILTER["LC Output Filter"] SR_Q2 --> OUT_FILTER OUT_FILTER --> OUTPUT["12V/48V Output"] SR_CTRL["SR Controller"] --> SR_DRV["High-Current Gate Driver"] SR_DRV --> SR_Q1 SR_DRV --> SR_Q2 end subgraph "Intermediate Bus Converter (48V to 12V)" INPUT_48V["48V Input"] --> BUCK_CONV["Multiphase Buck Converter"] subgraph "Buck Converter MOSFETs" BUCK_HIGH["VBGP1252N
High-Side MOSFET"] BUCK_LOW["VBGP1252N
Low-Side MOSFET"] end BUCK_CONV --> BUCK_HIGH BUCK_CONV --> BUCK_LOW BUCK_HIGH --> INDUCTOR["Buck Inductor"] INDUCTOR --> OUTPUT_CAP["Output Capacitors"] OUTPUT_CAP --> OUTPUT_12V["12V Output"] BUCK_LOW --> GND_BUCK BUCK_CTRL["Multiphase Controller"] --> BUCK_DRV["Driver"] BUCK_DRV --> BUCK_HIGH BUCK_DRV --> BUCK_LOW end subgraph "Point-of-Load VRM" OUTPUT_12V --> VRM["Multiphase CPU VRM"] VRM --> CPU_PWR["CPU Power Rails"] OUTPUT_12V --> MEM_VRM["Memory VRM"] MEM_VRM --> DIMM_PWR["DIMM Power"] OUTPUT_12V --> AUX_VRM["Auxiliary VRM"] AUX_VRM --> PCIE_PWR["PCIe Power"] end style SR_Q1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style BUCK_HIGH fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Thermal Management & Protection Topology Detail

graph LR subgraph "Three-Level Cooling Architecture" LEVEL1["Level 1: Primary Heatsink"] --> HS1["Aluminum Extrusion
Forced Air Cooling"] HS1 --> MOSFETS_PRI["Primary MOSFETs
VBP18R47S"] HS1 --> MOSFETS_IBC["IBC MOSFETs
VBGP1252N"] LEVEL2["Level 2: Secondary Heatsink"] --> HS2["Copper Base Plate
Forced Air Cooling"] HS2 --> MOSFETS_SR["SR MOSFETs
VBGM1102"] LEVEL3["Level 3: PCB Thermal"] --> PCB_DESIGN["Thermal Vias & Copper Pour"] PCB_DESIGN --> ICS["Control ICs & Drivers"] PCB_DESIGN --> SENSORS["Temperature Sensors"] TEMP_MONITOR["Temperature Monitor"] --> FAN_CTRL["Fan Controller"] FAN_CTRL --> FAN1["Primary Fan"] FAN_CTRL --> FAN2["Secondary Fan"] FAN_CTRL --> FAN3["Exhaust Fan"] end subgraph "Comprehensive Protection Network" subgraph "Electrical Protection" OVP["Over-Voltage Protection"] --> COMP1["Comparator"] OCP["Over-Current Protection"] --> COMP2["Comparator"] OTP["Over-Temperature Protection"] --> COMP3["Comparator"] UVP["Under-Voltage Protection"] --> COMP4["Comparator"] end subgraph "Fault Management" COMP1 --> FAULT_LOGIC["Fault Logic Controller"] COMP2 --> FAULT_LOGIC COMP3 --> FAULT_LOGIC COMP4 --> FAULT_LOGIC FAULT_LOGIC --> SHUTDOWN["Shutdown Signal"] FAULT_LOGIC --> ALERT["Alert to BMC"] SHUTDOWN --> GATE_DRIVERS["All Gate Drivers"] ALERT --> BMC_INTERFACE["BMC Communication"] end subgraph "Snubber & Clamping" RCD1["RCD Snubber Network"] --> PFC_MOSFETS RC1["RC Absorption Network"] --> LLC_MOSFETS TVS_ARRAY["TVS Diode Array"] --> GATE_PINS["All Gate Pins"] SCHOTTKY["Schottky Diodes"] --> SR_MOSFETS["SR MOSFETs"] end style MOSFETS_PRI fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style MOSFETS_SR fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style MOSFETS_IBC fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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