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Power MOSFET Selection Solution for Distributed Block Storage Systems: Building a High-Efficiency and Highly Reliable Power Foundation for Data Centers
Distributed Block Storage System Power MOSFET Topology Diagram

Distributed Block Storage System Power Architecture Overall Topology

graph LR %% Power Input Section subgraph "AC-DC Power Supply Unit (Server PSU)" AC_IN["AC Input (85-265VAC)"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> RECTIFIER["Bridge Rectifier"] RECTIFIER --> PFC_STAGE["PFC Boost Stage"] PFC_STAGE --> HV_BUS["High Voltage DC Bus (380-400V)"] HV_BUS --> LLC_CONVERTER["LLC Resonant Converter"] LLC_CONVERTER --> PSU_OUTPUT["12V/48V Main Output"] subgraph "PFC Stage MOSFET" Q_PFC1["VBP18R20SFD
800V/20A
TO-247"] Q_PFC2["VBP18R20SFD
800V/20A
TO-247"] end subgraph "LLC Stage MOSFET" Q_LLC1["VBP18R20SFD
800V/20A
TO-247"] Q_LLC2["VBP18R20SFD
800V/20A
TO-247"] end PFC_DRIVER["PFC Controller/Driver"] --> Q_PFC1 PFC_DRIVER --> Q_PFC2 LLC_DRIVER["LLC Controller/Driver"] --> Q_LLC1 LLC_DRIVER --> Q_LLC2 end %% Power Distribution Section PSU_OUTPUT --> DIST_BUS["Distribution Bus (12V/48V)"] subgraph "Server Node Power Distribution" DIST_BUS --> BACKPLANE_POWER["SSD Backplane Power"] DIST_BUS --> POL_CONVERTERS["Point-of-Load Converters"] DIST_BUS --> COOLING_SYSTEM["Cooling System"] subgraph "High-Current POL Converters" POL_12V_5V["12V to 5V Buck"] POL_5V_3V3["5V to 3.3V Buck"] POL_5V_1V8["5V to 1.8V Buck"] subgraph "Synchronous MOSFETs" Q_SYNC1["VBE1202
20V/120A
TO-252"] Q_SYNC2["VBE1202
20V/120A
TO-252"] Q_SYNC3["VBE1202
20V/120A
TO-252"] Q_SYNC4["VBE1202
20V/120A
TO-252"] end POL_12V_5V --> Q_SYNC1 POL_5V_3V3 --> Q_SYNC2 POL_5V_1V8 --> Q_SYNC3 BACKPLANE_POWER --> Q_SYNC4 end subgraph "SSD Array Power Management" SSD_POWER["SSD Power Switch"] --> SSD_ARRAY["SSD Array"] HOT_SWAP_CTRL["Hot-Swap Controller"] --> SSD_POWER end end %% Cooling & Auxiliary Management subgraph "Cooling & System Management" subgraph "Multi-Zone Fan Control" FAN_CONTROLLER["Fan Controller"] --> ZONE1_DRIVE["Zone 1 Drive"] FAN_CONTROLLER --> ZONE2_DRIVE["Zone 2 Drive"] FAN_CONTROLLER --> ZONE3_DRIVE["Zone 3 Drive"] subgraph "Fan Drive MOSFETs" Q_FAN1["VBA3638 (Dual-N)
60V/7A per Ch
SOP8"] Q_FAN2["VBA3638 (Dual-N)
60V/7A per Ch
SOP8"] Q_FAN3["VBA3638 (Dual-N)
60V/7A per Ch
SOP8"] end ZONE1_DRIVE --> Q_FAN1 ZONE2_DRIVE --> Q_FAN2 ZONE3_DRIVE --> Q_FAN3 Q_FAN1 --> FANS1["Chassis Fans"] Q_FAN2 --> FANS2["CPU/GPU Fans"] Q_FAN3 --> FANS3["PSU Fans"] end subgraph "Redundant Power OR-ing" PSU_A["PSU A Output"] --> OR_ING_NODE PSU_B["PSU B Output"] --> OR_ING_NODE OR_ING_NODE --> DIST_BUS subgraph "OR-ing MOSFETs" Q_OR1["VBA3638
60V/7A
SOP8"] Q_OR2["VBA3638
60V/7A
SOP8"] end PSU_A --> Q_OR1 PSU_B --> Q_OR2 end end %% Monitoring & Protection subgraph "System Monitoring & Protection" TEMP_SENSORS["Temperature Sensors"] --> MCU["System Management MCU"] CURRENT_SENSE["Current Sensors"] --> MCU VOLTAGE_MON["Voltage Monitors"] --> MCU MCU --> OCP_OTP["OCP/OTP Logic"] OCP_OTP --> SHUTDOWN_SIGNALS["Shutdown Control"] SHUTDOWN_SIGNALS --> Q_PFC1 SHUTDOWN_SIGNALS --> Q_LLC1 SHUTDOWN_SIGNALS --> Q_SYNC1 MCU --> FAN_PWM["Fan PWM Control"] FAN_PWM --> FAN_CONTROLLER end %% Thermal Management subgraph "Hierarchical Thermal Management" LEVEL1["Level 1: Heatsink Cooling"] --> Q_PFC1 LEVEL1 --> Q_LLC1 LEVEL2["Level 2: PCB Copper Pour"] --> Q_SYNC1 LEVEL2 --> Q_SYNC2 LEVEL3["Level 3: Airflow Cooling"] --> Q_FAN1 LEVEL3 --> Q_OR1 end %% Communication & Control MCU --> I2C_BUS["I2C/PMBus"] I2C_BUS --> PSU_MON["PSU Monitoring"] I2C_BUS --> TEMP_SENSORS MCU --> FAN_CONTROLLER %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SYNC1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_FAN1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the explosive growth of data and the evolution of cloud computing, distributed block storage systems have become the core infrastructure for data centers. Their power delivery and management subsystems, serving as the "heart and energy arteries," must provide highly efficient, reliable, and precisely controlled power conversion for critical loads such as SSD arrays, server fans, and DC-DC conversion modules. The selection of power MOSFETs directly determines the system's power efficiency, power density, thermal performance, and ultimately, operational stability and total cost of ownership (TCO). Addressing the stringent requirements of 24/7 data center operation for efficiency, reliability, scalability, and thermal management, this article reconstructs the power MOSFET selection logic based on scenario adaptation, providing an optimized, ready-to-implement solution.
I. Core Selection Principles and Scenario Adaptation Logic
Core Selection Principles
Voltage Robustness & Margin: For bus voltages ranging from 12V (for chipsets) to 48V/54V (emerging server rack architectures) and high-voltage AC-DC inputs (e.g., PFC stage), MOSFET voltage ratings must have sufficient margin (>30-50%) to withstand switching spikes and grid transients.
Ultra-Low Loss for High Efficiency: Prioritize devices with the lowest possible on-state resistance (Rds(on)) and optimized gate charge (Qg) to minimize conduction and switching losses, which is critical for reducing energy consumption and heat generation in high-density servers.
Package for Power Density & Thermal Performance: Select packages (e.g., TO-252, TO-263, TO-247, SOP8) based on power level, thermal dissipation requirements, and board space constraints to achieve optimal power density and reliable thermal management.
Reliability & Longevity: Devices must be rated for continuous 24/7 operation under elevated ambient temperatures, with excellent thermal stability and ruggedness to ensure mean time between failures (MTBF) targets are met.
Scenario Adaptation Logic
Based on the key power domains within a storage server/node, MOSFET applications are divided into three primary scenarios: High-Current DC-DC Conversion & SSD Power Delivery, High-Voltage AC-DC Input & PFC Stage, and System Cooling & Auxiliary Power Management. Device parameters are matched to the specific electrical and thermal demands of each domain.
II. MOSFET Selection Solutions by Scenario
Scenario 1: High-Current DC-DC Conversion & SSD Backplane Power Delivery (12V/5V/3.3V Rails)
Recommended Model: VBE1202 (Single-N, 20V, 120A, TO-252)
Key Parameter Advantages: Extremely low Rds(on) of 2.5mΩ at 4.5V Vgs and 3.5mΩ at 2.5V Vgs. Very low gate threshold voltage (0.5-1.5V) compatible with modern controller drivers. High continuous current rating of 120A.
Scenario Adaptation Value: The ultra-low Rds(on) minimizes conduction loss in synchronous buck converters for CPU, memory, or most critically, in point-of-load (POL) converters and power switches feeding SSD arrays. This ensures maximum efficiency for high-current, low-voltage rails, reduces thermal stress on SSDs, and supports hot-swap capabilities. The TO-252 package offers a good balance of current handling and footprint.
Applicable Scenarios: Synchronous rectification in high-current buck converters (e.g., 12V to 5V/3.3V/1.8V); SSD backplane power switching and sequencing.
Scenario 2: High-Voltage AC-DC Input & Power Factor Correction (PFC) Stage
Recommended Model: VBP18R20SFD (Single-N, 800V, 20A, TO-247)
Key Parameter Advantages: High voltage rating of 800V suitable for universal input (85-265VAC) PFC and bridge circuits. Low Rds(on) of 205mΩ at 10V Vgs for its voltage class. Utilizes Super Junction Multi-EPI technology for optimal switching performance and low conduction loss.
Scenario Adaptation Value: Enables the design of high-efficiency (>95% Platinum/Titanium level) server power supply units (PSUs). The low Rds(on) and advanced SJ technology reduce losses in the critical PFC stage, improving overall system efficiency and power quality. The TO-247 package provides excellent thermal dissipation for this high-power stage.
Applicable Scenarios: Boost PFC circuits, main switches in LLC resonant converters within high-efficiency server PSUs.
Scenario 3: System Cooling & Auxiliary Power Management (Fan Drive, OR-ing)
Recommended Model: VBA3638 (Dual-N+N, 60V, 7A per Ch, SOP8)
Key Parameter Advantages: Dual N-channel MOSFETs in a compact SOP8 package. Low and matched Rds(on) of 28mΩ at 10V Vgs per channel. 60V rating provides good margin for 12V/24V/48V fan buses.
Scenario Adaptation Value: The dual independent MOSFETs are ideal for driving multiple fan zones (e.g., chassis fans, CPU fan) with PWM control for precise thermal management and acoustics. They can also be used for OR-ing diodes in redundant power supply paths or for general-purpose load switching. The integrated dual design saves PCB space and simplifies layout.
Applicable Scenarios: Multi-zone BLDC/PWM fan drive circuits; redundant power path OR-ing; general-purpose load switching for peripherals.
III. System-Level Design Implementation Points
Drive Circuit Design
VBE1202: Requires a dedicated synchronous buck controller or driver IC capable of sourcing/sinking high peak current. Optimize gate drive loop layout to prevent oscillation.
VBP18R20SFD: Pair with a dedicated PFC or half-bridge driver IC. Use isolated or level-shifted gate drive as per topology. Attention to dv/dt and di/dt management is crucial.
VBA3638: Can be driven directly by a fan controller IC or MCU with sufficient drive strength. Include gate resistors for slew rate control.
Thermal Management Design
Hierarchical Strategy: VBP18R20SFD (TO-247) likely requires a heatsink attached to the PSU chassis. VBE1202 (TO-252) benefits from significant PCB copper pour area. VBA3638 (SOP8) relies on PCB copper for heat dissipation.
Derating Practice: Operate MOSFETs at ≤70-80% of their rated current under maximum ambient temperature (e.g., 50°C+ inside server). Ensure junction temperature remains with a safe margin below Tj(max).
EMC and Reliability Assurance
Switching Noise Mitigation: Use snubber circuits or RC buffers for VBP18R20SFD in high-voltage switching nodes. Place high-frequency decoupling capacitors close to the drains of VBE1202.
Protection Schemes: Implement over-current protection (OCP) and over-temperature protection (OTP) at the system level. Use TVS diodes on gate pins and power input lines for surge/ESD protection. For fan drives (VBA3638), consider back-EMF clamping.
IV. Core Value of the Solution and Optimization Suggestions
The scenario-adapted power MOSFET selection solution for distributed block storage systems achieves comprehensive coverage from high-voltage AC-DC input to low-voltage point-of-load delivery and critical cooling management. Its core value is reflected in three key aspects:
1. Total System Efficiency Optimization: By selecting optimal MOSFETs for each power domain—ultra-low Rds(on) devices like VBE1202 for high-current rails, advanced SJ MOSFETs like VBP18R20SFD for efficient AC-DC conversion—system-wide losses are minimized. This contributes directly to lower Power Usage Effectiveness (PUE), reduced electricity costs, and less cooling overhead for the data center.
2. Balancing High Reliability with Serviceability: The chosen devices offer robust electrical ratings and are packaged for effective thermal management, supporting the demanding 24/7 operational profile. The use of standard, widely available packages (TO-247, TO-252, SOP8) also facilitates maintenance and potential field replacement, balancing reliability with serviceability.
3. Optimizing Power Density and TCO: The combination of high-performance devices in space-efficient packages allows for compact power supply and motherboard designs, increasing storage density per rack unit. By improving efficiency, reliability, and density, this solution positively impacts the Total Cost of Ownership (TCO) of the storage infrastructure.
In the design of power subsystems for distributed block storage systems, judicious MOSFET selection is fundamental to achieving high efficiency, reliability, and density. This scenario-based solution, by aligning device characteristics with specific load requirements and incorporating robust system-level design practices, provides a actionable technical roadmap. As data centers evolve towards higher voltages (e.g., 48V), higher efficiency targets, and increased AI-driven power management, future MOSFET selection will further emphasize integration, advanced packaging (e.g., modules), and the potential adoption of Wide Bandgap (WBG) devices like SiC for the highest power stages, laying a future-proof hardware foundation for the next generation of sustainable, high-performance data storage.

Detailed Topology Diagrams

High-Voltage AC-DC & PFC Stage Detail

graph LR subgraph "Three-Phase PFC Stage" AC_IN["AC Input (3-Phase)"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> BRIDGE["3-Phase Rectifier"] BRIDGE --> PFC_INDUCTOR["PFC Inductor"] PFC_INDUCTOR --> PFC_SW_NODE subgraph "PFC MOSFET Array" Q_PFC_H1["VBP18R20SFD
800V/20A"] Q_PFC_H2["VBP18R20SFD
800V/20A"] Q_PFC_H3["VBP18R20SFD
800V/20A"] Q_PFC_L1["VBP18R20SFD
800V/20A"] Q_PFC_L2["VBP18R20SFD
800V/20A"] Q_PFC_L3["VBP18R20SFD
800V/20A"] end PFC_SW_NODE --> Q_PFC_H1 PFC_SW_NODE --> Q_PFC_H2 PFC_SW_NODE --> Q_PFC_H3 Q_PFC_H1 --> HV_BUS["HV Bus (400VDC)"] Q_PFC_H2 --> HV_BUS Q_PFC_H3 --> HV_BUS PFC_DRIVER["PFC Controller"] --> GATE_DRIVER["Gate Driver"] GATE_DRIVER --> Q_PFC_H1 GATE_DRIVER --> Q_PFC_L1 end subgraph "LLC Resonant Converter" HV_BUS --> LLC_RESONANT["LLC Resonant Tank"] LLC_RESONANT --> TRANSFORMER["HF Transformer"] TRANSFORMER --> LLC_SW_NODE subgraph "LLC Half-Bridge MOSFETs" Q_LLC_H["VBP18R20SFD
800V/20A"] Q_LLC_L["VBP18R20SFD
800V/20A"] end LLC_SW_NODE --> Q_LLC_H Q_LLC_H --> HV_BUS Q_LLC_L --> GND LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["Gate Driver"] LLC_DRIVER --> Q_LLC_H LLC_DRIVER --> Q_LLC_L TRANSFORMER --> SECONDARY["Secondary Side"] SECONDARY --> OUTPUT_RECT["Synchronous Rectification"] OUTPUT_RECT --> OUTPUT_FILTER["Output Filter"] OUTPUT_FILTER --> DC_OUT["12V/48V Output"] end subgraph "Protection Circuits" SNUBBER["RCD Snubber"] --> Q_PFC_H1 RC_ABSORB["RC Absorption"] --> Q_LLC_H TVS_ARRAY["TVS Protection"] --> GATE_DRIVER TVS_ARRAY --> LLC_DRIVER end style Q_PFC_H1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LLC_H fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

High-Current POL & SSD Power Management Detail

graph LR subgraph "Synchronous Buck Converter (12V to 5V/3.3V/1.8V)" VIN["12V Input"] --> INPUT_CAP["Input Capacitors"] INPUT_CAP --> BUCK_INDUCTOR["Buck Inductor"] BUCK_INDUCTOR --> SW_NODE["Switching Node"] subgraph "Control & High-Side MOSFET" BUCK_CONTROLLER["Buck Controller"] --> GATE_DRV["Gate Driver"] GATE_DRV --> Q_HS["High-Side MOSFET"] end subgraph "Low-Side Synchronous MOSFETs" Q_LS1["VBE1202
20V/120A"] Q_LS2["VBE1202
20V/120A"] Q_LS3["VBE1202
20V/120A"] end SW_NODE --> Q_HS Q_HS --> VIN SW_NODE --> Q_LS1 SW_NODE --> Q_LS2 SW_NODE --> Q_LS3 Q_LS1 --> GND Q_LS2 --> GND Q_LS3 --> GND SW_NODE --> OUTPUT_FILTER["LC Output Filter"] OUTPUT_FILTER --> VOUT["5V/3.3V/1.8V Output"] VOUT --> LOAD["CPU/Memory/SSD"] VOUT --> FB["Voltage Feedback"] FB --> BUCK_CONTROLLER end subgraph "SSD Backplane Power Switching" BACKPLANE_IN["12V Backplane"] --> HOT_SWAP["Hot-Swap Controller"] HOT_SWAP --> Q_SSD_SW["VBE1202
20V/120A"] Q_SSD_SW --> SSD_POWER["SSD Power Rail"] SSD_POWER --> SSD_SLOT1["SSD Slot 1"] SSD_POWER --> SSD_SLOT2["SSD Slot 2"] SSD_POWER --> SSD_SLOT3["SSD Slot 3"] SSD_POWER --> SSD_SLOT4["SSD Slot 4"] CURRENT_SENSE["Current Sense"] --> HOT_SWAP TEMP_SENSE["Temperature Sense"] --> HOT_SWAP end subgraph "Power Sequencing Logic" SEQ_CONTROLLER["Sequencing Controller"] --> ENABLE_12V["Enable 12V Rail"] SEQ_CONTROLLER --> ENABLE_5V["Enable 5V Rail"] SEQ_CONTROLLER --> ENABLE_3V3["Enable 3.3V Rail"] SEQ_CONTROLLER --> ENABLE_1V8["Enable 1.8V Rail"] ENABLE_12V --> Q_HS ENABLE_5V --> Q_LS1 ENABLE_3V3 --> Q_LS2 ENABLE_1V8 --> Q_LS3 end style Q_LS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_SSD_SW fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Cooling & Auxiliary Power Management Detail

graph LR subgraph "Multi-Zone PWM Fan Control" FAN_CONTROLLER["Fan Controller IC"] --> ZONE1_PWM["Zone 1 PWM"] FAN_CONTROLLER --> ZONE2_PWM["Zone 2 PWM"] FAN_CONTROLLER --> ZONE3_PWM["Zone 3 PWM"] subgraph "Dual MOSFET Fan Drivers" Q_FAN_ZONE1["VBA3638
Dual N-Channel"] Q_FAN_ZONE2["VBA3638
Dual N-Channel"] Q_FAN_ZONE3["VBA3638
Dual N-Channel"] end ZONE1_PWM --> Q_FAN_ZONE1 ZONE2_PWM --> Q_FAN_ZONE2 ZONE3_PWM --> Q_FAN_ZONE3 VCC_12V["12V Supply"] --> Q_FAN_ZONE1 VCC_12V --> Q_FAN_ZONE2 VCC_12V --> Q_FAN_ZONE3 Q_FAN_ZONE1 --> FAN1_1["Fan 1-1"] Q_FAN_ZONE1 --> FAN1_2["Fan 1-2"] Q_FAN_ZONE2 --> FAN2_1["Fan 2-1"] Q_FAN_ZONE2 --> FAN2_2["Fan 2-2"] Q_FAN_ZONE3 --> FAN3_1["Fan 3-1"] Q_FAN_ZONE3 --> FAN3_2["Fan 3-2"] FAN1_1 --> GND FAN1_2 --> GND end subgraph "Redundant Power OR-ing Circuit" PSU_A["PSU A (12V)"] --> Q_OR_A["VBA3638
Dual N-Channel"] PSU_B["PSU B (12V)"] --> Q_OR_B["VBA3638
Dual N-Channel"] Q_OR_A --> OR_NODE["OR-ed Output"] Q_OR_B --> OR_NODE OR_NODE --> DISTRIBUTION["Distribution Bus"] OR_CONTROLLER["OR-ing Controller"] --> GATE_A["Gate Control A"] OR_CONTROLLER --> GATE_B["Gate Control B"] GATE_A --> Q_OR_A GATE_B --> Q_OR_B end subgraph "Temperature Monitoring & Control" TEMP_SENSOR1["CPU Temp Sensor"] --> MCU["System MCU"] TEMP_SENSOR2["Ambient Temp Sensor"] --> MCU TEMP_SENSOR3["PSU Temp Sensor"] --> MCU MCU --> PWM_CONTROL["PWM Control Logic"] PWM_CONTROL --> FAN_CONTROLLER MCU --> ALARM_LOGIC["Alarm/Shutdown Logic"] ALARM_LOGIC --> SHUTDOWN["System Shutdown"] end subgraph "Fan Protection Circuits" BACK_EMF["Back-EMF Clamping"] --> Q_FAN_ZONE1 BACK_EMF --> Q_FAN_ZONE2 TVS_FAN["TVS Protection"] --> VCC_12V FUSE["Polyfuse"] --> VCC_12V end style Q_FAN_ZONE1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_OR_A fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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