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High-Efficiency Power MOSFET Selection Solution for Cold Plate Liquid-Cooled IT Container Units: A Guide to Adapting Reliable and Dense Power Delivery Systems
Cold Plate Liquid-Cooled IT Container Power MOSFET Topology

Cold Plate Liquid-Cooled IT Container Power Delivery System Overall Topology

graph LR %% Input & Primary Power Stage subgraph "High-Voltage Input & PFC Stage (Primary Side)" AC_IN["Three-Phase AC Input
or 380VDC"] --> EMI_FILTER["EMI Filter &
Surge Protection"] EMI_FILTER --> PFC_CIRCUIT["Active PFC Circuit"] subgraph "PFC Power MOSFET" Q_PFC["VBL15R30S
500V/30A
Super Junction"] end PFC_CIRCUIT --> Q_PFC Q_PFC --> HV_BUS["High-Voltage DC Bus
~400VDC"] HV_BUS --> ISOLATION["Isolation Stage
(if required)"] end %% Intermediate Bus & Distribution subgraph "Intermediate Bus Converter & Power Distribution" HV_BUS --> IBC["48V Intermediate Bus Converter"] subgraph "IBC Synchronous Rectification" Q_IBC_HIGH["VBGED1401
40V/150A
High Side"] Q_IBC_LOW["VBGED1401
40V/150A
Low Side"] end IBC --> Q_IBC_HIGH Q_IBC_HIGH --> Q_IBC_LOW Q_IBC_LOW --> IBC_OUT["12V/5V Distribution Bus"] IBC_OUT --> PUMP_DRIVER["Liquid Cooling Pump Driver"] PUMP_DRIVER --> COOLING_PUMP["High-Power Pump"] IBC_OUT --> FAN_DRIVER["High-Speed Fan Driver"] FAN_DRIVER --> COOLING_FANS["Cooling Fans Array"] end %% Point-of-Load & Server Power subgraph "CPU/GPU Point-of-Load (PoL) Power" IBC_OUT --> VRM["Multi-Phase Voltage Regulator Module"] subgraph "VRM Synchronous Buck Converter" Q_VRM1["VBQG5222
Dual N+P MOSFET
±20V/±5A"] Q_VRM2["VBQG5222
Dual N+P MOSFET
±20V/±5A"] Q_VRM3["VBQG5222
Dual N+P MOSFET
±20V/±5A"] Q_VRM4["VBQG5222
Dual N+P MOSFET
±20V/±5A"] end VRM --> Q_VRM1 VRM --> Q_VRM2 VRM --> Q_VRM3 VRM --> Q_VRM4 Q_VRM1 --> CPU_POWER["CPU Core Power
0.8-1.5V"] Q_VRM2 --> GPU_POWER["GPU Core Power
0.8-1.5V"] Q_VRM3 --> MEMORY_POWER["Memory Power
1.2V"] Q_VRM4 --> CHIPSET_POWER["Chipset Power
1.0V"] end %% Control & Management System subgraph "Intelligent Control & Monitoring" CONTROLLER["Main System Controller"] --> PFC_CONTROL["PFC Controller"] CONTROLLER --> IBC_CONTROL["IBC Controller"] CONTROLLER --> VRM_CONTROL["Multi-Phase VRM Controller"] CONTROLLER --> TEMP_MONITOR["Temperature Monitoring"] CONTROLLER --> FLOW_CONTROL["Coolant Flow Control"] TEMP_MONITOR --> NTC_SENSORS["NTC Sensors Array"] FLOW_CONTROL --> PUMP_SPEED["Pump Speed PWM"] FLOW_CONTROL --> FAN_SPEED["Fan Speed PWM"] end %% Thermal Management subgraph "Unified Cold Plate Thermal Management" COLD_PLATE["Liquid Cold Plate"] --> MOSFET_INTERFACE["MOSFET Thermal Interface"] COLD_PLATE --> HEAT_EXCHANGER["Liquid-to-Liquid Heat Exchanger"] HEAT_EXCHANGER --> EXTERNAL_COOLING["External Cooling Loop"] MOSFET_INTERFACE --> Q_PFC MOSFET_INTERFACE --> Q_IBC_HIGH MOSFET_INTERFACE --> Q_VRM1 end %% Protection & Reliability subgraph "System Protection & Reliability" OVP["Over-Voltage Protection"] --> Q_PFC OCP["Over-Current Protection"] --> Q_IBC_HIGH OTP["Over-Temperature Protection"] --> ALL_MOSFETS TVS_ARRAY["TVS Surge Protection"] --> AC_IN SNUBBER_CIRCUITS["Snubber Circuits"] --> Q_PFC GATE_PROTECTION["Gate-Source Clamping"] --> Q_VRM1 end %% Style Definitions style Q_PFC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_IBC_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_VRM1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style CONTROLLER fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Driven by the demands of high-density computing and green data centers, cold plate liquid-cooled IT container units have become a critical infrastructure for modern computing. Their power delivery and thermal management systems, serving as the "energy arteries and cooling muscles" of the entire unit, must provide efficient, stable, and precisely controlled power conversion for core loads such as pumps, high-speed fans, and server motherboards (CPUs/GPUs). The selection of power MOSFETs directly determines the system's conversion efficiency, power density, thermal performance, and operational reliability. Addressing the stringent requirements of IT container units for efficiency, reliability, compactness, and 24/7 operation, this article centers on scenario-based adaptation to reconstruct the power MOSFET selection logic, providing an optimized solution ready for direct implementation.
I. Core Selection Principles and Scenario Adaptation Logic
Core Selection Principles
High Voltage & High Reliability: For power architectures involving AC-DC (PFC stage) or high-voltage DC bus (e.g., 380VDC), MOSFETs must have sufficient voltage margin and robustness to handle switching voltage spikes and grid transients.
Ultra-Low Loss is Paramount: Prioritize devices with extremely low on-state resistance (Rds(on)) and optimized gate charge (Qg) to minimize conduction and switching losses, which is critical for achieving high system efficiency and reducing thermal load on the liquid cooling system.
Package for Power Density & Thermal Compatibility: Select packages like TOLL, LFPAK, DFN, or TO-263 based on power level and board space, ensuring excellent thermal performance to interface effectively with cold plates or heatsinks.
Mission-Critical Reliability: Devices must be qualified for continuous 24/7 operation under elevated ambient temperatures, with a focus on thermal stability, avalanche ruggedness, and long-term reliability.
Scenario Adaptation Logic
Based on the power conversion chain within a liquid-cooled IT container, MOSFET applications are divided into three main scenarios: High-Voltage Input/PFC Stage (Primary Side), Intermediate Bus Conversion & Pump Drive (Power Distribution), and CPU/GPU Point-of-Load (PoL) Power (Precision Delivery). Device parameters and characteristics are matched accordingly.
II. MOSFET Selection Solutions by Scenario
Scenario 1: High-Voltage Input / PFC Stage – Primary Side Power Device
Recommended Model: VBL15R30S (Single N-MOS, 500V, 30A, TO-263)
Key Parameter Advantages: Utilizes Super Junction (SJ_Multi-EPI) technology, offering an excellent balance of high voltage rating (500V) and low Rds(on) (140mΩ @10V). A continuous current rating of 30A suits kilowatt-level power factor correction circuits.
Scenario Adaptation Value: The TO-263 package provides robust thermal and power handling capability, easily mounted to a heatsink. Super Junction technology ensures low switching loss at high voltages, critical for achieving high efficiency in the front-end PFC or primary DC-DC stage. Its high voltage margin safeguards against line surges common in data center environments.
Applicable Scenarios: Active PFC circuits, high-voltage DC-DC primary switches in 380VDC or three-phase input power supplies.
Scenario 2: Intermediate Bus Conversion & Pump Drive – Power Distribution Device
Recommended Model: VBGED1401 (Single N-MOS, 40V, 150A, LFPAK56)
Key Parameter Advantages: Features SGT (Shielded Gate Trench) technology, achieving an ultra-low Rds(on) of 0.7mΩ at 10V drive. An extremely high continuous current rating of 150A meets the demands of high-current 48V-to-12V/5V intermediate bus converters (IBCs) or high-power pump motor drives.
Scenario Adaptation Value: The LFPAK56 (Power-SO8) package offers an outstanding combination of very low package parasitic inductance, excellent thermal resistance, and a small footprint. The ultra-low conduction loss minimizes heat generation at high currents, directly boosting the efficiency of the power distribution stage. This is essential for maximizing the overall Power Usage Effectiveness (PUE) of the container unit.
Applicable Scenarios: Synchronous rectification and switch elements in high-current 48V/12V DC-DC converters; drive for high-power liquid cooling pumps.
Scenario 3: CPU/GPU Point-of-Load (PoL) Power – Precision Delivery Device
Recommended Model: VBQG5222 (Dual N+P MOSFET, ±20V, ±5A, DFN6(2x2)-B)
Key Parameter Advantages: Integrates a matched pair of N and P-channel MOSFETs in a ultra-compact DFN package. Features very low gate threshold voltage (Vth ≈ ±0.8V) and low Rds(on) (e.g., 24mΩ/40mΩ @2.5V for N/P), enabling efficient operation from low-voltage drive signals.
Scenario Adaptation Value: The tiny dual configuration is ideal for space-constrained, multi-phase VRM (Voltage Regulator Module) or high-frequency PoL buck converters powering CPUs and GPUs. Low Vth allows for direct drive by advanced PWM controllers, simplifying design. The integrated pair ensures parameter consistency for synchronous rectification, enabling fast switching, precise voltage regulation, and high current density critical for processor power delivery.
Applicable Scenarios: Synchronous buck converter high-side and low-side switches in multi-phase VRMs; load switches for high-performance computing cards.
III. System-Level Design Implementation Points
Drive Circuit Design
VBL15R30S: Requires a dedicated high-voltage gate driver IC with adequate drive current and negative voltage clamp capability to manage Miller plateau and ensure fast, safe switching.
VBGED1401: Pair with a high-current driver IC. PCB layout must minimize power loop inductance. Use a low-impedance gate drive path.
VBQG5222: Can be driven directly by many modern multi-phase PWM controllers. Optimize gate drive traces for symmetry in multi-phase applications.
Thermal Management Design
Unified Cold Plate Strategy: All three selected packages (TO-263, LFPAK56, DFN) feature exposed thermal pads suitable for direct thermal interface with a cold plate or a shared heatsink attached to the cold plate.
Derating for High Ambient: Design for junction temperatures well below the maximum rating, considering the potentially higher local ambient temperature inside the server tray. Utilize the cold plate's capability effectively.
EMC and Reliability Assurance
Switching Node Control: For VBL15R30S and VBGED1401, careful snubber design and RC damping may be necessary to control high di/dt and dv/dt and mitigate high-frequency EMI.
Protection Measures: Implement comprehensive overcurrent, overtemperature, and overvoltage protection at each power stage. Use TVS diodes for surge protection on input lines. Ensure proper gate-source clamping for all MOSFETs.
IV. Core Value of the Solution and Optimization Suggestions
The power MOSFET selection solution for cold plate liquid-cooled IT container units, based on scenario adaptation logic, achieves comprehensive coverage from high-voltage input to ultra-low-voltage PoL delivery. Its core value is mainly reflected in the following three aspects:
Maximizing Energy Efficiency from Grid to Silicon: By selecting optimized devices for each conversion stage—Super Junction for high-voltage efficiency, SGT for ultra-low loss in high-current distribution, and advanced trench for precision PoL—losses are minimized throughout the chain. This contributes directly to a lower PUE, reducing total cost of ownership (TCO) and aligning with sustainability goals.
Enabling High Power Density and Thermal Co-Design: The selected packages (LFPAK56, DFN6) offer superior power density, freeing valuable PCB space for other components. Their excellent thermal characteristics are perfectly suited for direct integration with advanced cold plate designs, enabling tighter thermal budgets and higher compute density per rack unit.
Ensuring Mission-Critical Reliability and Scalability: The chosen devices are engineered for high reliability under continuous operation. The scalable nature of the solution—from single-phase PoL to multi-phase VRMs and parallelable intermediate converters—supports power delivery for a wide range of server and GPU configurations within the container, ensuring design flexibility and long-term operational stability.
In the design of power delivery systems for cold plate liquid-cooled IT container units, power MOSFET selection is a cornerstone for achieving efficiency, density, and unwavering reliability. The scenario-based selection solution proposed in this article, by accurately matching the demands of different power conversion stages and combining it with system-level drive, thermal, and protection design co-optimized for liquid cooling, provides a comprehensive, actionable technical reference. As computing demands push towards higher power and higher density, power device selection will increasingly focus on deep integration with the thermal management system. Future exploration could focus on the application of next-generation wide-bandgap devices (like GaN for ultra-high-frequency PoL) and the development of integrated power stages or modules that further simplify design and maximize performance, laying a solid hardware foundation for the next generation of ultra-efficient, high-density computing infrastructure.

Detailed MOSFET Application Topologies

High-Voltage PFC Stage Topology (VBL15R30S)

graph LR subgraph "Three-Phase PFC Boost Converter" AC_IN["Three-Phase Input"] --> RECTIFIER["Three-Phase Bridge Rectifier"] RECTIFIER --> BOOST_INDUCTOR["PFC Boost Inductor"] BOOST_INDUCTOR --> SWITCH_NODE["Switching Node"] SWITCH_NODE --> Q1["VBL15R30S
500V/30A"] Q1 --> HV_OUT["High-Voltage DC Output
~400VDC"] BOOST_DIODE["Boost Diode"] --> HV_OUT PFC_CONTROLLER["PFC Controller IC"] --> GATE_DRIVER["High-Voltage Gate Driver"] GATE_DRIVER --> Q1 HV_OUT --> VOLTAGE_FEEDBACK["Voltage Feedback"] VOLTAGE_FEEDBACK --> PFC_CONTROLLER end subgraph "Thermal Interface & Protection" Q1 --> THERMAL_PAD["Exposed Thermal Pad"] THERMAL_PAD --> COLD_PLATE_INTERFACE["Cold Plate Interface"] RCD_SNUBBER["RCD Snubber Circuit"] --> Q1 GATE_CLAMP["Gate-Source Clamp
(TVS Diode)"] --> Q1 CURRENT_SENSE["Current Sense Resistor"] --> PFC_CONTROLLER end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intermediate Bus Converter & Pump Drive Topology (VBGED1401)

graph LR subgraph "48V to 12V/5V Synchronous Buck Converter" HV_IN["48V Input"] --> BUCK_INDUCTOR["Buck Inductor"] BUCK_INDUCTOR --> SW_NODE["Switching Node"] subgraph "Synchronous MOSFET Pair" Q_HIGH["VBGED1401
High Side
40V/150A"] Q_LOW["VBGED1401
Low Side
40V/150A"] end SW_NODE --> Q_HIGH SW_NODE --> Q_LOW Q_HIGH --> HV_IN Q_LOW --> GND SW_NODE --> OUTPUT_FILTER["LC Output Filter"] OUTPUT_FILTER --> LV_OUT["12V/5V Output"] BUCK_CONTROLLER["Buck Controller"] --> GATE_DRIVER["High-Current Driver"] GATE_DRIVER --> Q_HIGH GATE_DRIVER --> Q_LOW end subgraph "Liquid Cooling Pump Drive Circuit" LV_OUT --> PUMP_DRIVER["PWM Motor Driver"] PUMP_DRIVER --> PUMP_MOSFET["VBGED1401 Array"] PUMP_MOSFET --> PUMP_MOTOR["Three-Phase Pump Motor"] SPEED_CONTROL["Speed Control PWM"] --> PUMP_DRIVER CURRENT_LIMIT["Current Limit Protection"] --> PUMP_MOSFET end subgraph "Thermal Management" Q_HIGH --> LFPAK_PAD["LFPAK56 Thermal Pad"] Q_LOW --> LFPAK_PAD LFPAK_PAD --> COLD_PLATE["Cold Plate Contact"] end style Q_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOW fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

CPU/GPU Point-of-Load VRM Topology (VBQG5222)

graph LR subgraph "Multi-Phase Synchronous Buck Converter (Phase 1)" VIN["12V Input"] --> PHASE_INDUCTOR["Phase Inductor L1"] PHASE_INDUCTOR --> PHASE_NODE["Phase Node"] subgraph "VBQG5222 Dual MOSFET Pair" Q_HIGH["N-Channel
High Side"] Q_LOW["P-Channel
Low Side"] end PHASE_NODE --> Q_HIGH PHASE_NODE --> Q_LOW Q_HIGH --> VIN Q_LOW --> PGND PHASE_NODE --> PHASE_CAP["Output Capacitors"] PHASE_CAP --> VOUT["CPU/GPU Core Voltage"] end subgraph "Multi-Phase Interleaving Control" PHASE2["Phase 2
VBQG5222 Pair"] --> VOUT PHASE3["Phase 3
VBQG5222 Pair"] --> VOUT PHASE4["Phase 4
VBQG5222 Pair"] --> VOUT MULTI_PHASE_CTRL["Multi-Phase Controller"] --> PHASE_DRIVERS["Phase Drivers"] PHASE_DRIVERS --> Q_HIGH PHASE_DRIVERS --> Q_LOW PHASE_DRIVERS --> PHASE2 PHASE_DRIVERS --> PHASE3 PHASE_DRIVERS --> PHASE4 VOUT --> VOLTAGE_SENSE["Voltage Sensing"] CURRENT_SENSE["Current Balancing"] --> MULTI_PHASE_CTRL end subgraph "Thermal & Layout Optimization" Q_HIGH --> DFN_PAD["DFN6(2x2) Thermal Pad"] Q_LOW --> DFN_PAD DFN_PAD --> THERMAL_VIAS["Thermal Vias Array"] THERMAL_VIAS --> COPPER_POUR["PCB Copper Pour"] COPPER_POUR --> COLD_PLATE_CONNECTION["Cold Plate Connection"] end style Q_HIGH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_LOW fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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