With the rapid advancement of artificial intelligence, AI scientific computing servers have become the core infrastructure for high-performance computational tasks. The power delivery (PDN) and point-of-load (POL) conversion systems, serving as the "energy heart" of the entire server, must provide ultra-stable, high-efficiency, and high-density power to critical loads such as CPUs, GPUs, memory, and accelerators. The selection of power MOSFETs directly dictates system power efficiency, thermal performance, power density, and operational reliability. Addressing the stringent requirements of AI servers for 24/7 uninterrupted operation, extreme power density, and superior thermal management, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with the server's harsh operating conditions:
- Efficiency & Loss First: Prioritize devices with extremely low Rds(on) to minimize conduction loss in high-current paths, and low Qg/Coss to reduce switching loss at high frequencies. This is critical for reducing total power loss and thermal stress in high-power-density scenarios.
- High-Temperature Stability: Devices must feature a wide junction temperature range (e.g., -55°C ~ 150°C or 175°C) and stable parameters under thermal stress to ensure reliability in confined, high-ambient-temperature chassis environments.
- Package for Power Density and Cooling: Select advanced packages like DFN and TO-LL with low thermal resistance and parasitic inductance for high-current POL applications. Use compact, thermally enhanced packages for auxiliary rails to maximize board space utilization.
- System Reliability Redundancy: Beyond device ruggedness, selection must support system-level protection features (OCP, OTP, UVLO) and ensure sufficient voltage/current derating to handle transients and surges typical in data center environments.
(B) Scenario Adaptation Logic: Categorization by Power Subsystem
Divide the server power architecture into three core scenarios: First, High-Current CPU/GPU POL Conversion, demanding the highest current capability and lowest loss. Second, High-Voltage AC-DC PFC / Isolated DC-DC Stage, requiring high-voltage blocking capability and good switching performance. Third, Intelligent Power Management for Auxiliary Rails, requiring multi-channel control, sequencing, and high-side switching capability for loads like memory, SSDs, and fans.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: High-Current CPU/GPU POL Converter (48V/12V to <1.8V) – The Power Core
These synchronous buck converters handle currents from hundreds to thousands of Amperes, requiring ultra-low-loss MOSFETs for both high-side and low-side switches.
- Recommended Model: VBL1402 (Single-N, 40V, 150A, TO-263)
- Parameter Advantages: Trench technology achieves an ultra-low Rds(on) of 2mΩ (typ.) at 10V. A continuous current rating of 150A (with high peak capability) perfectly suits multi-phase VRM designs for 48V or 12V intermediate buses. The TO-263 (D²PAK) package offers excellent thermal performance for direct-attach heatsinking.
- Adaptation Value: Dramatically reduces conduction loss in the critical power path. For a 100A per-phase current, per-device conduction loss is only 0.2W. Enables higher switching frequencies (300kHz-1MHz) in multi-phase controllers, improving transient response and reducing output capacitor count, directly enhancing computational stability.
- Selection Notes: Must be used in multi-phase configurations with a dedicated PWM controller (e.g., Infineon IR35201, MPS MP296x). Requires meticulous PCB layout with symmetric power loops, thick copper (≥3oz), and extensive use of thermal vias. Active cooling (heatsink/fan) is mandatory.
(B) Scenario 2: PFC / Isolated DC-DC Primary Side (400V Bus) – High-Voltage Handler
The Power Factor Correction (PFC) stage and LLC resonant converter primary side operate at high voltages (~400VDC), requiring MOSFETs with high Vds and good switching characteristics.
- Recommended Model: VBMB15R24S (Single-N, 500V, 24A, TO-220F)
- Parameter Advantages: Super Junction (SJ_Multi-EPI) technology provides an excellent balance of low Rds(on) (120mΩ at 10V) and high voltage rating (500V). The 24A current rating is suitable for medium-to-high power server SMPS units. TO-220F (fully isolated) package simplifies thermal interface design.
- Adaptation Value: The low Rds(on) and fast intrinsic diode reduce conduction and switching losses in critical PFC and LLC circuits, helping to achieve Titanium-level (>96%) efficiency for the AC-DC power supply. The isolated package enhances system safety and creepage distance management.
- Selection Notes: Verify system power level and ensure adequate current derating. Pair with gate drivers having sufficient drive current (≥2A). Snubber circuits or RC dampers are often required to manage voltage spikes and ringing.
(C) Scenario 3: Auxiliary Rail & Power Sequencing Control – The Intelligent Manager
Secondary-side rails (e.g., 12V, 5V, 3.3V, 1.8V for peripherals) and load switch functions for memory/SSDs require compact, efficient switches for power sequencing, on/off control, and fault isolation.
- Recommended Model: VBQG4338 (Dual P+P, -30V, -5.4A per channel, DFN6(2x2)-B)
- Parameter Advantages: Highly integrated dual P-MOSFETs in a tiny DFN6 package save over 60% PCB space compared to two discrete SOT-23 devices. Low Rds(on) of 38mΩ (at 10V) minimizes voltage drop. Low Vth of -1.7V allows for easy direct drive by 3.3V/5V system management controllers (BMC).
- Adaptation Value: Enables precise power sequencing and hot-swap capabilities for NVMe drives and memory modules. Allows independent enabling/disabling of peripheral rails for power capping and fault isolation, enhancing system manageability and reliability. The small size is ideal for dense motherboard layouts.
- Selection Notes: Ideal for 12V or lower voltage rail high-side switching. Requires a simple NPN or dedicated load switch IC for gate control from logic-level signals. Ensure proper copper pad for heat dissipation on the PCB.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
- VBL1402: Requires a dedicated multi-phase PWM controller with integrated high-current drivers. Optimize gate drive strength (typically 2A-5A) to minimize switching losses. Use Kelvin connections for accurate source sensing.
- VBMB15R24S: Use an isolated or high-side gate driver IC (e.g., Si823x) with adequate negative voltage handling for LLC half-bridge configurations. Attention to Miller clamping is crucial.
- VBQG4338: Can be driven directly by BMC or companion IC GPIOs. A series gate resistor (4.7Ω-22Ω) is recommended to control inrush current during turn-on and damp ringing.
(B) Thermal Management Design: Tiered and Aggressive Cooling
- VBL1402 (POL): Most Critical. Requires direct attachment to a custom heatsink via thermal interface material (TIM). PCB must use maximum copper area, multiple thermal vias under the pad, and potentially an embedded heat spreader.
- VBMB15R24S (PFC/LLC): Typically mounted on the main PSU heatsink. Ensure good thermal contact and use insulating washers if needed. Consider forced air cooling from system fans.
- VBQG4338 (Load Switch): A modest PCB copper pad (≥50mm²) is usually sufficient. Locate away from primary heat sources.
- System-Level: AI server thermal design must prioritize airflow across these power components. Computational fluid dynamics (CFD) analysis is recommended to optimize fan placement and ducting.
(C) EMC and Reliability Assurance
- EMC Suppression:
- VBL1402/VBMB15R24S: Use low-ESR/ESL ceramic capacitors very close to drain-source terminals. Implement proper snubber networks. Ferrite beads on gate drive paths can help.
- System-Level: Strict PCB zoning (high-power, high-speed, analog). Use EMI filters on all input/output power cables. Proper shielding of sensitive analog sensing lines.
- Reliability Protection:
- Derating: Adhere to industry-standard derating guidelines (e.g., 80% of Vds, 50-70% of Id at max operating temperature).
- Protection Circuits: Implement comprehensive OCP (using shunt resistors or inductor DCR sensing), OVP, and OTP at the controller level. Use hot-swap controllers for pluggable card slots.
- Transient Protection: Employ TVS diodes at input power connectors and sensitive load points. Ensure proper input bulk capacitance to handle hold-up time requirements.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
- Maximized Power Efficiency: Optimized MOSFET selection across the power chain can push server SMPS efficiency to >96% Titanium level and POL efficiency to >93%, directly reducing operational electricity costs and thermal load.
- Uncompromised Reliability for 24/7 Operation: Devices selected for high-temperature stability and used within conservative derating margins ensure mean time between failures (MTBF) targets are met in demanding data center environments.
- High Power Density Enablement: The use of compact, high-performance packages like DFN and thermally optimized TO-263 allows for more compact power supply designs and denser motherboard layouts, supporting higher computational density per rack unit.
(B) Optimization Suggestions
- Power Scaling: For extreme-power GPU cards (e.g., >500W), consider parallel operation of VBL1402 or explore even lower Rds(on) options in similar packages. For higher-power PSUs (>2kW), select higher-current variants in the VBMB15R24S family.
- Integration Upgrade: For the highest density POL designs, consider using DrMOS or Smart Power Stage modules which integrate driver, MOSFETs, and protection. For multi-rail sequencing, use dedicated power sequence ICs with integrated FETs.
- Special Scenarios: For servers targeting harsh environments or mission-critical applications, seek automotive-grade (AEC-Q101) qualified versions of core MOSFETs where available.
Conclusion
Power MOSFET selection is pivotal to achieving the trifecta of high efficiency, high density, and supreme reliability in AI server power systems. This scenario-based scheme provides a targeted technical roadmap for power design engineers through precise load matching and rigorous system-level co-design. Future exploration should focus on the adoption of Wide Bandgap (SiC and GaN) devices for the highest efficiency PFC and primary-side stages, as well as advanced digital power management, to fuel the next generation of exascale computational infrastructure.

Detailed MOSFET Selection Topology Diagrams