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Optimization of Power Chain for AI Hybrid Storage Arrays: A Precise MOSFET Selection Scheme Based on Main Power Distribution, SSD Rail Switching, and Data Protection Power Path
AI Hybrid Storage Array Power Chain Topology Diagram

AI Hybrid Storage Array Power Chain Overall Topology Diagram

graph LR %% Main Power Input and Distribution subgraph "Main Power Input & Distribution" AC_DC["AC Input
Power Supply"] --> RACK_48V["Rack 48VDC Bus"] RACK_48V --> ORING_CONTROLLER["OR-ing Controller
& Logic"] ORING_CONTROLLER --> MAIN_SWITCH["VBP165R32SE
650V/32A"] MAIN_SWITCH --> INTERMEDIATE_BUS["Intermediate Bus
48V/12V"] INTERMEDIATE_BUS --> IBC_CONVERTER["IBC (Intermediate Bus Converter)"] IBC_CONVERTER --> DRIVE_BACKPLANE_POWER["Drive Backplane Power
12V/5V"] end %% SSD Power Management Section subgraph "SSD Power Rail Management" subgraph "SSD Power Switch Array" SSD_SW_1["VBQF2309
(-30V/-45A)
SSD_12V_Rail_1"] SSD_SW_2["VBQF2309
(-30V/-45A)
SSD_3.3V_Rail_1"] SSD_SW_3["VBQF2309
(-30V/-45A)
SSD_12V_Rail_2"] SSD_SW_4["VBQF2309
(-30V/-45A)
SSD_3.3V_Rail_2"] end DRIVE_BACKPLANE_POWER --> SSD_SW_1 DRIVE_BACKPLANE_POWER --> SSD_SW_2 DRIVE_BACKPLANE_POWER --> SSD_SW_3 DRIVE_BACKPLANE_POWER --> SSD_SW_4 SSD_SW_1 --> NVME_SSD_1["NVMe SSD Bank 1
(12V Input)"] SSD_SW_2 --> NVME_SSD_1 SSD_SW_3 --> NVME_SSD_2["NVMe SSD Bank 2
(12V Input)"] SSD_SW_4 --> NVME_SSD_2 end %% HDD Power & Data Protection Section subgraph "HDD Power & Data Protection Path" DRIVE_BACKPLANE_POWER --> HDD_POWER_DIST["HDD Power Distribution"] HDD_POWER_DIST --> HDD_ARRAY["HDD Array
(Spin-up/Operation)"] BACKUP_SOURCE["Backup Power Source
(SuperCap/Battery)"] --> BACKUP_SWITCH["VBM16I20
650V IGBT+FRD"] BACKUP_SWITCH --> PROTECTION_BUS["Data Protection Bus"] PROTECTION_BUS --> CRITICAL_LOAD["Critical Loads
Controller, Cache"] end %% Control & Monitoring System subgraph "System Control & Monitoring" STORAGE_CONTROLLER["Storage Controller"] --> BMC["Baseboard Management Controller (BMC)"] BMC --> POWER_SEQUENCER["Power Sequencing Logic"] BMC --> HEALTH_MONITOR["Health & Telemetry Monitor"] POWER_SEQUENCER --> GATE_DRIVER_SSD["SSD Switch Gate Driver"] POWER_SEQUENCER --> GATE_DRIVER_MAIN["Main Switch Gate Driver"] POWER_SEQUENCER --> GATE_DRIVER_BACKUP["Backup Switch Gate Driver"] HEALTH_MONITOR --> TEMP_SENSORS["Temperature Sensors"] HEALTH_MONITOR --> CURRENT_SENSORS["Current Sensors"] HEALTH_MONITOR --> VOLTAGE_MONITORS["Voltage Monitors"] end %% Thermal Management subgraph "Hierarchical Thermal Management" LEVEL1_COOLING["Level 1: Forced Airflow
Main Power Path"] --> MAIN_SWITCH LEVEL2_COOLING["Level 2: PCB Conduction + Airflow
SSD Power Switches"] --> SSD_SW_1 LEVEL2_COOLING --> SSD_SW_2 LEVEL3_COOLING["Level 3: Natural/Convection
Backup Circuit"] --> BACKUP_SWITCH end %% Protection Circuits subgraph "Protection & Reliability Circuits" SNUBBER_MAIN["Snubber Network"] --> MAIN_SWITCH RC_FILTERS["RC Gate Filters"] --> SSD_SW_1 TVS_DIODES["TVS/ESD Protection"] --> SSD_SW_1 SNUBBER_BACKUP["Snubber Network"] --> BACKUP_SWITCH PLA_SIGNAL["Power Loss Alert (PLA)"] --> SUPERVISORY_CIRCUIT["Supervisory Circuit"] SUPERVISORY_CIRCUIT --> BACKUP_SWITCH end %% Connections GATE_DRIVER_SSD --> SSD_SW_1 GATE_DRIVER_SSD --> SSD_SW_2 GATE_DRIVER_MAIN --> MAIN_SWITCH GATE_DRIVER_BACKUP --> BACKUP_SWITCH BMC --> CAN_BUS["System CAN Bus"] %% Style Definitions style MAIN_SWITCH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SSD_SW_1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style BACKUP_SWITCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Preface: Building the "Power Integrity Backbone" for Data-Centric Computing – Discussing the Systems Thinking Behind Power Device Selection in Storage Systems
In the era of AI-driven data explosion, a high-performance hybrid storage array (SSD+HDD) is not merely a collection of storage media and controllers. It is, more importantly, a complex system demanding extreme power integrity, high-density power delivery, and robust fault tolerance. Its core performance metrics—consistent low-latency SSD access, reliable HDD spin-up/operation, and guaranteed data persistence during power events—are all deeply rooted in the fundamental power conversion and management infrastructure.
This article employs a systematic and collaborative design mindset to deeply analyze the core challenges within the power delivery network of AI hybrid storage arrays: how, under the multiple constraints of high power density, low noise, high reliability in 24/7 operation, and strict transient response requirements, can we select the optimal combination of power MOSFETs for the three key nodes: main 48V/12V power distribution, SSD multi-rail intelligent switching, and data protection/backup power path management?
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Current Power Arteries: VBP165R32SE (650V, 32A, TO-247) – Main Power Path Switch & OR-ing Controller
Core Positioning & Topology Deep Dive: Serving as the primary switch in the 48V-to-12V/5V intermediate bus converter (IBC) output stage or as the critical OR-ing FET for redundant power supplies. Its ultra-low Rds(on) of 89mΩ ensures minimal conduction loss during high-current delivery to multiple drive backplanes. The 650V rating provides robust protection against voltage spikes on the 48V bus in rack-scale environments.
Key Technical Parameter Analysis:
Ultra-Low Loss Conduction: The 89mΩ Rds(on) is critical for efficiency in high-current paths (e.g., powering 20+ HDDs or multiple SSD banks), directly reducing thermal load on the storage enclosure.
TO-247 Package for Thermal Dominance: This package offers superior thermal dissipation capability, essential for handling the concentrated heat from sustained high-current flow, enabling simpler heatsink design or higher power density.
Selection Trade-off: Compared to lower-current devices requiring parallelization, this single, high-current SJ-MOSFET simplifies layout, improves reliability by reducing component count, and offers better dynamic current sharing performance.
2. The SSD Power Precision Governor: VBQF2309 (-30V, -45A, DFN8) – SSD 12V/3.3V Rail Intelligent Hot-Swap & Power Gating Switch
Core Positioning & System Benefit: As the core switch for individual NVMe SSD or SSD group power rails (12V and 3.3V). Its exceptionally low Rds(on) of 11mΩ and compact DFN8 package are pivotal for space-constrained, high-density storage servers.
Minimized Voltage Drop & Space: The ultra-low Rds(on) guarantees negligible voltage drop at high SSD burst currents, maintaining power integrity. The DFN8 package allows placement directly near SSD connectors, minimizing PCB trace inductance and resistance.
Intelligent Power Management: Enables per-SSD or per-group power sequencing, hot-swap capability, and rapid power gating for thermal or fault management, controlled by the Storage Controller or BMC.
Reason for P-Channel Selection: As a high-side switch on the positive rail, it allows direct control by low-voltage logic (pull low to turn on), simplifying the drive circuit significantly compared to using an N-MOSFET with a charge pump—a critical advantage for managing dozens of power rails.
3. The Data Protection Sentinel: VBM16I20 (650V IGBT+FRD, 20A, TO-220F) – Backup Power (SuperCap/Battery) Bus Switching and Inrush Control
Core Positioning & System Integration Advantage: Acts as the main switch controlling the connection between the backup energy storage (e.g., supercapacitor bank) and the main DC bus during power failure. The integrated IGBT+FRD is ideal for this medium-frequency, unidirectional/bidirectional energy transfer role in hold-up circuits.
Robust Surge Handling: The IGBT structure offers superior short-circuit withstand capability and ruggedness against the large inrush currents when connecting backup storage, which is a common stress point.
Integrated FRD for Seamless Transition: The built-in FRD provides an efficient path for reverse current if needed, simplifying the topology for circuits that may also trickle-charge the backup system from the main bus.
Cost-Effective Reliability: For the specific application of backup power switching, which may not require ultra-high frequency switching, this integrated IGBT solution offers a more robust and cost-optimal solution compared to high-voltage MOSFETs.
II. System Integration Design and Expanded Key Considerations
1. Topology, Sequencing, and Monitoring
Power Sequencing & Integrity: The gate drive for VBQF2309 must support programmable slew rate control for soft-start, preventing bus sag during multiple SSD spin-up. Its status (flag) should be monitored by the management controller.
OR-ing & Fault Management: The VBP165R32SE in OR-ing circuits requires fast comparators and control logic to prevent back-feed during a supply fault, ensuring system availability.
Backup Power Handshake: The switching of VBM16I20 must be precisely synchronized with the Power Loss Alert (PLA) signal and supervisory circuitry to guarantee a glitch-free transition to backup power within milliseconds, ensuring data flush completion.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Air Flow): The VBP165R32SE on the main power path requires attachment to the system's overall airflow heatsink or the chassis wall.
Secondary Heat Source (PCB Conduction & Airflow): Multiple VBQF2309 devices dissipate heat through their thermal pads into the PCB ground plane, which must be designed with adequate vias and coupled to the enclosure's airflow.
Tertiary Heat Source (Natural/Convection): The VBM16I20 in the backup circuit typically operates intermittently; its TO-220F package can be mounted on a small bracket or use PCB copper area for heat dissipation.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBP165R32SE: Utilize snubber networks to clamp voltage spikes caused by parasitic inductance in high-di/dt power paths.
VBQF2309: Implement RC filters on the gate and TVS diodes on the drain to suppress noise and ESD events from hot-plug activities.
VBM16I20: Ensure the drive voltage is stable (e.g., 15V) to maintain low VCEsat, and design snubbers for the inductive bus.
Derating Practice:
Voltage Derating: Operate VBP165R32SE below 520V (80% of 650V); operate VBQF2309 comfortably within the 12V rail.
Current & Thermal Derating: Base the current rating of VBQF2309 on the actual PCB thermal resistance and local ambient temperature, ensuring Tj < 125°C during worst-case SSD burst activity. Ensure VBM16I20 junction temperature is within limits during full backup current delivery.
III. Quantifiable Perspective on Scheme Advantages and Competitor Comparison
Quantifiable Efficiency Improvement: Using VBP165R32SE with 89mΩ vs. a typical 150mΩ device in a 20A main path reduces conduction loss by approximately 40%, lowering system thermal load and cooling cost.
Quantifiable Density & Reliability Improvement: Using VBQF2309 (DFN8) for SSD power switching saves over 70% board space per channel compared to discrete SO-8 solutions, enabling higher SSD counts per rack unit and improving power distribution network reliability.
Lifecycle Cost & Data Integrity Optimization: The robust design centered on VBM16I20 for backup power ensures near-100% success rate in data protection events, preventing data loss and associated costs, while the overall robust power chain reduces field failures.
IV. Summary and Forward Look
This scheme provides a complete, optimized power chain for AI hybrid storage arrays, spanning from high-current main power delivery, granular SSD rail control, to critical data protection power switching. Its essence lies in "matching to needs, optimizing the system":
Main Power Path – Focus on "High-Current Efficiency & Robustness": Select high-current, low-Rds(on) devices in thermally capable packages for the backbone power.
SSD Power Rail – Focus on "Precision & Density": Employ ultra-compact, ultra-low Rds(on) switches to enable intelligent, high-integrity power management at the point of load.
Data Protection Path – Focus on "Ruggedness & Surety": Choose devices with inherent ruggedness (IGBT) for the infrequent but mission-critical backup switching events.
Future Evolution Directions:
Integrated Power Stages (DrMOS): For the next-generation SSD power rail, consider DrMOS modules that integrate the driver, MOSFETs, and protection, further optimizing transient response and footprint.
Digital Power Management: Migrate towards digital controllers and smart power stages for all major rails, enabling real-time telemetry, adaptive tuning, and predictive health management of the entire storage array power system.
Higher Voltage Bus Migration: As rack power moves towards 54V or higher, devices like VBP185R50SFD (850V) would become relevant for the primary OR-ing and conversion stages, offering the necessary voltage margin.

Detailed Topology Diagrams

Main Power Distribution & OR-ing Topology Detail

graph LR subgraph "Redundant 48V Input OR-ing" PSU1["48V Power Supply 1"] --> ORING_FET1["VBP165R32SE
OR-ing FET 1"] PSU2["48V Power Supply 2"] --> ORING_FET2["VBP165R32SE
OR-ing FET 2"] ORING_FET1 --> COMMON_BUS["Common 48V Bus"] ORING_FET2 --> COMMON_BUS ORING_CONTROLLER["OR-ing Controller"] --> COMPARATOR["Fast Comparator"] COMPARATOR --> GATE_DRIVER["Gate Driver"] GATE_DRIVER --> ORING_FET1 GATE_DRIVER --> ORING_FET2 COMMON_BUS --> VOLTAGE_FEEDBACK["Voltage Feedback"] VOLTAGE_FEEDBACK --> ORING_CONTROLLER end subgraph "Intermediate Bus Converter (IBC)" COMMON_BUS --> IBC_INPUT["IBC Input Stage"] IBC_INPUT --> ISOLATION_TRANSFORMER["Isolation Transformer"] ISOLATION_TRANSFORMER --> IBC_OUTPUT["IBC Output Stage"] IBC_OUTPUT --> OUTPUT_SWITCH["VBP165R32SE
Output Switch"] OUTPUT_SWITCH --> INTERMEDIATE_BUS_OUT["12V Intermediate Bus"] IBC_CONTROLLER["IBC Controller"] --> IBC_GATE_DRIVER["Gate Driver"] IBC_GATE_DRIVER --> OUTPUT_SWITCH INTERMEDIATE_BUS_OUT --> CURRENT_FEEDBACK["Current Feedback"] CURRENT_FEEDBACK --> IBC_CONTROLLER end subgraph "Backplane Power Distribution" INTERMEDIATE_BUS_OUT --> POL_CONVERTER_12V["12V Point-of-Load"] INTERMEDIATE_BUS_OUT --> POL_CONVERTER_5V["5V Point-of-Load"] POL_CONVERTER_12V --> HDD_CONNECTOR["HDD Backplane Connector"] POL_CONVERTER_5V --> HDD_CONNECTOR POL_CONVERTER_12V --> SSD_POWER_RAIL["SSD Power Rail Input"] end style ORING_FET1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style OUTPUT_SWITCH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

SSD Power Rail Switching & Management Topology Detail

graph LR subgraph "Single NVMe SSD Power Channel" SSD_POWER_IN["12V/3.3V Input Rail"] --> HIGH_SIDE_SWITCH["VBQF2309
P-MOSFET Switch"] HIGH_SIDE_SWITCH --> SSD_CONNECTOR["NVMe SSD Connector"] CONTROL_LOGIC["BMC/Controller GPIO"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> GATE_CONTROL["Gate Control Circuit"] GATE_CONTROL --> HIGH_SIDE_SWITCH CURRENT_SENSE["Current Sense Resistor"] --> SENSE_AMPLIFIER["Sense Amplifier"] SENSE_AMPLIFIER --> ADC["ADC"] ADC --> CONTROL_LOGIC VOLTAGE_MONITOR["Voltage Monitor"] --> CONTROL_LOGIC end subgraph "Multi-Channel SSD Bank Management" CONTROL_LOGIC --> SEQUENCING_LOGIC["Power Sequencing Logic"] SEQUENCING_LOGIC --> CHANNEL_1["Channel 1 Enable"] SEQUENCING_LOGIC --> CHANNEL_2["Channel 2 Enable"] SEQUENCING_LOGIC --> CHANNEL_N["Channel N Enable"] CHANNEL_1 --> SWITCH_1["VBQF2309 Ch1"] CHANNEL_2 --> SWITCH_2["VBQF2309 Ch2"] CHANNEL_N --> SWITCH_N["VBQF2309 ChN"] SWITCH_1 --> SSD_BANK_1["SSD Bank 1"] SWITCH_2 --> SSD_BANK_2["SSD Bank 2"] SWITCH_N --> SSD_BANK_N["SSD Bank N"] end subgraph "Hot-Swap & Protection" HOTPLUG_DETECT["Hot-Plug Detection"] --> INRUSH_CONTROL["Inrush Current Control"] INRUSH_CONTROL --> SOFT_START["Soft-Start Circuit"] SOFT_START --> HIGH_SIDE_SWITCH TVS_ARRAY["TVS Diode Array"] --> SSD_CONNECTOR RC_FILTER["RC Filter"] --> GATE_CONTROL THERMAL_SENSOR["Thermal Sensor"] --> CONTROL_LOGIC end style HIGH_SIDE_SWITCH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SWITCH_1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Data Protection & Backup Power Path Topology Detail

graph LR subgraph "Backup Power Source & Switching" SUPERCAP_BANK["Supercapacitor Bank"] --> CHARGE_CONTROLLER["Charge Controller"] BATTERY_BACKUP["Lithium Backup Battery"] --> CHARGE_CONTROLLER MAIN_48V_BUS["Main 48V Bus"] --> TRICKLE_CHARGE["Trickle Charge Circuit"] TRICKLE_CHARGE --> SUPERCAP_BANK CHARGE_CONTROLLER --> BACKUP_BUS["Backup Power Bus"] BACKUP_BUS --> PROTECTION_SWITCH["VBM16I20 IGBT+FRD"] PROTECTION_SWITCH --> CRITICAL_BUS["Critical Load Bus"] end subgraph "Power Fail Detection & Switching Control" MAIN_48V_BUS --> VOLTAGE_DETECTOR["Voltage Detector"] VOLTAGE_DETECTOR --> PLA_GENERATOR["PLA Signal Generator"] PLA_GENERATOR --> SUPERVISORY_CIRCUIT["Supervisory Circuit"] SUPERVISORY_CIRCUIT --> GATE_DRIVER["IGBT Gate Driver"] GATE_DRIVER --> PROTECTION_SWITCH SUPERVISORY_CIRCUIT --> CHARGE_DISABLE["Charge Disable"] CHARGE_DISABLE --> TRICKLE_CHARGE end subgraph "Critical Loads During Backup" CRITICAL_BUS --> CONTROLLER_POWER["Storage Controller Power"] CRITICAL_BUS --> CACHE_POWER["Cache Memory Power"] CRITICAL_BUS --> FLUSH_CIRCUIT["Data Flush Circuit"] CONTROLLER_POWER --> DATA_FLUSH["Data Flush Operation"] CACHE_POWER --> DATA_FLUSH FLUSH_CIRCUIT --> DATA_FLUSH DATA_FLUSH --> FLUSH_COMPLETE["Flush Complete Signal"] FLUSH_COMPLETE --> SUPERVISORY_CIRCUIT end subgraph "Protection Circuits" SNUBBER_NETWORK["RCD Snubber Network"] --> PROTECTION_SWITCH DRIVE_REGULATOR["15V Gate Drive Regulator"] --> GATE_DRIVER CURRENT_LIMIT["Current Limit Circuit"] --> PROTECTION_SWITCH VOLTAGE_CLAMP["Voltage Clamp Circuit"] --> CRITICAL_BUS end style PROTECTION_SWITCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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