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Preface: Constructing the "Power Backbone" for AI Liquid-Cooled Storage Systems – Discussing the Systems Thinking Behind Power Device Selection
AI Liquid-Cooled Storage System Power Topology Diagram

AI Liquid-Cooled Storage System Power Chain Overall Topology Diagram

graph LR %% Input Power Distribution subgraph "Input Power Distribution" INPUT_BUS["400V DC Input Bus"] --> MAIN_DCDC["Primary DC/DC Converter"] end %% Primary DC/DC Conversion Stage subgraph "Primary High-Efficiency DC/DC Converter" MAIN_DCDC --> CONVERTER_STAGE["High-Frequency Isolated Converter"] subgraph "Primary Switch Array" Q_PRIMARY1["VBP165R96SFD
650V/96A (SJ)"] Q_PRIMARY2["VBP165R96SFD
650V/96A (SJ)"] end CONVERTER_STAGE --> Q_PRIMARY1 CONVERTER_STAGE --> Q_PRIMARY2 Q_PRIMARY1 --> HV_TO_ISOLATED["HV to Transformer"] Q_PRIMARY2 --> HV_TO_ISOLATED HV_TO_ISOLATED --> ISOLATED_XFMR["Isolation Transformer"] end %% Intermediate Voltage Distribution subgraph "Intermediate Voltage Bus Distribution" ISOLATED_XFMR --> INTERMEDIATE_BUS["Intermediate Voltage Bus
12V/48V"] INTERMEDIATE_BUS --> AUX_DISTRIBUTION["Auxiliary Power Distribution"] INTERMEDIATE_BUS --> STORAGE_RAIL["Storage Rack Power Rails"] end %% High-Current Auxiliary Power Distribution subgraph "High-Current Auxiliary Power Distribution" AUX_DISTRIBUTION --> AUX_SWITCH_NODE["Auxiliary Switch Node"] subgraph "High-Current Distribution Switches" Q_AUX1["VBP2157N
-150V/-50A (P-Ch)"] Q_AUX2["VBP2157N
-150V/-50A (P-Ch)"] end AUX_SWITCH_NODE --> Q_AUX1 AUX_SWITCH_NODE --> Q_AUX2 Q_AUX1 --> SECONDARY_CONVERTERS["Secondary Converters"] Q_AUX2 --> FAN_ARRAYS["Fan Arrays"] SECONDARY_CONVERTERS --> BACKUP_CIRCUITS["Backup Circuits"] FAN_ARRAYS --> COOLING_SYSTEM["Cooling System"] end %% Low-Voltage Control & Protection subgraph "Low-Voltage Control & Protection Domain" BMC_FPGA["BMC/FPGA Controller"] --> CONTROL_SIGNALS["Control Signals"] subgraph "Precision Logic-Level Switches" Q_LOGIC1["VB562K
Dual N+P (SOT23-6)"] Q_LOGIC2["VB562K
Dual N+P (SOT23-6)"] Q_LOGIC3["VB562K
Dual N+P (SOT23-6)"] end CONTROL_SIGNALS --> Q_LOGIC1 CONTROL_SIGNALS --> Q_LOGIC2 CONTROL_SIGNALS --> Q_LOGIC3 Q_LOGIC1 --> LOAD_SWITCHING["Load Switching/OR-ing"] Q_LOGIC2 --> SIGNAL_ISOLATION["Signal Level Translation"] Q_LOGIC3 --> HOT_SWAP_CONTROL["Hot-Swap Control"] end %% System Monitoring & Management subgraph "System Monitoring & Management" TEMP_SENSORS["Temperature Sensors"] --> SYSTEM_MGMT["System Management Controller"] CURRENT_SENSE["Current Sense Circuits"] --> SYSTEM_MGMT VOLTAGE_MON["Voltage Monitors"] --> SYSTEM_MGMT SYSTEM_MGMT --> FAULT_REPORTING["Fault Reporting"] SYSTEM_MGMT --> PWM_CONTROL["PWM Control Signals"] end %% Thermal Management Hierarchy subgraph "Three-Level Thermal Management" COOLING_LEVEL1["Level 1: Liquid Cold Plate"] --> Q_PRIMARY1 COOLING_LEVEL1 --> Q_PRIMARY2 COOLING_LEVEL2["Level 2: Air-Cooled Heat Sink"] --> Q_AUX1 COOLING_LEVEL2 --> Q_AUX2 COOLING_LEVEL3["Level 3: PCB Conduction"] --> Q_LOGIC1 COOLING_LEVEL3 --> Q_LOGIC2 end %% Style Definitions style Q_PRIMARY1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_AUX1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOGIC1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style SYSTEM_MGMT fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the era of AI and high-density computing, the power supply architecture of liquid-cooled storage systems is the cornerstone for ensuring data integrity, computational stability, and energy efficiency. An excellent system is not just a cluster of drives and controllers; it is a meticulously managed ecosystem for high-current, high-availability power delivery and conversion. Its core performance—high-efficiency power conversion, precise voltage regulation for critical loads, and robust fault isolation—hinges on the judicious selection of power semiconductor devices.
This article adopts a holistic, system-level approach to dissect the core challenges within the power path of AI liquid-cooled storage systems: how to select the optimal power MOSFETs for critical nodes—such as the high-efficiency main DC/DC converter, the high-current auxiliary power distribution, and the low-voltage precision switching—under the constraints of high power density, exceptional reliability under thermal stress, and stringent cost control.
Within an AI storage system's power design, the choice of switching devices directly determines conversion efficiency, thermal load, power density, and system uptime. Based on comprehensive considerations of high-voltage handling, low-loss conduction, parallel capability, and compact integration, this article selects three key devices to construct a tiered, synergistic power solution.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Efficiency Power Core: VBP165R96SFD (650V, 96A, Rds(on)@10V=19mΩ, TO-247, SJ_Multi-EPI) – Primary High-Voltage DC/DC Converter Switch
Core Positioning & Topology Deep Dive: Ideal as the primary switch in high-power, high-efficiency isolated DC/DC converters (e.g., LLC Resonant or Phase-Shifted Full-Bridge) that step down from a 400V DC bus to intermediate voltages (e.g., 12V/48V) for storage racks. Its Super Junction Multi-EPI technology delivers an exceptionally low specific on-resistance, making it perfect for high-frequency (e.g., 100-500kHz) hard-switching or soft-switching topologies where low conduction and switching loss are paramount.
Key Technical Parameter Analysis:
Ultra-Low Rds(on): The 19mΩ rating at 10V Vgs is outstanding for a 650V device, minimizing conduction losses in high-current paths, directly boosting conversion efficiency and reducing thermal load on the liquid cooling system.
High Current Capability: The 96A continuous current rating supports parallel operation for even higher power stages or provides significant headroom for transient loads, enhancing system robustness.
Technology Advantage: Super Junction (SJ) technology offers the best trade-off between breakdown voltage and on-resistance. The Multi-EPI process further optimizes switching characteristics and reliability.
Selection Trade-off: Compared to standard planar MOSFETs or lower-current SJ devices, the VBP165R96SFD offers superior power density and efficiency, justifying its use in the highest-stress conversion stage where losses have the greatest system-wide impact.
2. The High-Current Auxiliary Power Manager: VBP2157N (-150V, -50A, Rds(on)@10V=65mΩ, TO-247, Trench) – Negative Rail or High-Current Auxiliary Power Distribution Switch
Core Positioning & System Benefit: Serves as a high-side switch for high-current auxiliary rails (e.g., a -12V or -48V bus, or as a P-channel switch for a positive rail using the body diode orientation) within the power distribution unit. Its very low Rds(on) of 65mΩ at 10V Vgs ensures minimal voltage drop and power loss when distributing tens of amperes to secondary converters, fan arrays, or backup circuits.
Application Example: Can be used for intelligent enabling/disabling of entire power shelves or high-power redundant feeds, providing both power control and fault isolation. Its P-channel nature simplifies high-side drive circuitry when used on positive rails.
Drive & Package Considerations: The TO-247 package offers excellent thermal performance, crucial for a device handling high continuous current. Its gate threshold (Vth = -2.0V) allows for confident turn-on/off with standard gate drive voltages.
3. The Precision Logic-Level Companion: VB562K (Dual N+P, ±60V, 0.8A/-0.55A, SOT23-6, Trench) – Low-Voltage Signal & Protection Switching
Core Positioning & System Integration Advantage: This dual complementary MOSFET pair in a minuscule SOT23-6 package is the ideal solution for space-constrained, low-power control and protection functions. It enables elegant solutions for:
Load Switching & OR-ing: Power path selection between redundant low-current supplies (e.g., management controller power).
Signal Level Translation & Isolation: Isolating digital control signals between different power domains.
Hot-Swap & Inrush Current Limiting: In conjunction with a controller, for safely plugging modules.
Key Technical Parameter Analysis:
Logic-Level Compatibility: Low Rds(on) at 4.5V Vgs (850mΩ N-Ch, 2410mΩ P-Ch) allows efficient operation directly from 3.3V or 5V microcontroller GPIO pins, eliminating need for level shifters.
Integrated Complementary Pair: Saves critical board space and simplifies design for bidirectional switching or push-pull stages compared to using two discrete devices.
Reason for Selection: In a dense AI storage system, managing numerous low-power control signals and protection circuits requires highly integrated, board-space-efficient components. The VB562K perfectly meets this need for intelligent, localized power management.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Coordination
High-Frequency Primary Converter: Driving the VBP165R96SFD requires a high-current, low-inductance gate driver capable of fast transitions to minimize switching loss. Its switching node must be carefully laid out to minimize ringing and EMI.
High-Current Power Distribution: The gate drive for VBP2157N must be robust enough to handle its higher gate charge quickly, ensuring clean switching during high-current transitions. Its status (e.g., via sense FET or temperature monitor if available) should be reported to the system management controller.
Digital Control Domain: The VB562K can be driven directly by FPGA or BMC GPIOs. Incorporating series gate resistors is crucial to dampen oscillations and control rise/fall times, protecting the driving IC.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Liquid Cold Plate): The VBP165R96SFD in the main DC/DC converter is a primary heat source and must be mounted directly onto a liquid-cooled cold plate or a heatsink with excellent thermal interface material.
Secondary Heat Source (Forced Air/Liquid Assisted): The VBP2157N, handling high continuous current, will require a dedicated heatsink, potentially within an airflow path or coupled to a secondary cooling loop.
Tertiary Heat Source (PCB Conduction & Ambient): The VB562K and associated logic circuits primarily rely on PCB copper pours and vias for heat dissipation, aided by the system's overall ambient temperature control.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBP165R96SFD: In LLC or similar topologies, the resonant tank naturally reduces switching stress, but careful snubber design across the primary switches may still be needed to clamp any parasitic ringing.
VBP2157N: For inductive auxiliary loads, ensure proper freewheeling paths with Schottky diodes to handle turn-off energy.
VB562K: Use TVS diodes on its drain pins if switching signals connected to external cables to protect against ESD or transient surges.
Derating Practice:
Voltage Derating: Operational VDS for VBP165R96SFD should be below 80% of 650V (520V). For VBP2157N, ensure VDS stress is suitably below its -150V rating.
Current & Thermal Derating: Use transient thermal impedance curves. Limit continuous junction temperature (Tj) to 125°C or lower for long-term reliability. The high current rating of VBP165R96SFD and VBP2157N must be derated based on actual heatsink temperature and duty cycle.
III. Quantifiable Perspective on Scheme Advantages and Competitor Comparison
Quantifiable Efficiency Gain: In a 3kW primary DC/DC stage, using VBP165R96SFD with its 19mΩ Rds(on) versus a typical 650V/30mΩ SJ MOSFET can reduce conduction losses by over 35% at full load, directly lowering coolant temperature rise and improving PUE.
Quantifiable Power Density & Reliability Improvement: Using the VB562K for eight different control/protection circuits saves >70% PCB area compared to discrete SOT-23 devices, reduces component count, and increases the MTBF of the management subsystem.
Lifecycle Cost Optimization: The high efficiency of the primary converter reduces electricity costs. The robustness of the selected devices, coupled with proper derating, minimizes field failures and downtime in critical AI storage infrastructure.
IV. Summary and Forward Look
This scheme presents a comprehensive, optimized power chain for AI liquid-cooled storage systems, addressing high-voltage conversion, high-current distribution, and precision low-power control. Its essence is "right-sizing for the task, optimizing the whole":
Primary Conversion Level – Focus on "Peak Efficiency": Invest in state-of-the-art SJ MOSFETs to minimize losses in the highest-power path.
Power Distribution Level – Focus on "Robustness & Control": Use high-current, low-loss switches to ensure reliable and efficient power delivery to subsystems.
Control & Protection Level – Focus on "Intelligent Integration": Leverage highly integrated dual MOSFETs to enable sophisticated control and protection in minimal space.
Future Evolution Directions:
Wide Bandgap Adoption: For the next generation of even higher efficiency and power density, the primary converter could migrate to Gallium Nitride (GaN) HEMTs, enabling multi-MHz switching frequencies and further size reduction.
Fully Integrated Power Stages: Consider smart power stages or DrMOS modules that integrate the driver, MOSFETs, and protection, simplifying design and improving switching performance for point-of-load converters.
Advanced Monitoring: Integration of current sensing and temperature monitoring within the power switch package itself for enhanced system health analytics and predictive maintenance.
Engineers can adapt this framework based on specific system parameters: input voltage range, total power budget, number and type of auxiliary rails, and the thermal performance of the liquid cooling solution, to design optimized, reliable power systems for AI storage applications.

Detailed Topology Diagrams

Primary High-Efficiency DC/DC Converter Topology Detail

graph LR subgraph "High-Frequency Isolated Converter Topology" INPUT_400V["400V DC Input Bus"] --> RESONANT_TANK["LLC/PSFB Resonant Tank"] RESONANT_TANK --> PRIMARY_SW_NODE["Primary Switching Node"] subgraph "Primary Switch Half-Bridge" Q_HB1["VBP165R96SFD
650V/96A"] Q_HB2["VBP165R96SFD
650V/96A"] end PRIMARY_SW_NODE --> Q_HB1 PRIMARY_SW_NODE --> Q_HB2 Q_HB1 --> PRIMARY_GND["Primary Ground"] Q_HB2 --> PRIMARY_GND PRIMARY_SW_NODE --> HF_TRANSFORMER["High-Frequency Transformer"] HF_TRANSFORMER --> RECTIFICATION["Secondary Rectification"] RECTIFICATION --> INTERMEDIATE_OUT["12V/48V Intermediate Bus"] end subgraph "Gate Drive & Control" GATE_DRIVER["High-Current Gate Driver"] --> Q_HB1 GATE_DRIVER --> Q_HB2 CONTROLLER_IC["LLC/PSFB Controller"] --> GATE_DRIVER CURRENT_FEEDBACK["Current Sense"] --> CONTROLLER_IC VOLTAGE_FEEDBACK["Voltage Sense"] --> CONTROLLER_IC end subgraph "Protection Circuits" SNUBBER_NETWORK["RCD/RC Snubber"] --> Q_HB1 SNUBBER_NETWORK --> Q_HB2 OVERCURRENT_PROT["Overcurrent Protection"] --> CONTROLLER_IC OVERVOLTAGE_PROT["Overvoltage Protection"] --> CONTROLLER_IC end style Q_HB1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_HB2 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Auxiliary Power Distribution & Control Topology Detail

graph LR subgraph "High-Current Auxiliary Rail Switching" INTERMEDIATE_RAIL["12V/48V Intermediate Rail"] --> AUX_SW_HIGH["High-Side Switch Node"] subgraph "P-Channel High-Side Switches" Q_AUX_HS1["VBP2157N
-150V/-50A"] Q_AUX_HS2["VBP2157N
-150V/-50A"] end AUX_SW_HIGH --> Q_AUX_HS1 AUX_SW_HIGH --> Q_AUX_HS2 Q_AUX_HS1 --> SECONDARY_POWER["Secondary Converters Rail"] Q_AUX_HS2 --> COOLING_POWER["Cooling System Rail"] SECONDARY_POWER --> SECONDARY_LOAD["Point-of-Load Converters"] COOLING_POWER --> FAN_PUMP_LOAD["Fans & Pump Arrays"] end subgraph "Logic-Level Control & Protection Switching" BMC_GPIO["BMC/FPGA GPIO"] --> LEVEL_SHIFTER["Level Shifter/Driver"] subgraph "Dual MOSFET Switch Arrays" Q_LOGIC_SW1["VB562K Dual N+P"] Q_LOGIC_SW2["VB562K Dual N+P"] Q_LOGIC_SW3["VB562K Dual N+P"] end LEVEL_SHIFTER --> Q_LOGIC_SW1 LEVEL_SHIFTER --> Q_LOGIC_SW2 LEVEL_SHIFTER --> Q_LOGIC_SW3 subgraph "Application Functions" Q_LOGIC_SW1 --> LOAD_SELECT["Redundant Power OR-ing"] Q_LOGIC_SW2 --> SIGNAL_TRANS["Domain Signal Translation"] Q_LOGIC_SW3 --> INRUSH_CTRL["Hot-Swap Inrush Control"] LOAD_SELECT --> REDUNDANT_SUPPLIES["Dual Supplies"] SIGNAL_TRANS --> ISOLATED_SIGNALS["Isolated Domains"] INRUSH_CTRL --> MODULE_POWER["Module Power Rail"] end end subgraph "Monitoring & Feedback" CURRENT_MON["Current Monitoring"] --> SYSTEM_BMC["System BMC"] TEMP_MON["Temperature Monitoring"] --> SYSTEM_BMC SYSTEM_BMC --> ENABLE_SIGNALS["Enable/Disable Signals"] ENABLE_SIGNALS --> Q_AUX_HS1 ENABLE_SIGNALS --> Q_AUX_HS2 end style Q_AUX_HS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOGIC_SW1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Thermal Management & Protection Topology Detail

graph LR subgraph "Three-Level Cooling Architecture" LEVEL1["Level 1: Liquid Cooling"] --> COLD_PLATE["Liquid Cold Plate"] COLD_PLATE --> Q_PRIMARY_COOL["Primary MOSFETs (VBP165R96SFD)"] LEVEL2["Level 2: Forced Air"] --> HEATSINK_FANS["Heatsink with Fans"] HEATSINK_FANS --> Q_AUX_COOL["Auxiliary MOSFETs (VBP2157N)"] LEVEL3["Level 3: Conduction"] --> PCB_THERMAL["PCB Thermal Design"] PCB_THERMAL --> Q_LOGIC_COOL["Logic Switches (VB562K)"] end subgraph "Temperature Sensing Network" TEMP_SENSOR1["Cold Plate Temp"] --> TEMP_MONITOR["Temperature Monitor IC"] TEMP_SENSOR2["Heatsink Temp"] --> TEMP_MONITOR TEMP_SENSOR3["Ambient Air Temp"] --> TEMP_MONITOR TEMP_SENSOR4["PCB Local Temp"] --> TEMP_MONITOR TEMP_MONITOR --> CONTROL_LOGIC["Cooling Control Logic"] end subgraph "Cooling Control System" CONTROL_LOGIC --> PWM_CONTROLLER["PWM Controller"] PWM_CONTROLLER --> PUMP_DRIVER["Pump Driver"] PWM_CONTROLLER --> FAN_DRIVER["Fan Driver"] PUMP_DRIVER --> LIQUID_PUMP["Liquid Pump"] FAN_DRIVER --> FAN_ARRAY["Fan Array"] end subgraph "Electrical Protection Network" TVS_ARRAY["TVS Diode Array"] --> GATE_DRIVERS["Gate Driver ICs"] SCHOTTKY_DIODES["Schottky Freewheeling Diodes"] --> Q_AUX_COOL OVERCURRENT_COMP["Overcurrent Comparator"] --> FAULT_LATCH["Fault Latch"] OVERVOLTAGE_COMP["Overvoltage Comparator"] --> FAULT_LATCH FAULT_LATCH --> SHUTDOWN_SIGNAL["Global Shutdown"] SHUTDOWN_SIGNAL --> Q_PRIMARY_COOL SHUTDOWN_SIGNAL --> Q_AUX_COOL end style Q_PRIMARY_COOL fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_AUX_COOL fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LOGIC_COOL fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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