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Intelligent Power MOSFET Selection Solution for AI Liquid-Cooled Server Clusters – Design Guide for High-Density, High-Efficiency, and High-Reliability Power Systems
AI Liquid-Cooled Server Cluster Power MOSFET System Topology Diagram

AI Server Cluster Power System Overall Topology Diagram

graph TD %% AC-DC Front End Section subgraph "AC-DC Front End: PFC & LLC Conversion" AC_IN["Three-Phase 480VAC Input"] --> EMI_FILTER["EMI Filter & Surge Protection"] EMI_FILTER --> PFC_BRIDGE["Three-Phase Rectifier"] PFC_BRIDGE --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_NODE["PFC Switching Node"] subgraph "High-Voltage SiC MOSFET Array" Q_PFC1["VBP165C93-4L
650V/93A (SiC)"] Q_PFC2["VBP165C93-4L
650V/93A (SiC)"] end PFC_NODE --> Q_PFC1 PFC_NODE --> Q_PFC2 Q_PFC1 --> HV_BUS["High-Voltage DC Bus
~800VDC"] Q_PFC2 --> HV_BUS HV_BUS --> LLC_RESONANT["LLC Resonant Tank"] LLC_RESONANT --> LLC_XFMR["LLC Transformer Primary"] LLC_XFMR --> LLC_NODE["LLC Switching Node"] subgraph "LLC Primary MOSFETs" Q_LLC1["VBP165C93-4L
650V/93A (SiC)"] Q_LLC2["VBP165C93-4L
650V/93A (SiC)"] end LLC_NODE --> Q_LLC1 LLC_NODE --> Q_LLC2 Q_LLC1 --> GND_PRI Q_LLC2 --> GND_PRI HV_BUS --> AUX_PSU["Auxiliary Power Supply
12V/5V"] end %% Intermediate Bus & POL Conversion subgraph "Intermediate Bus & POL Voltage Regulation" LLC_XFMR_SEC["LLC Transformer Secondary"] --> SR_NODE["Synchronous Rectification Node"] subgraph "Synchronous Rectification MOSFETs" Q_SR1["VBP1102N
100V/72A"] Q_SR2["VBP1102N
100V/72A"] end SR_NODE --> Q_SR1 SR_NODE --> Q_SR2 Q_SR1 --> INT_BUS["Intermediate DC Bus
48VDC"] Q_SR2 --> INT_BUS INT_BUS --> DCDC_CONV["DC-DC Converter
48V to 12V/5V"] DCDC_CONV --> POL_VRM["Point-of-Load (POL) VRM"] subgraph "Multi-Phase CPU/GPU VRM" PHASE1["Phase 1: VBP1102N x2"] PHASE2["Phase 2: VBP1102N x2"] PHASE3["Phase 3: VBP1102N x2"] PHASE4["Phase 4: VBP1102N x2"] end POL_VRM --> PHASE1 POL_VRM --> PHASE2 POL_VRM --> PHASE3 POL_VRM --> PHASE4 PHASE1 --> CPU_PWR["CPU Power Rail
~1.8V, 500A+"] PHASE2 --> CPU_PWR PHASE3 --> GPU_PWR["GPU Power Rail
~12V, 300A+"] PHASE4 --> GPU_PWR end %% Thermal Management Drive Section subgraph "Liquid Cooling System Drive" MCU["System Management MCU"] --> PUMP_DRIVER["Pump Driver Controller"] MCU --> FAN_DRIVER["Fan Driver Controller"] subgraph "Liquid Cooling Pump H-Bridge" Q_PUMP_HS1["VBM82152M
-150V/-15A (P-MOS)"] Q_PUMP_LS1["VBP1102N
100V/72A"] Q_PUMP_HS2["VBM82152M
-150V/-15A (P-MOS)"] Q_PUMP_LS2["VBP1102N
100V/72A"] end PUMP_DRIVER --> Q_PUMP_HS1 PUMP_DRIVER --> Q_PUMP_LS1 PUMP_DRIVER --> Q_PUMP_HS2 PUMP_DRIVER --> Q_PUMP_LS2 Q_PUMP_HS1 --> PUMP_MOTOR["Liquid Cooling Pump
(BLDC/PMSM)"] Q_PUMP_LS1 --> PUMP_MOTOR Q_PUMP_HS2 --> PUMP_MOTOR Q_PUMP_LS2 --> PUMP_MOTOR subgraph "High-Performance Fan Arrays" FAN_HS["VBM82152M xN"] FAN_LS["VBP1102N xN"] end FAN_DRIVER --> FAN_HS FAN_DRIVER --> FAN_LS FAN_HS --> FAN_ARRAY["Server Fan Array"] FAN_LS --> FAN_ARRAY end %% Control & Monitoring subgraph "Intelligent Control & Protection" AUX_PSU --> MCU MCU --> SENSOR_INTERFACE["Sensor Interface"] SENSOR_INTERFACE --> TEMP_SENSORS["Temperature Sensors"] SENSOR_INTERFACE --> CURRENT_SENSE["Precision Current Sensing"] SENSOR_INTERFACE --> VOLTAGE_MON["Voltage Monitoring"] MCU --> PROTECTION_LOGIC["Protection Logic"] PROTECTION_LOGIC --> OCP["Over-Current Protection"] PROTECTION_LOGIC --> OVP["Over-Voltage Protection"] PROTECTION_LOGIC --> OTP["Over-Temperature Protection"] OCP --> GATE_DRIVERS["Gate Driver Disable"] OVP --> GATE_DRIVERS OTP --> GATE_DRIVERS end %% Thermal Management System subgraph "Three-Level Thermal Management" LIQUID_COLD_PLATE["Liquid Cold Plate"] --> Q_SR1 LIQUID_COLD_PLATE --> Q_SR2 LIQUID_COLD_PLATE --> PHASE1 LIQUID_COLD_PLATE --> PHASE2 FORCED_AIR["Forced Air Cooling"] --> Q_PFC1 FORCED_AIR --> Q_LLC1 FORCED_AIR --> Q_PUMP_HS1 NATURAL_CONV["PCB Thermal Design"] --> MCU NATURAL_CONV --> GATE_DRIVERS THERMAL_CONTROLLER["Thermal Controller"] --> LIQUID_COLD_PLATE THERMAL_CONTROLLER --> FORCED_AIR THERMAL_CONTROLLER --> PUMP_MOTOR THERMAL_CONTROLLER --> FAN_ARRAY end %% Communications MCU --> PMBUS["PMBus Communication"] MCU --> I2C_SMBUS["I2C/SMBus Interface"] MCU --> ETHERNET["Ethernet Management"] %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_PUMP_HS1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style PHASE1 fill:#f3e5f5,stroke:#9c27b0,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the explosive growth of AI computing demand and the continuous evolution of data center infrastructure, AI liquid-cooled server clusters have become the core of high-performance computing. Their power delivery and thermal management systems, serving as the energy conversion and control center, directly determine the cluster's computational efficiency, power usage effectiveness (PUE), operational stability, and overall cost of ownership. The power MOSFET, as a key switching component in these systems, significantly impacts power density, conversion efficiency, thermal performance, and long-term reliability through its selection. Addressing the high-power, high-ripple, and harsh operational environment (high temperature, high humidity) of AI server clusters, this article proposes a complete, actionable power MOSFET selection and design implementation plan with a scenario-oriented and systematic design approach.
I. Overall Selection Principles: System Compatibility and Balanced Design
The selection of power MOSFETs should not pursue superiority in a single parameter but achieve a balance among voltage/current rating, switching performance, thermal impedance, and package robustness to precisely match the stringent requirements of server power supplies and liquid cooling pump/fan drives.
Voltage and Current Margin Design: Based on the system bus voltage (e.g., 12V input, 48V intermediate bus, or high-voltage PFC stages), select MOSFETs with a voltage rating margin of ≥50-100% to handle severe switching spikes and transients in multi-phase VRMs and LLC converters. The current rating must withstand high ripple currents with sufficient margin, typically keeping the continuous operating current below 50-60% of the device’s rated DC current.
Ultra-Low Loss Priority: Loss directly dictates power supply efficiency and heat generation. Conduction loss is critical in high-current paths like synchronous rectification, necessitating ultra-low on-resistance (Rds(on)). Switching loss dominates in high-frequency primary-side switches, requiring low gate charge (Qg) and low output capacitance (Coss). For the highest efficiency, Silicon Carbide (SiC) MOSFETs should be considered for high-voltage stages.
Package and Thermal Management Coordination: High power density demands packages with extremely low thermal resistance and suitability for heatsink or cold plate attachment (e.g., TO-247, TO-247-4L, D2PAK). The 4-lead packages (like TO-247-4L) with a separate source sense (Kelvin connection) are preferred for critical high-frequency switches to minimize parasitic inductance and switching loss. PCB design must integrate thick copper layers and thermal vias.
Reliability and Ruggedness: Servers operate 24/7 under high load. Focus on the device's maximum junction temperature (Tj max), avalanche energy rating (EAS), body diode robustness, and long-term parameter stability under thermal cycling. Automotive-grade or equivalent high-reliability parts are recommended.
II. Scenario-Specific MOSFET Selection Strategies
The main power domains in AI liquid-cooled server clusters include high-voltage AC-DC front-end PFC/LLC, intermediate bus DC-DC conversion (48V-12V/5V), and Point-of-Load (POL) voltage regulation (VRM/VRD) for CPUs/GPUs, alongside the liquid cooling pump and fan drives. Targeted selection is required for each.
Scenario 1: High-Voltage Primary-Side Switching & PFC (650V-850V Class)
This stage handles AC-DC conversion and power factor correction, requiring high-voltage capability, fast switching, and high efficiency to reduce losses before downstream conversion.
Recommended Model: VBP165C93-4L (Single-N, 650V, 93A, TO247-4L, SiC Technology)
Parameter Advantages:
Utilizes advanced SiC technology, offering ultra-low Rds(on) of 22 mΩ (@18V), drastically reducing conduction loss compared to Si counterparts.
Extremely fast intrinsic body diode and low Qg/Coss enable high-frequency operation (>100 kHz), reducing magnetic component size and improving power density.
TO247-4L package with Kelvin source minimizes gate loop inductance, optimizing switching performance and loss.
Scenario Value:
Enables >98% efficiency in PFC and LLC stages, directly improving overall PUE.
High-frequency operation allows for compact, high-power-density power supply designs.
Superior high-temperature performance aligns well with the hot operating environment near server racks.
Scenario 2: High-Current Synchronous Rectification & DC-DC Conversion (48V-12V, VRM)
This stage demands the lowest possible conduction loss to handle currents often exceeding several hundred Amperes, especially in multi-phase VRMs for CPUs/GPUs.
Recommended Model: VBP1102N (Single-N, 100V, 72A, TO247, Trench Technology)
Parameter Advantages:
Very low Rds(on) of 18 mΩ (@10V) minimizes conduction voltage drop and I²R losses in high-current paths.
High continuous current rating (72A) suits parallel operation in multi-phase buck converters.
Standard TO247 package offers excellent thermal performance for heatsink mounting.
Scenario Value:
Ideal for synchronous rectifier in 48V-12V DC-DC converters and as low-side switches in multi-phase VRMs.
High current handling per device reduces the number of parallel components needed, simplifying design and layout.
Robust construction ensures reliability under high ripple current stress.
Scenario 3: Liquid Cooling Pump & High-Performance Fan Drive (12V/48V BLDC/PMSM)
Cooling pumps and fans are critical for thermal management. Their drivers require reliable high-side/low-side switching, fault tolerance, and efficient operation.
Recommended Model: VBM82152M (Single-P, -150V, -15A, TO220F, Trench Technology)
Parameter Advantages:
High voltage rating (-150V) provides ample margin for 48V or higher pump motor drives, handling back-EMF safely.
Low Rds(on) of 160 mΩ (@10V) for a P-channel device reduces losses in high-side configuration.
TO220F (fully insulated) package simplifies heatsink installation without isolation pads, improving thermal management and safety.
Scenario Value:
Excellent for high-side switching in H-bridge motor drive circuits, simplifying gate drive design compared to using an N-MOS with a bootstrap circuit.
The insulated package is advantageous in liquid cooling systems where condensation or accidental coolant contact is a concern, enhancing system safety and reliability.
Enables efficient and reliable speed control of pumps and fans, crucial for maintaining optimal coolant temperature.
III. Key Implementation Points for System Design
Drive Circuit Optimization:
SiC MOSFET (VBP165C93-4L): Must use dedicated, high-speed gate driver ICs with negative turn-off voltage capability to maximize switching speed, minimize loss, and prevent false triggering. Careful attention to PCB layout to minimize power loop and gate loop parasitics is paramount.
High-Current N-MOS (VBP1102N): Use drivers with strong sink/source capability (≥4A) to ensure fast switching in parallel configurations. Implement active balancing techniques when paralleling multiple devices.
High-Voltage P-MOS (VBM82152M): Can be driven by a level-shifted signal from the controller. Ensure the driver can handle the required voltage swing and provide adequate pull-up strength for fast turn-off.
Thermal Management Design:
Tiered Strategy: SiC and high-current MOSFETs must be mounted on dedicated heatsinks or cold plates. Use thermal interface materials with high conductivity.
PCB Thermal Design: For all packages, employ maximum copper pour area, multiple thermal vias under the thermal pad (for surface-mount types), and connect to internal power planes for heat spreading.
Monitoring: Implement junction temperature sensing or model-based thermal monitoring to dynamically adjust fan/pump speed or workload, preventing overtemperature.
EMC and Reliability Enhancement:
Snubber Networks: Use RC snubbers across drain-source of primary-side switches (VBP165C93-4L) to dampen high-frequency ringing and reduce EMI.
Protection Circuits: Incorporate comprehensive protection: TVS diodes for voltage clamping, accurate current sensing for overcurrent protection, and overtemperature shutdown.
Decoupling: Place high-quality, low-ESL capacitors very close to the drain-source terminals of all power MOSFETs to provide local high-frequency energy and reduce voltage spikes.
IV. Solution Value and Expansion Recommendations
Core Value:
Maximized Power Efficiency: The combination of SiC for high-voltage switching and low-Rds(on) trench MOSFETs for rectification/conversion pushes system-level efficiency beyond 96%, significantly reducing operational energy costs and cooling load.
Enhanced Power Density: High-frequency operation enabled by SiC and compact, high-performance packages allows for smaller, more powerful power supplies, freeing up valuable space within the server chassis.
Uncompromising Reliability: The selected high-voltage, high-current, and insulated package devices, combined with robust thermal and protection design, ensure continuous 24/7 operation under demanding AI workloads.
Optimization and Adjustment Recommendations:
Higher Power Scaling: For CPU/GPU VRMs exceeding 1000A, consider even lower Rds(on) devices or advanced packaging like DirectFET or PowerStage modules for ultimate current density.
Integration Path: For design simplification, consider integrated DrMOS or Smart Power Stages for POL applications, which combine MOSFETs, drivers, and protection.
Future Technology Adoption: Monitor the development of Gallium Nitride (GaN) HEMTs for even higher frequency (MHz range) operation in intermediate bus converters, enabling further size reduction.
Liquid Cooling Specifics: For pumps immersed in dielectric coolant, ensure selected MOSFET packages and associated components are compatible with the specific coolant chemistry to prevent corrosion or degradation.
The selection of power MOSFETs is a cornerstone in designing the power and thermal management systems for AI liquid-cooled server clusters. The scenario-based selection and systematic design methodology proposed herein aim to achieve the optimal balance among power density, efficiency, thermal performance, and rugged reliability. As AI computing demands escalate, the adoption of wide-bandgap semiconductors like SiC and GaN will become increasingly critical, providing the foundation for next-generation, ultra-high-efficiency data center infrastructure. In the era of AI, superior hardware design remains the bedrock of computational performance and operational sustainability.

Detailed Topology Diagrams

High-Voltage SiC PFC/LLC Primary Side Topology

graph LR subgraph "Three-Phase PFC Stage with SiC MOSFETs" AC_IN["480VAC 3-Phase"] --> RECT["Three-Phase Rectifier"] RECT --> L_PFC["PFC Boost Inductor"] L_PFC --> NODE_PFC["PFC Switching Node"] subgraph "PFC MOSFET Array" Q1["VBP165C93-4L
650V/93A SiC"] Q2["VBP165C93-4L
650V/93A SiC"] end NODE_PFC --> Q1 NODE_PFC --> Q2 Q1 --> HV_BUS["HV DC Bus (800V)"] Q2 --> HV_BUS CTRL_PFC["PFC Controller"] --> DRV_PFC["SiC Gate Driver"] DRV_PFC --> Q1 DRV_PFC --> Q2 end subgraph "LLC Resonant Stage with SiC MOSFETs" HV_BUS --> Lr["Resonant Inductor"] Lr --> Cr["Resonant Capacitor"] Cr --> XFMR_PRI["LLC Transformer Primary"] XFMR_PRI --> NODE_LLC["LLC Switching Node"] subgraph "LLC MOSFET Array" Q3["VBP165C93-4L
650V/93A SiC"] Q4["VBP165C93-4L
650V/93A SiC"] end NODE_LLC --> Q3 NODE_LLC --> Q4 Q3 --> GND Q4 --> GND CTRL_LLC["LLC Controller"] --> DRV_LLC["SiC Gate Driver"] DRV_LLC --> Q3 DRV_LLC --> Q4 end subgraph "Protection & Snubber Circuits" RCD_SNUBBER["RCD Snubber"] --> Q1 RC_SNUBBER["RC Snubber"] --> Q3 TVS_ARRAY["TVS Protection"] --> DRV_PFC TVS_ARRAY --> DRV_LLC end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q3 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Multi-Phase CPU/GPU VRM Topology with Parallel MOSFETs

graph LR subgraph "Single VRM Phase Leg" VIN["12V Input"] --> L_PHASE["Output Inductor"] L_PHASE --> VOUT["CPU/GPU Power Rail"] subgraph "High-Side Switch (Parallel)" Q_HS1["VBP1102N
100V/72A"] Q_HS2["VBP1102N
100V/72A"] end subgraph "Low-Side Switch (Parallel)" Q_LS1["VBP1102N
100V/72A"] Q_LS2["VBP1102N
100V/72A"] end VIN --> Q_HS1 VIN --> Q_HS2 Q_HS1 --> SW_NODE["Phase Node"] Q_HS2 --> SW_NODE SW_NODE --> L_PHASE SW_NODE --> Q_LS1 SW_NODE --> Q_LS2 Q_LS1 --> GND Q_LS2 --> GND C_OUT["Output Capacitors"] --> VOUT C_OUT --> GND end subgraph "Multi-Phase Interleaving" PHASE_CONTROLLER["Multi-Phase Controller"] --> PHASE1["Phase 1 Driver"] PHASE_CONTROLLER --> PHASE2["Phase 2 Driver"] PHASE_CONTROLLER --> PHASE3["Phase 3 Driver"] PHASE_CONTROLLER --> PHASE4["Phase 4 Driver"] PHASE1 --> HS_DRV1["High-Side Driver"] PHASE1 --> LS_DRV1["Low-Side Driver"] PHASE2 --> HS_DRV2["High-Side Driver"] PHASE2 --> LS_DRV2["Low-Side Driver"] HS_DRV1 --> Q_HS1 LS_DRV1 --> Q_LS1 HS_DRV2 --> Q_HS2 LS_DRV2 --> Q_LS2 end subgraph "Current Balancing & Monitoring" CURRENT_SENSE["Current Sense Amplifier"] --> SW_NODE CURRENT_SENSE --> BALANCE_CTRL["Balance Controller"] BALANCE_CTRL --> PHASE_CONTROLLER TEMP_SENSE["Temperature Sensor"] --> BALANCE_CTRL end style Q_HS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_LS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Liquid Cooling Pump & Fan Drive Topology

graph LR subgraph "Liquid Cooling Pump H-Bridge Drive" PUMP_MCU["Pump Controller"] --> PUMP_DRIVER["Gate Driver IC"] subgraph "H-Bridge MOSFET Configuration" Q_HS1_P["VBM82152M
-150V/-15A (P-MOS)"] Q_LS1_N["VBP1102N
100V/72A"] Q_HS2_P["VBM82152M
-150V/-15A (P-MOS)"] Q_LS2_N["VBP1102N
100V/72A"] end PUMP_DRIVER --> Q_HS1_P PUMP_DRIVER --> Q_LS1_N PUMP_DRIVER --> Q_HS2_P PUMP_DRIVER --> Q_LS2_N VCC_48V["48V DC Bus"] --> Q_HS1_P VCC_48V --> Q_HS2_P Q_HS1_P --> NODE_A["Phase A"] Q_LS1_N --> NODE_A Q_HS2_P --> NODE_B["Phase B"] Q_LS2_N --> NODE_B NODE_A --> PUMP_WINDING["Pump Motor Winding"] NODE_B --> PUMP_WINDING Q_LS1_N --> GND Q_LS2_N --> GND end subgraph "Fan Array Drive Circuit" FAN_MCU["Fan Controller"] --> FAN_DRIVER["Gate Driver Array"] subgraph "Fan Channel MOSFETs" FAN_HS["VBM82152M x4
(P-MOS High-Side)"] FAN_LS["VBP1102N x4
(N-MOS Low-Side)"] end FAN_DRIVER --> FAN_HS FAN_DRIVER --> FAN_LS VCC_12V["12V DC"] --> FAN_HS FAN_HS --> FAN_NODE["Fan Power Node"] FAN_LS --> FAN_NODE FAN_NODE --> FAN_MOTOR["Brushless Fan Motor"] FAN_LS --> GND end subgraph "Thermal Feedback & Control" PUMP_TEMP["Pump Temperature"] --> PUMP_MCU FLOW_SENSOR["Coolant Flow Sensor"] --> PUMP_MCU FAN_TEMP["Ambient Temperature"] --> FAN_MCU PUMP_MCU --> SPEED_CONTROL["PWM Speed Control"] FAN_MCU --> FAN_SPEED["Fan Speed Control"] end subgraph "Protection Circuits" OCP_PUMP["Pump Over-Current"] --> FAULT_LOGIC["Fault Logic"] OTP_PUMP["Pump Over-Temp"] --> FAULT_LOGIC OCP_FAN["Fan Over-Current"] --> FAULT_LOGIC FAULT_LOGIC --> SHUTDOWN["System Shutdown"] SHUTDOWN --> PUMP_DRIVER SHUTDOWN --> FAN_DRIVER end style Q_HS1_P fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_LS1_N fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style FAN_HS fill:#fff3e0,stroke:#ff9800,stroke-width:2px style FAN_LS fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
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