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MOSFET Selection Strategy and Device Adaptation Handbook for AI Server Energy-Saving Control Systems with High-Power-Density and Efficiency Requirements
AI Server Energy-Saving Control System MOSFET Topology Diagram

AI Server Energy-Saving Control System Overall Topology Diagram

graph LR %% Main Power Input Section subgraph "Primary Power Input & Distribution" PSU["Server PSU
48V/12V Output"] --> INPUT_FILTER["Input Filter & Protection"] INPUT_FILTER --> BUS_48V["48V Intermediate Bus"] INPUT_FILTER --> BUS_12V["12V Distribution Bus"] BUS_48V --> IBC["Intermediate Bus Converter"] end %% High-Current DC-DC Conversion & VRM (Scenario 1) subgraph "High-Current DC-DC & VRM (Power Core)" IBC --> VRM_INPUT["VRM Input 12V"] subgraph "Multi-Phase VRM for CPU/GPU" PHASE1["Phase 1
VBGMB1103 100V/80A"] PHASE2["Phase 2
VBGMB1103 100V/80A"] PHASE3["Phase 3
VBGMB1103 100V/80A"] PHASE4["Phase 4
VBGMB1103 100V/80A"] end VRM_INPUT --> PHASE1 VRM_INPUT --> PHASE2 VRM_INPUT --> PHASE3 VRM_INPUT --> PHASE4 PHASE1 --> CPU_VRM["CPU VRM Output
0.8-1.5V"] PHASE2 --> CPU_VRM PHASE3 --> GPU_VRM["GPU VRM Output
0.8-1.5V"] PHASE4 --> GPU_VRM CPU_VRM --> CPU_LOAD["CPU Core Load"] GPU_VRM --> GPU_LOAD["GPU Core Load"] end %% Power Sequencing & High-Side Switching (Scenario 2) subgraph "Power Sequencing & Load Switching (Management)" SEQ_CONTROLLER["Sequencing Controller"] --> SW_MEM["VBA2311A
Memory Power Switch"] SEQ_CONTROLLER --> SW_SSD["VBA2311A
SSD Backplane Switch"] SEQ_CONTROLLER --> SW_EXP["VBA2311A
Expansion Card Switch"] BUS_12V --> SW_MEM BUS_12V --> SW_SSD BUS_12V --> SW_EXP SW_MEM --> MEM_POWER["Memory Module Power"] SW_SSD --> SSD_POWER["SSD Backplane Power"] SW_EXP --> EXP_POWER["PCIe Card Power"] end %% Low-Power Auxiliary & Fan Control (Scenario 3) subgraph "Auxiliary Power & Cooling Control (Support)" MCU["Server Management MCU"] --> POL_CTRL["POL Controller"] MCU --> FAN_CTRL["Fan Controller"] subgraph "Point-of-Load Switching" POL_3V3["VBK7695
3.3V Rail Switch"] POL_5V["VBK7695
5V Rail Switch"] POL_SENSOR["VBK7695
Sensor Power Switch"] end subgraph "Cooling Fan PWM Control" FAN1_CTRL["VBK7695
CPU Fan PWM"] FAN2_CTRL["VBK7695
GPU Fan PWM"] FAN3_CTRL["VBK7695
System Fan PWM"] end POL_CTRL --> POL_3V3 POL_CTRL --> POL_5V POL_CTRL --> POL_SENSOR FAN_CTRL --> FAN1_CTRL FAN_CTRL --> FAN2_CTRL FAN_CTRL --> FAN3_CTRL POL_3V3 --> LOGIC_POWER["3.3V Logic Power"] POL_5V --> PERIPHERAL_POWER["5V Peripheral Power"] POL_SENSOR --> SENSOR_POWER["Sensor Power Rail"] FAN1_CTRL --> CPU_FAN["CPU Cooling Fan"] FAN2_CTRL --> GPU_FAN["GPU Cooling Fan"] FAN3_CTRL --> SYS_FAN["System Cooling Fan"] end %% Thermal Management System subgraph "Tiered Thermal Management" COOLING_LEVEL1["Level 1: Cold Plate Cooling
VRM MOSFETs"] COOLING_LEVEL2["Level 2: Heatsink + Airflow
Load Switches"] COOLING_LEVEL3["Level 3: PCB Copper Pour
POL Switches"] COOLING_LEVEL1 --> PHASE1 COOLING_LEVEL1 --> PHASE2 COOLING_LEVEL2 --> SW_MEM COOLING_LEVEL2 --> SW_SSD COOLING_LEVEL3 --> POL_3V3 COOLING_LEVEL3 --> FAN1_CTRL end %% Protection & Monitoring subgraph "Protection & Monitoring Circuits" OC_PROTECTION["Overcurrent Protection"] --> PHASE1 OT_PROTECTION["Overtemperature Protection"] --> PHASE2 UVLO["Undervoltage Lockout"] --> SEQ_CONTROLLER OVP["Overvoltage Protection"] --> POL_CTRL CURRENT_SENSE["Current Sense Amplifiers"] VOLTAGE_SENSE["Voltage Sense Networks"] TEMP_SENSORS["Temperature Sensors
NTC/RTD"] CURRENT_SENSE --> MCU VOLTAGE_SENSE --> MCU TEMP_SENSORS --> MCU end %% Communication & Control MCU --> PMBUS["PMBus/I2C Interface"] MCU --> BMC["BMC Communication"] MCU --> CLOUD_MGMT["Cloud Management Interface"] %% Style Definitions style PHASE1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SW_MEM fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style POL_3V3 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the rapid evolution of AI computing and the urgent need for data center sustainability, AI server energy-saving control systems have become critical for managing power integrity and thermal performance. The power delivery and management systems, serving as the "vascular and neural network" of the server, provide precise power conversion, sequencing, and switching for key loads such as CPU/GPU VRMs, high-speed fans, and auxiliary DC-DC rails. The selection of power MOSFETs directly determines system conversion efficiency, thermal footprint, power density, and reliability. Addressing the stringent demands of AI servers for extreme efficiency, high heat flux management, and precise control, this article develops a practical and optimized MOSFET selection strategy through scenario-based adaptation.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Three-Dimensional Optimization for High Density
MOSFET selection requires coordinated optimization across three dimensions—loss, thermal, and voltage—ensuring robust operation under high ambient temperatures and dynamic loads:
Prioritize Ultra-Low Loss: For CPU/GPU VRMs and bulk DC-DC converters, prioritize devices with extremely low Rds(on) (minimizing conduction loss) and low Qg/Qoss (minimizing switching loss at high frequency), crucial for achieving >96% peak efficiency and reducing coolant burden.
Thermal and Package Co-design: Choose packages (e.g., TO220F, TO263) with low thermal resistance for high-power stages, enabling effective attachment to heatsinks or cold plates. For point-of-load (POL) switches, select compact packages (e.g., SOP8, SC70-6) to save board area in congested spaces.
Voltage and Reliability Margins: For 12V/48V intermediate bus architectures, ensure sufficient voltage derating (≥60% margin) to handle transient spikes. Devices must offer high junction temperature capability (Tj max ≥ 150°C) and robust gate oxide for 24/7 mission-critical operation.
(B) Scenario Adaptation Logic: Categorization by Power Path and Function
Divide server power paths into three core control scenarios: First, High-Current DC-DC Conversion & VRM (Power Core), requiring highest efficiency and current handling. Second, Power Sequencing & High-Side Switching (Management & Safety), requiring compact solutions for board-level power control. Third, Low-Power Auxiliary Rail & Fan Control (Support & Cooling), requiring space-efficient switches for intelligent power-gating and speed control.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: High-Current DC-DC Conversion & VRM – Power Core Device
Multi-phase VRMs and 48V-to-12V/5V intermediate bus converters (IBCs) require handling very high continuous and transient currents with minimal loss.
Recommended Model: VBGMB1103 (Single-N, 100V, 80A, TO220F)
Parameter Advantages: Advanced SGT technology achieves an ultra-low Rds(on) of 2.9mΩ at 10V. High continuous current of 80A suits multi-phase buck converters for GPU power or high-power IBCs. TO220F package offers excellent thermal performance for heatsink mounting.
Adaptation Value: Drastically reduces conduction loss in critical power paths. In a 48V-12V IBC phase handling 30A, device conduction loss is only ~2.6W, enabling system efficiency >97%. Supports high-frequency multiphase operation, improving transient response and reducing input/output capacitance needs.
Selection Notes: Verify phase current and thermal design. Ensure gate driver capability (≥3A peak) to switch low Qg device efficiently. Implement precise current sharing and temperature monitoring.
(B) Scenario 2: Power Sequencing & High-Side Switching – Management & Safety Device
Power sequencing, hot-swap, and high-side load switching for various rails (e.g., 12V, 5V) require compact, efficient P-Channel or high-voltage N-Channel solutions for safe power-up/down sequences.
Recommended Model: VBA2311A (Single-P, -30V, -12.5A, SOP8)
Parameter Advantages: P-Channel configuration simplifies high-side drive. Very low Rds(on) of 11mΩ (10V) minimizes voltage drop. SOP8 package saves significant PCB area compared to discrete solutions. -30V rating is ideal for 12V bus control with ample margin.
Adaptation Value: Enables intelligent, sequenced power-up for SSD backplanes, memory modules, or expansion cards, preventing inrush currents. Low on-resistance ensures minimal power loss on the critical power path. Saves layout space for dense server motherboard designs.
Selection Notes: Use with an NPN transistor or dedicated high-side driver for gate control. Add RC snubber if switching inductive loads. Ensure current is within safe operating area (SOA) during hot-swap events.
(C) Scenario 3: Low-Power Auxiliary Rail & Fan Control – Support & Cooling Device
Controlling low-power rails (3.3V, 5V) for sensors, management controllers, and PWM control of high-speed cooling fans requires small, logic-level devices.
Recommended Model: VBK7695 (Single-N, 60V, 2.5A, SC70-6)
Parameter Advantages: Ultra-compact SC70-6 package minimizes footprint. Low Vth of 1.7V allows direct drive by 3.3V MCU GPIO. Good Rds(on) (75mΩ @10V) for its size. 60V rating provides strong margin for 12V/24V fan PWM circuits.
Adaptation Value: Enables fine-grained power-gating of peripheral components, reducing standby power. Used as a PWM switch for 4-wire fans, allowing dynamic speed control for acoustic and thermal optimization. Its tiny size allows placement near the load.
Selection Notes: Ensure gate drive strength is adequate for target switching frequency. Add a small gate resistor to dampen ringing. For fan control, include a freewheeling diode path.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBGMB1103: Pair with high-current, high-speed multi-phase PWM controllers and drivers (e.g., Infineon XDPE, TI PMBus controllers). Minimize power loop inductance with a tight layout.
VBA2311A: Implement a simple NPN level translator or use a dedicated load switch IC with integrated control for sequencing. A pull-up resistor on the gate ensures default-off state.
VBK7695: Can be driven directly from MCU but include a series resistor (e.g., 10Ω). For higher frequency PWM, a dedicated gate driver buffer may be beneficial.
(B) Thermal Management Design: Tiered and Direct Cooling
VBGMB1103: Requires dedicated heatsink or thermal interface to server's cooling solution (cold plate/heat sink). Use thermal pads and ensure mounting pressure.
VBA2311A: A modest copper pour under the SOP8 package is typically sufficient for its power level. Ensure general airflow over the board.
VBK7695: Local copper heat spreading is adequate. Its low power dissipation minimizes thermal impact.
Overall: Place high-power MOSFETs in the primary airflow path or directly on cold plates. Monitor junction temperature via associated controller ICs.
(C) EMC and Reliability Assurance
EMC Suppression:
VBGMB1103: Use low-ESR ceramic capacitors very close to drain and source pins. Optimize snubber networks for high-frequency switching nodes in VRMs.
VBA2311A/VBK7695: Add ferrite beads in series with the switched load for noise filtering. Ensure clean, isolated ground paths for sensitive analog controls.
Reliability Protection:
Derating Design: Derate voltage by 50% and current by at least 30% from absolute maximum ratings at maximum operating temperature.
Overcurrent/Overtemperature Protection: Utilize the integrated protection features of server PWM controllers for VRM stages. For load switches, implement current limiting or use ICs with built-in fault protection.
ESD/Surge Protection: Apply TVS diodes on all external connections (fan headers, power inputs). Use gate-source resistors and TVS for GPIO-connected MOSFETs (VBK7695).
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Power Density and Efficiency: The selected devices optimize the efficiency of every power stage, reducing total power loss and enabling higher compute density within the same thermal design power (TDP) envelope.
Enhanced System Reliability and Manageability: Enables precise power sequencing and intelligent control of auxiliary loads, improving system stability and facilitating advanced power capping/management features.
Optimized Cost-Structure for Scale: Leverages mature, high-volume MOSFET technologies, providing the optimal balance of performance and cost for large-scale server deployment.
(B) Optimization Suggestions
Power Scaling: For even higher current VRMs (>100A per phase), consider parallel operation of VBGMB1103 or evaluate higher current variants. For 48V direct conversion, consider VBN1154N (150V).
Integration Upgrade: For advanced power sequencing, use integrated load switches with I2C/PMBus interface instead of discrete VBA2311A. For fan fail detection, consider devices with integrated sense FET.
Specialized Scenarios: For redundant power supply (OR-ing) applications, use VBA2311A for its low reverse recovery charge. For harsh environments, select automotive-grade equivalents.
Advanced Cooling Control: Pair VBK7695 with temperature sensors and MCU to create closed-loop, adaptive fan speed profiles, further optimizing acoustic noise and energy use.
Conclusion
Strategic MOSFET selection is central to achieving the high efficiency, power density, and intelligent control required in next-generation AI servers. This scenario-based scheme provides targeted technical guidance for power system architects through precise load matching and robust system-level design. Future exploration should focus on the integration of Wide Bandgap (SiC/GaN) devices for the highest efficiency conversion stages and the adoption of fully integrated smart power stages (IPMs) to further simplify design and enhance monitoring capabilities, paving the way for more sustainable and powerful AI computing infrastructure.

Detailed MOSFET Application Topology Diagrams

High-Current VRM & DC-DC Conversion Topology (Scenario 1)

graph LR subgraph "Multi-Phase Buck Converter for CPU/GPU" INPUT_12V["12V Input Bus"] --> INDUCTOR["Buck Inductor"] INDUCTOR --> SWITCHING_NODE["Switching Node"] subgraph "High-Side & Low-Side MOSFET Pair" HS_MOSFET["VBGMB1103
High-Side Switch"] LS_MOSFET["VBGMB1103
Low-Side Switch"] end SWITCHING_NODE --> HS_MOSFET SWITCHING_NODE --> LS_MOSFET HS_MOSFET --> INPUT_12V LS_MOSFET --> GND["Power Ground"] SWITCHING_NODE --> OUTPUT_FILTER["Output LC Filter"] OUTPUT_FILTER --> VOUT["0.8-1.5V Output"] subgraph "Control & Driver" PWM_CONTROLLER["Multi-Phase PWM Controller"] GATE_DRIVER["High-Current Gate Driver
3A Peak"] end PWM_CONTROLLER --> GATE_DRIVER GATE_DRIVER --> HS_MOSFET GATE_DRIVER --> LS_MOSFET VOUT -->|Voltage Feedback| PWM_CONTROLLER end subgraph "Thermal Management" COLD_PLATE["Liquid Cold Plate"] --> HS_MOSFET COLD_PLATE --> LS_MOSFET HEATSINK["Aluminum Heatsink"] --> COLD_PLATE FAN["Cooling Fan"] --> HEATSINK TEMP_SENSOR["Temperature Sensor"] --> PWM_CONTROLLER end style HS_MOSFET fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style LS_MOSFET fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Power Sequencing & High-Side Switching Topology (Scenario 2)

graph LR subgraph "Sequenced Power-Up Control" SEQ_CTRL["Sequencing Controller"] --> CHANNEL1["Channel 1 Enable"] SEQ_CTRL --> CHANNEL2["Channel 2 Enable"] SEQ_CTRL --> CHANNEL3["Channel 3 Enable"] subgraph "High-Side P-MOSFET Switches" SWITCH1["VBA2311A
Memory Power
-30V/-12.5A"] SWITCH2["VBA2311A
SSD Power
-30V/-12.5A"] SWITCH3["VBA2311A
PCIe Power
-30V/-12.5A"] end CHANNEL1 --> GATE_DRIVE1["Level Shifter"] CHANNEL2 --> GATE_DRIVE2["Level Shifter"] CHANNEL3 --> GATE_DRIVE3["Level Shifter"] GATE_DRIVE1 --> SWITCH1 GATE_DRIVE2 --> SWITCH2 GATE_DRIVE3 --> SWITCH3 POWER_12V["12V Power Bus"] --> SWITCH1 POWER_12V --> SWITCH2 POWER_12V --> SWITCH3 SWITCH1 --> MEM_OUT["Memory Module Power"] SWITCH2 --> SSD_OUT["SSD Backplane Power"] SWITCH3 --> PCIE_OUT["PCIe Card Power"] end subgraph "Inrush Current Protection" CURRENT_LIMIT["Current Limit Circuit"] --> SWITCH1 SOFT_START["Soft-Start Control"] --> GATE_DRIVE1 RC_SNUBBER["RC Snubber Network"] --> SWITCH1 end subgraph "Status Monitoring" POWER_GOOD["Power Good Signal"] --> SEQ_CTRL CURRENT_SENSE["Current Sense"] --> SEQ_CTRL VOLTAGE_SENSE["Voltage Sense"] --> SEQ_CTRL end style SWITCH1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SWITCH2 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Auxiliary Power & Intelligent Fan Control Topology (Scenario 3)

graph LR subgraph "Point-of-Load Power Gating" MCU_GPIO["MCU GPIO 3.3V"] --> POL_ENABLE["POL Enable"] subgraph "Logic-Level N-MOSFET Switches" POL_3V3["VBK7695
3.3V Rail
60V/2.5A"] POL_5V["VBK7695
5V Rail
60V/2.5A"] POL_SENSOR["VBK7695
Sensor Power
60V/2.5A"] end POL_ENABLE --> POL_3V3 POL_ENABLE --> POL_5V POL_ENABLE --> POL_SENSOR AUX_3V3["3.3V Auxiliary"] --> POL_3V3 AUX_5V["5V Auxiliary"] --> POL_5V AUX_SENSOR["Sensor Power"] --> POL_SENSOR POL_3V3 --> LOGIC_LOAD["Logic Circuits"] POL_5V --> PERIPHERAL_LOAD["Peripherals"] POL_SENSOR --> SENSOR_LOAD["Temperature Sensors"] end subgraph "Intelligent Fan Speed Control" FAN_CONTROLLER["Fan Controller"] --> PWM_GEN["PWM Generator"] subgraph "Fan PWM MOSFET Drivers" FAN1_PWM["VBK7695
CPU Fan Control"] FAN2_PWM["VBK7695
GPU Fan Control"] FAN3_PWM["VBK7695
System Fan Control"] end PWM_GEN --> FAN1_PWM PWM_GEN --> FAN2_PWM PWM_GEN --> FAN3_PWM FAN_POWER["12V Fan Power"] --> FAN1_PWM FAN_POWER --> FAN2_PWM FAN_POWER --> FAN3_PWM FAN1_PWM --> CPU_FAN_OUT["CPU Fan"] FAN2_PWM --> GPU_FAN_OUT["GPU Fan"] FAN3_PWM --> SYS_FAN_OUT["System Fan"] end subgraph "Thermal Feedback Loop" TEMP_CPU["CPU Temp Sensor"] --> FAN_CONTROLLER TEMP_GPU["GPU Temp Sensor"] --> FAN_CONTROLLER TEMP_SYS["System Temp Sensor"] --> FAN_CONTROLLER FAN_TACH["Fan Tachometer"] --> FAN_CONTROLLER end subgraph "EMC & Protection" GATE_RES["10Ω Gate Resistor"] --> POL_3V3 FLYWHEEL_DIODE["Flywheel Diode"] --> FAN1_PWM TVS_ARRAY["TVS Protection"] --> FAN_POWER end style POL_3V3 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style FAN1_PWM fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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