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Power MOSFET Selection Solution for AI Data Backup All-in-One Systems – Design Guide for High-Efficiency, High-Reliability, and Compact Drive Systems
AI Data Backup All-in-One System Power MOSFET Topology Diagram

AI Data Backup All-in-One System Overall Power Topology Diagram

graph LR %% Main Power Input & Distribution Section subgraph "Main Power Input & Primary Distribution" AC_IN["AC Input
90-264VAC"] --> PSU["Server PSU
12V/48V Output"] PSU --> DC_BUS_12V["12V DC Power Bus"] PSU --> DC_BUS_48V["48V DC Power Bus"] DC_BUS_12V --> ORING_CONTROLLER["OR-ing Controller"] DC_BUS_48V --> ORING_CONTROLLER ORING_CONTROLLER --> MAIN_BUS["Main Power Bus"] end %% High-Current DC-DC Conversion Section subgraph "High-Current DC-DC Conversion & CPU/ASIC Power" MAIN_BUS --> BUCK_CONV["Synchronous Buck Converter"] subgraph "Primary Power MOSFET Array" Q_HIGH1["VBM1303A
30V/160A"] Q_LOW1["VBM1303A
30V/160A"] Q_HIGH2["VBM1303A
30V/160A"] Q_LOW2["VBM1303A
30V/160A"] end BUCK_CONV --> Q_HIGH1 Q_HIGH1 --> SW_NODE["Switching Node"] SW_NODE --> Q_LOW1 Q_LOW1 --> GND_POWER["Power Ground"] SW_NODE --> OUTPUT_FILTER1["Output LC Filter"] OUTPUT_FILTER1 --> CPU_VCC["CPU/ASIC Core Voltage
(0.8-1.2V/100A+)"] BUCK_CONV --> Q_HIGH2 Q_HIGH2 --> SW_NODE2["Switching Node"] SW_NODE2 --> Q_LOW2 Q_LOW2 --> GND_POWER SW_NODE2 --> OUTPUT_FILTER2["Output LC Filter"] OUTPUT_FILTER2 --> MEMORY_VCC["Memory/IO Voltage
(1.8-3.3V)"] end %% Intelligent Cooling System Section subgraph "Intelligent Cooling System Drive" subgraph "Fan/Pump Control MOSFETs" FAN_MOS1["VBE2305
-30V/-100A"] FAN_MOS2["VBE2305
-30V/-100A"] PUMP_MOS["VBE2305
-30V/-100A"] end DC_BUS_12V --> FAN_MOS1 DC_BUS_12V --> FAN_MOS2 DC_BUS_12V --> PUMP_MOS FAN_MOS1 --> FAN_ARRAY["High-Speed Fan Array"] FAN_MOS2 --> FAN_ARRAY PUMP_MOS --> LIQUID_PUMP["Liquid Cooling Pump"] end %% Auxiliary Power Management Section subgraph "Auxiliary Power Management & Peripheral Switching" MCU["System Management MCU"] --> GPIO_CONTROL["GPIO Control Signals"] subgraph "Load Switch MOSFET Array" SSD_SWITCH["VBJ1311
30V/13A"] SENSOR_SWITCH["VBJ1311
30V/13A"] COMM_SWITCH["VBJ1311
30V/13A"] BACKPLANE_SWITCH["VBJ1311
30V/13A"] end DC_BUS_5V["5V Auxiliary Bus"] --> SSD_SWITCH DC_BUS_5V --> SENSOR_SWITCH DC_BUS_3V3["3.3V Auxiliary Bus"] --> COMM_SWITCH DC_BUS_3V3 --> BACKPLANE_SWITCH SSD_SWITCH --> SSD_BACKPLANE["SSD Backplane Power"] SENSOR_SWITCH --> SENSORS["Temperature/Sensors"] COMM_SWITCH --> COM_MODULE["Communication Module"] BACKPLANE_SWITCH --> EXPANSION["Expansion Card Power"] end %% Protection & Monitoring Section subgraph "System Protection & Monitoring" subgraph "Current Sensing & Protection" CURRENT_SENSE1["High-Precision Current Sense"] CURRENT_SENSE2["High-Precision Current Sense"] OVERCURRENT_DETECT["Overcurrent Detector"] end subgraph "Thermal Management" TEMP_SENSORS["Multiple NTC Sensors"] THERMAL_CONTROLLER["Thermal Management IC"] end subgraph "EMC & Transient Protection" TVS_ARRAY["TVS Diode Array"] SNUBBER_CIRCUITS["RC Snubber Networks"] ESD_PROTECTION["ESD Protection"] end CURRENT_SENSE1 --> CPU_VCC CURRENT_SENSE2 --> MAIN_BUS TEMP_SENSORS --> THERMAL_CONTROLLER THERMAL_CONTROLLER --> MCU TVS_ARRAY --> DC_BUS_12V TVS_ARRAY --> DC_BUS_48V SNUBBER_CIRCUITS --> Q_HIGH1 ESD_PROTECTION --> GPIO_CONTROL end %% System Interfaces subgraph "System Interfaces" MCU --> I2C_BUS["I2C/SMBus"] MCU --> PMBUS["PMBus Interface"] MCU --> ALERT_SIGNALS["Fault Alert Signals"] I2C_BUS --> PSU PMBUS --> PSU ALERT_SIGNALS --> LED_INDICATORS["Status LEDs"] end %% Style Definitions style Q_HIGH1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LOW1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style FAN_MOS1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SSD_SWITCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the exponential growth of data and the critical need for uninterrupted operation, AI data backup all-in-one systems have become essential for modern data infrastructure. Their power delivery, cooling, and management circuits, serving as the backbone for stability and efficiency, directly determine the system's data integrity, operational reliability, power density, and thermal performance. The power MOSFET, as a key switching component, significantly impacts system efficiency, thermal management, electromagnetic compatibility, and long-term durability through its selection. Addressing the high-availability, 24/7 operation, and stringent thermal constraints of AI backup appliances, this article proposes a complete, actionable power MOSFET selection and design implementation plan with a scenario-oriented and systematic approach.
I. Overall Selection Principles: System Compatibility and Balanced Design
MOSFET selection must achieve an optimal balance between electrical performance, thermal characteristics, package size, and reliability, tailored to the specific demands of server-grade hardware.
Voltage and Current Margin Design: Based on typical system voltages (12V, 48V), select MOSFETs with a voltage rating margin ≥50% to handle bus transients and spikes. The continuous operating current should not exceed 60-70% of the device's rated current to ensure longevity under peak computational or backup loads.
Low Loss Priority: Power loss directly impacts energy efficiency (PUE) and thermal dissipation. Prioritize devices with low on-resistance (Rds(on)) to minimize conduction loss. For switching regulators, also consider gate charge (Q_g) and output capacitance (Coss) to reduce dynamic losses and enable higher frequency, compact designs.
Package and Thermal Coordination: Select packages based on power level and thermal design constraints. High-power paths require packages with very low thermal resistance (e.g., TO-263, TO-220). For space-constrained, high-density boards, consider advanced packages like DFN. PCB copper area and heatsinking are integral to the selection process.
Reliability and Lifespan: For 24/7 data center environments, focus on the device's operational junction temperature range, long-term parameter stability, and ruggedness against electrical stress to match mission-critical reliability targets.
II. Scenario-Specific MOSFET Selection Strategies
The main electrical loads within an AI backup appliance can be categorized into primary power conversion, cooling system drive, and auxiliary/management power distribution.
Scenario 1: High-Current DC-DC Power Conversion & Distribution (Primary 12V/48V Paths)
This scenario involves the main board power delivery and high-current backup power paths, requiring extremely low loss and high current capability.
Recommended Model: VBM1303A (Single-N, 30V, 160A, TO-220)
Parameter Advantages:
Exceptionally low Rds(on) of 3 mΩ (@10 V), minimizing conduction loss in high-current paths.
Very high continuous current rating of 160A, suitable for primary power stages and OR-ing circuits.
TO-220 package facilitates robust mechanical mounting to heatsinks for optimal thermal management.
Scenario Value:
Ideal for synchronous buck converters for CPU/ASIC core voltages or high-current load switches, maximizing conversion efficiency (>95%).
High current handling supports redundant power supply designs and surge currents during drive array activation.
Scenario 2: Intelligent Cooling Fan Drive (High-Speed Blowers or Pump Control)
Cooling is critical for AI hardware. Fan drives require efficient PWM control, reliability, and moderate current handling for variable speed operation.
Recommended Model: VBE2305 (Single-P, -30V, -100A, TO-252)
Parameter Advantages:
Low Rds(on) of 5 mΩ (@10 V) ensures minimal voltage drop and heat generation in the drive path.
High current rating (-100A) provides ample margin for fan startup inrush currents.
P-Channel configuration simplifies high-side drive for fan arrays with common positive rail.
Scenario Value:
Enables efficient, PWM-based speed control for cooling systems, allowing dynamic thermal management based on AI workload.
TO-252 (D2PAK) package offers a good balance of power handling and PCB footprint for multi-fan controller boards.
Scenario 3: Auxiliary Power Management & Peripheral Switching (Sensors, Comm., SSD Backplane Power)
These are numerous lower-power rails requiring compact, efficient switching for power gating and voltage regulation, often directly MCU-controlled.
Recommended Model: VBJ1311 (Single-N, 30V, 13A, SOT-223)
Parameter Advantages:
Low Rds(on) of 8 mΩ (@10 V) for high efficiency even in low-voltage pathways.
Low gate threshold (Vth ~1.7V) allows direct drive from 3.3V/5V system management controllers.
SOT-223 package provides a compact footprint with superior thermal performance compared to smaller SOT packages.
Scenario Value:
Perfect for point-of-load (PoL) switches, SSD backplane power control, and sensor module power cycling to minimize standby leakage.
Can be used in synchronous rectification stages of low-power DC-DC converters, improving overall system efficiency.
III. Key Implementation Points for System Design
Drive Circuit Optimization:
For VBM1303A, use dedicated gate driver ICs with strong sink/source capability to minimize switching losses in high-frequency converters.
For VBE2305 as a high-side switch, implement a proper level-shifted gate driver (e.g., bootstrap circuit or dedicated high-side driver).
For VBJ1311 driven directly by an MCU, include a series gate resistor (~10-100Ω) and consider a pull-down resistor for defined off-state.
Thermal Management Design:
Implement a tiered strategy: attach VBM1303A to a dedicated heatsink; use generous PCB copper pours for VBE2305; natural convection via copper is sufficient for VBJ1311.
Ensure proper airflow across all power components as part of the system cooling plan.
EMC and Reliability Enhancement:
Use snubber circuits or small drain-source capacitors for VBM1303A in switching applications to dampen voltage ringing.
Integrate TVS diodes on gate pins for ESD protection, especially for VBJ1311 connected to external management interfaces.
Implement overcurrent protection using sense resistors or eFuse controllers for all critical power paths.
IV. Solution Value and Expansion Recommendations
Core Value:
Maximized Power Integrity & Efficiency: The combination of ultra-low Rds(on) devices ensures minimal voltage sag and power loss across critical paths, improving overall system PUE.
Enhanced System Reliability: High-current margins and robust package selections ensure stable operation under continuous and cyclical AI workloads.
Optimized Thermal & Spatial Profile: The selected packages align with high-density layout requirements while providing clear thermal upgrade paths.
Optimization and Adjustment Recommendations:
Higher Voltage Needs: For 48V or higher intermediate bus applications, consider VBGL1108 (100V, 78A, SGT) for its excellent Rds(on) at higher voltage ratings.
Space-Constrained High Power: For very compact, high-current Point-of-Load designs, VBQA2309 (DFN8, -60A) offers an excellent power density solution.
Advanced Integration: For multi-channel fan control or complex power sequencing, explore multi-MOSFET array packages or integrated power stage modules.
The strategic selection of power MOSFETs is a cornerstone in designing reliable and efficient AI data backup all-in-one systems. The scenario-based selection methodology outlined here aims to achieve the optimal balance between power density, thermal performance, and unwavering reliability. As AI workloads and power demands evolve, future designs may incorporate wide-bandgap devices (SiC, GaN) for the highest efficiency power conversion stages, paving the way for next-generation, hyper-scale data storage solutions.

Detailed Topology Diagrams

High-Current DC-DC Conversion & CPU Power Topology Detail

graph LR subgraph "Multi-Phase Synchronous Buck Converter" VIN["12V/48V Input"] --> PHASE1["Phase 1"] VIN --> PHASE2["Phase 2"] VIN --> PHASE3["Phase 3"] VIN --> PHASE4["Phase 4"] subgraph PHASE1 ["Phase 1 Circuit"] P1_HIGH["VBM1303A
High-Side"] P1_LOW["VBM1303A
Low-Side"] P1_DRIVER["Gate Driver"] P1_INDUCTOR["Power Inductor"] end subgraph PHASE2 ["Phase 2 Circuit"] P2_HIGH["VBM1303A
High-Side"] P2_LOW["VBM1303A
Low-Side"] P2_DRIVER["Gate Driver"] P2_INDUCTOR["Power Inductor"] end P1_DRIVER --> P1_HIGH P1_DRIVER --> P1_LOW P2_DRIVER --> P2_HIGH P2_DRIVER --> P2_LOW P1_HIGH --> P1_SW["SW Node"] P1_LOW --> GND1[GND] P2_HIGH --> P2_SW["SW Node"] P2_LOW --> GND2[GND] P1_SW --> P1_INDUCTOR P2_SW --> P2_INDUCTOR P1_INDUCTOR --> OUTPUT_CAPS["Output Capacitors"] P2_INDUCTOR --> OUTPUT_CAPS OUTPUT_CAPS --> VOUT["CPU Core Voltage
0.8-1.2V"] end subgraph "Controller & Compensation" CONTROLLER["Multi-Phase Buck Controller"] COMPENSATION["Compensation Network"] CURRENT_BALANCE["Current Balancing"] CONTROLLER --> P1_DRIVER CONTROLLER --> P2_DRIVER CONTROLLER --> CURRENT_BALANCE VOUT --> FB["Voltage Feedback"] FB --> COMPENSATION COMPENSATION --> CONTROLLER end subgraph "Monitoring & Protection" CURRENT_SENSE["Current Sense Amplifier"] OVERTEMP["Overtemperature Detect"] OVERCURRENT["Overcurrent Protection"] CURRENT_SENSE --> CONTROLLER OVERTEMP --> CONTROLLER OVERCURRENT --> SHUTDOWN["Shutdown Control"] end style P1_HIGH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style P1_LOW fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intelligent Cooling System & Peripheral Switching Topology Detail

graph LR subgraph "Fan & Pump Control System" subgraph "High-Side P-MOSFET Array" FAN1_MOS["VBE2305
Fan 1 Control"] FAN2_MOS["VBE2305
Fan 2 Control"] FAN3_MOS["VBE2305
Fan 3 Control"] PUMP_MOS["VBE2305
Pump Control"] end DC_12V["12V Rail"] --> FAN1_MOS DC_12V --> FAN2_MOS DC_12V --> FAN3_MOS DC_12V --> PUMP_MOS FAN1_MOS --> FAN1["Fan 1"] FAN2_MOS --> FAN2["Fan 2"] FAN3_MOS --> FAN3["Fan 3"] PUMP_MOS --> PUMP["Cooling Pump"] subgraph "Drive Circuit" PWM_CONTROLLER["PWM Fan Controller"] LEVEL_SHIFTER["Level Shifter"] BOOTSTRAP["Bootstrap Circuit"] PWM_CONTROLLER --> LEVEL_SHIFTER LEVEL_SHIFTER --> FAN1_MOS LEVEL_SHIFTER --> FAN2_MOS LEVEL_SHIFTER --> FAN3_MOS BOOTSTRAP --> PUMP_MOS end TEMP_SENSORS["Temperature Sensors"] --> THERMAL_MCU["Thermal Management MCU"] THERMAL_MCU --> PWM_CONTROLLER end subgraph "Peripheral Load Switching" subgraph "N-MOSFET Load Switches" SSD_POWER["VBJ1311
SSD Power"] SENSOR_POWER["VBJ1311
Sensor Power"] COMM_POWER["VBJ1311
Comm Power"] LED_POWER["VBJ1311
LED Power"] end MCU_GPIO["MCU GPIO"] --> GATE_DRIVE["Gate Drive Buffer"] GATE_DRIVE --> SSD_POWER GATE_DRIVE --> SENSOR_POWER GATE_DRIVE --> COMM_POWER GATE_DRIVE --> LED_POWER VCC_5V["5V Rail"] --> SSD_POWER VCC_5V --> SENSOR_POWER VCC_3V3["3.3V Rail"] --> COMM_POWER VCC_3V3 --> LED_POWER SSD_POWER --> SSD_LOAD["SSD Array"] SENSOR_POWER --> SENSOR_LOAD["Sensor Modules"] COMM_POWER --> COMM_LOAD["Comm Interface"] LED_POWER --> LED_LOAD["Status LEDs"] end style FAN1_MOS fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SSD_POWER fill:#fff3e0,stroke:#ff9800,stroke-width:2px

System Protection & Thermal Management Topology Detail

graph LR subgraph "Three-Level Thermal Management Architecture" LEVEL1["Level 1: Active Cooling"] --> COLD_PLATE["Liquid Cold Plate
CPU/ASIC"] LEVEL2["Level 2: Forced Air"] --> HEATSINK["Heatsink + Fans
Power MOSFETs"] LEVEL3["Level 3: Natural Convection"] --> PCB_COPPER["PCB Copper Pour
Control ICs"] TEMP_MONITOR["Temperature Monitor IC"] --> LEVEL1 TEMP_MONITOR --> LEVEL2 TEMP_MONITOR --> LEVEL3 LEVEL1 --> FAN_CONTROL["Fan Speed Control"] LEVEL2 --> FAN_CONTROL end subgraph "Electrical Protection Network" subgraph "Transient Voltage Suppression" TVS_12V["TVS: 12V Bus"] TVS_48V["TVS: 48V Bus"] TVS_GATE["TVS: Gate Protection"] end subgraph "Current Limiting & Fault Protection" CURRENT_SENSE["Current Sense Resistor"] E_FUSE["eFuse Controller"] OCP_COMP["Overcurrent Comparator"] end subgraph "Snubber & EMI Reduction" RC_SNUBBER["RC Snubber Network"] FERITE_BEAD["Ferrite Bead Filter"] BY_PASS_CAP["Bypass Capacitors"] end TVS_12V --> MAIN_BUS["Main Power Bus"] TVS_48V --> MAIN_BUS TVS_GATE --> GATE_PINS["MOSFET Gate Pins"] CURRENT_SENSE --> E_FUSE E_FUSE --> OCP_COMP OCP_COMP --> FAULT_OUT["Fault Signal"] RC_SNUBBER --> POWER_MOSFET["Power MOSFET Drain"] FERITE_BEAD --> INPUT_RAIL["Input Power Rail"] BY_PASS_CAP --> IC_SUPPLY["IC Supply Pins"] end subgraph "System Monitoring & Communication" PMIC["Power Management IC"] --> I2C_BUS["I2C/SMBus"] ADC["ADC Monitor"] --> VOLT_SENSE["Voltage Sensing"] ADC --> TEMP_SENSE["Temperature Sensing"] ADC --> CURR_SENSE["Current Sensing"] FAULT_OUT --> PMIC PMIC --> ALERT["System Alert"] I2C_BUS --> HOST_MCU["Host Management MCU"] end style COLD_PLATE fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style HEATSINK fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style PCB_COPPER fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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