Driven by the explosive growth of AI computing, micro-module data centers are evolving towards higher density and greater scalability. Their power delivery systems, serving as the "energy arteries" for computing clusters, must provide ultra-high-efficiency, high-power-density, and ultra-reliable power conversion for critical loads such as GPU/Accelerator cards, high-speed cooling fans, and management units. The selection of power MOSFETs directly determines the system's power loss, thermal performance, power density, and operational stability. Addressing the stringent requirements of AI expansion kits for efficiency, thermal management, power density, and 24/7 reliability, this article centers on scenario-based adaptation to reconstruct the power MOSFET selection logic, providing an optimized solution ready for direct implementation. I. Core Selection Principles and Scenario Adaptation Logic Core Selection Principles 1. Voltage Rating with Margin: For AC-DC front-end (e.g., PFC) and DC-DC intermediate bus (e.g., 12V/48V), select MOSFETs with voltage ratings exceeding the maximum operating voltage by a sufficient margin (≥30-50%) to handle line transients and switching spikes. 2. Ultra-Low Loss is Paramount: Prioritize devices with the lowest possible on-state resistance (Rds(on)) and gate charge (Qg) to minimize conduction and switching losses, which is critical for efficiency and thermal management in high-density racks. 3. Package for Power Density and Cooling: Select packages (e.g., TO247, TO220F, DFN) based on power level, required current capability, and thermal dissipation path (heatsink or PCB) to maximize power density. 4. Reliability Under Continuous Stress: Devices must be rated for continuous operation under high ambient temperatures, with excellent thermal stability and ruggedness against voltage surges common in server environments. Scenario Adaptation Logic Based on the power chain within an AI expansion kit, MOSFET applications are divided into three key scenarios: High-Voltage AC-DC Front-End Conversion, High-Current DC-DC Point-of-Load (POL) Conversion, and Cooling & Auxiliary Power Management. Device parameters are matched to the specific voltage, current, and switching frequency demands of each stage. II. MOSFET Selection Solutions by Scenario Scenario 1: High-Voltage AC-DC Front-End / PFC Stage (400V-800V Bus) Recommended Model: VBP16R87SFD (Single-N, 600V, 87A, TO247) Key Parameter Advantages: Features low Rds(on) of 26mΩ at 10V drive using SJ_Multi-EPI technology, coupled with a high current rating of 87A. The 600V rating is ideal for universal input (85-265VAC) PFC and bridge circuits. Scenario Adaptation Value: The TO247 package provides an excellent thermal path for heatsink mounting, crucial for dissipating heat in high-power front-end stages. The extremely low conduction loss directly boosts overall system efficiency (e.g., achieving >96% efficiency for PFC), reducing thermal stress on the entire expansion kit. Applicable Scenarios: PFC boost switches, high-voltage DC-DC primary-side switches in 3KW+ power supply units for AI racks. Scenario 2: High-Current 12V/48V to GPU VRM / POL Conversion Recommended Model: VBGQA1810 (Single-N, 80V, 58A, DFN8(5x6)) Key Parameter Advantages: Utilizes SGT technology to achieve an ultra-low Rds(on) of 9.5mΩ at 10V drive (12.5mΩ at 4.5V). The 58A continuous current rating meets the high transient demands of modern GPU cores. Scenario Adaptation Value: The compact DFN8(5x6) package offers very low parasitic inductance and excellent thermal performance via a large exposed pad, enabling high-frequency multiphase VRM designs with superior power density. The low gate charge allows for fast switching, reducing switching loss and magnetics size in high-frequency POL converters. Applicable Scenarios: Synchronous buck converters for GPU/CPU VRMs, high-current load switches on 12V/48V intermediate buses. Scenario 3: Cooling Fan Drive & Auxiliary Power Management Recommended Model: VBQF2658 (Single-P, -60V, -11A, DFN8(3x3)) Key Parameter Advantages: A -60V P-MOSFET with Rds(on) of 60mΩ at 10V drive (-75mΩ at 4.5V). The -11A current rating is sufficient for driving multiple high-speed fans in parallel or fan arrays. Scenario Adaptation Value: The P-channel configuration simplifies high-side switching for fan speed control or enable/disable functions, often requiring only a simple level-shift circuit. The ultra-compact DFN8(3x3) package saves valuable PCB space in densely populated management boards. Its low Rds(on) ensures minimal voltage drop and heat generation in the fan power path. Applicable Scenarios: High-side power switches for brushless DC (BLDC) fan arrays, hot-swap control, and general-purpose low-voltage power distribution switching. III. System-Level Design Implementation Points Drive Circuit Design VBP16R87SFD: Requires a dedicated high-voltage gate driver IC with adequate peak current capability. Careful attention to gate loop layout is essential to minimize ringing and prevent cross-talk. VBGQA1810: Optimize for high-frequency operation. Use a driver with strong sink/source capability. Ensure very short, symmetric gate and power loop traces in multiphase designs. VBQF2658: Can be driven by a small NPN transistor or a small-signal N-MOSFET for level shifting. A series gate resistor is recommended to dampen ringing. Thermal Management Design Hierarchical Strategy: VBP16R87SFD must be mounted on a heatsink. VBGQA1810 requires a significant PCB thermal relief area connected to internal ground/power planes or a chassis heatsink via thermal interface material. VBQF2658 relies on PCB copper pour for heat dissipation. Derating: Operate MOSFETs at ≤70-80% of their rated current under maximum ambient temperature (e.g., 50°C+ inside the rack). Ensure junction temperatures remain within safe limits with adequate margin. EMC and Reliability Assurance Snubber Networks: For VBP16R87SFD, consider RC snubbers across the drain-source to damp high-frequency oscillations and reduce EMI. Protection: Implement overcurrent protection (OCP) and overtemperature protection (OTP) at the system level for all power stages. Use TVS diodes on gate pins and input/output ports for surge and ESD protection. Ensure proper input/output filtering to meet relevant EMC standards for data center equipment. IV. Core Value of the Solution and Optimization Suggestions The power MOSFET selection solution for AI micro-module data center expansion kits, based on a scenario-adapted logic, provides a complete coverage from high-voltage input to point-of-load and auxiliary management. Its core value is reflected in: 1. Breakthrough in Power Density and Efficiency: By deploying the ultra-low-loss VBGQA1810 in POL stages and the high-efficiency VBP16R87SFD in front-end stages, system-wide conduction and switching losses are dramatically reduced. This enables higher power delivery within the same or smaller footprint, directly contributing to higher compute density per rack unit and improved Power Usage Effectiveness (PUE). 2. Balance of Thermal Management and Intelligent Control: The selection of compact packages (DFN8) for high-current and fan control applications saves space for additional monitoring and control circuitry. The use of devices like VBQF2658 facilitates precise, software-defined fan speed control, allowing for dynamic cooling optimization based on real-time thermal telemetry, thereby improving energy efficiency. 3. Equilibrium of Ultra-High Reliability and Total Cost of Ownership (TCO): The chosen MOSFETs are rated for industrial-grade reliability and continuous operation. Combined with robust thermal and protection design, they ensure mean time between failures (MTBF) targets are met, minimizing downtime. Utilizing proven, volume-produced silicon-based technologies (SJ, SGT) offers a superior cost-to-performance ratio compared to nascent wide-bandgap solutions for most of the power chain, optimizing the TCO for large-scale deployment. In the design of power delivery systems for AI micro-module data centers, MOSFET selection is a cornerstone for achieving high density, efficiency, and unwavering reliability. The scenario-based selection solution proposed here, by precisely matching device characteristics to specific load requirements and coupling it with rigorous system-level design, provides a comprehensive and actionable technical roadmap for expansion kit developers. As AI workloads push power demands even higher, future explorations should focus on the application of next-generation wide-bandgap devices (like SiC in PFC/primary stages and GaN in high-frequency POL stages) and the integration of intelligent power stage modules with digital interfaces, laying a solid hardware foundation for the next generation of scalable, efficient, and intelligent AI infrastructure. In the era of intelligent computing, a robust and efficient power delivery system is the fundamental guarantee for unleashing AI performance.
Detailed Topology Diagrams
High-Voltage AC-DC Front-End / PFC Stage Detail
graph LR
subgraph "Three-Phase PFC Boost Converter"
A[Three-Phase AC Input] --> B[EMI Filter]
B --> C[Three-Phase Rectifier]
C --> D[PFC Boost Inductor]
D --> E[PFC Switching Node]
E --> F["VBP16R87SFD 600V/87A/26mΩ TO247"]
F --> G[High-Voltage DC Bus 400-800VDC]
G --> H[DC-DC Converter]
I[PFC Controller IC] --> J[Gate Driver]
J --> F
G -->|Voltage Feedback| I
K[Current Sense Resistor] -->|Current Feedback| I
L[RC Snubber] --> F
end
subgraph "Thermal & Protection"
M[Heatsink] --> F
N[Temperature Sensor] --> O[OTP Circuit]
O --> P[Shutdown Signal]
P --> I
Q[TVS Diode] --> J
end
style F fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
GPU VRM Multi-Phase POL Conversion Detail
graph LR
subgraph "Three-Phase Synchronous Buck Converter"
A[12V/48V Intermediate Bus] --> B[Input Capacitors]
B --> C[Phase 1 Inductor]
B --> D[Phase 2 Inductor]
B --> E[Phase 3 Inductor]
subgraph "Phase 1"
C --> SW_NODE1[Switching Node]
SW_NODE1 --> Q_H1["VBGQA1810 High-Side 80V/58A/9.5mΩ"]
SW_NODE1 --> Q_L1["VBGQA1810 Low-Side 80V/58A/9.5mΩ"]
Q_H1 --> VIN1[12V/48V Bus]
Q_L1 --> GND1[Ground]
end
subgraph "Phase 2"
D --> SW_NODE2[Switching Node]
SW_NODE2 --> Q_H2["VBGQA1810 High-Side 80V/58A/9.5mΩ"]
SW_NODE2 --> Q_L2["VBGQA1810 Low-Side 80V/58A/9.5mΩ"]
Q_H2 --> VIN2[12V/48V Bus]
Q_L2 --> GND2[Ground]
end
subgraph "Phase 3"
E --> SW_NODE3[Switching Node]
SW_NODE3 --> Q_H3["VBGQA1810 High-Side 80V/58A/9.5mΩ"]
SW_NODE3 --> Q_L3["VBGQA1810 Low-Side 80V/58A/9.5mΩ"]
Q_H3 --> VIN3[12V/48V Bus]
Q_L3 --> GND3[Ground]
end
C --> OUTPUT["GPU VRM Output 0.8-1.2V"]
D --> OUTPUT
E --> OUTPUT
OUTPUT --> F[GPU/Accelerator Load]
G[Multi-Phase Controller] --> H[Gate Driver IC]
H --> Q_H1
H --> Q_L1
H --> Q_H2
H --> Q_L2
H --> Q_H3
H --> Q_L3
end
subgraph "Thermal Management"
I[PCB Thermal Relief Area] --> Q_H1
I --> Q_L1
I --> Q_H2
I --> Q_L2
I --> Q_H3
I --> Q_L3
J[Thermal Via Array] --> I
end
style Q_H1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style Q_L1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
Cooling System & Auxiliary Management Detail
graph LR
subgraph "High-Side Fan Array Control"
A[Management MCU] --> B[PWM Signal]
B --> C[Level Shifter Circuit]
C --> D["VBQF2658 Channel 1 -60V/-11A/60mΩ"]
C --> E["VBQF2658 Channel 2 -60V/-11A/60mΩ"]
C --> F["VBQF2658 Channel 3 -60V/-11A/60mΩ"]
G[12V Auxiliary Power] --> D
G --> E
G --> F
D --> H[BLDC Fan 1]
E --> I[BLDC Fan 2]
F --> J[BLDC Fan 3]
H --> K[Fan Speed Feedback]
I --> K
J --> K
K --> A
end
subgraph "Hot-Swap Power Management"
L[12V Auxiliary Power] --> M["VBQF2658 Hot-Swap Switch"]
N[Hot-Swap Controller] --> O[Gate Control]
O --> M
M --> P[Expansion Slot Power]
Q[Current Sense] --> N
R[OVP/OCP Circuit] --> N
end
subgraph "Thermal Monitoring & Control"
S[Temperature Sensor 1] --> T[ADC Input]
U[Temperature Sensor 2] --> T
V[Temperature Sensor 3] --> T
T --> A
A --> W[Dynamic Cooling Algorithm]
W --> X[Fan Speed Adjustment]
W --> Y[Power Throttling]
X --> B
end
subgraph "Thermal Dissipation"
Z[PCB Copper Pour] --> D
Z --> E
Z --> F
Z --> M
end
style D fill:#fff3e0,stroke:#ff9800,stroke-width:2px
style E fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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