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MOSFET Selection Strategy and Device Adaptation Handbook for AI Industrial Servers with Wide-Temperature and High-Reliability Requirements
AI Industrial Server MOSFET Topology Diagram

AI Industrial Server Power MOSFET System Overall Topology Diagram

graph LR %% AI Server Power System Overview subgraph "AI Industrial Server Power System" subgraph "Scenario 1: CPU/GPU Multi-Phase VRM - Power Core" direction TB VRM_IN["48V/12V Input Bus"] --> PHASE1["Phase 1 Buck Converter"] VRM_IN --> PHASE2["Phase 2 Buck Converter"] VRM_IN --> PHASEN["Phase N Buck Converter"] subgraph "VRM MOSFET Array" Q_HIGH1["VBGMB1105
High-Side Switch
100V/60A"] Q_LOW1["VBGMB1105
Low-Side Switch
100V/60A"] Q_HIGH2["VBGMB1105
High-Side Switch
100V/60A"] Q_LOW2["VBGMB1105
Low-Side Switch
100V/60A"] end PHASE1 --> Q_HIGH1 PHASE1 --> Q_LOW1 PHASE2 --> Q_HIGH2 PHASE2 --> Q_LOW2 Q_LOW1 --> GND_VRM Q_LOW2 --> GND_VRM subgraph "VRM Controller & Driver" PWM_CTRL["Multi-Phase PWM Controller"] GATE_DRIVER["High-Current Gate Driver"] end PWM_CTRL --> GATE_DRIVER GATE_DRIVER --> Q_HIGH1 GATE_DRIVER --> Q_LOW1 GATE_DRIVER --> Q_HIGH2 GATE_DRIVER --> Q_LOW2 Q_HIGH1 --> INDUCTOR1["Output Inductor"] Q_HIGH2 --> INDUCTOR2["Output Inductor"] INDUCTOR1 --> CPU_VCC["CPU/GPU Core Power
0.8-1.5V/100-500A"] INDUCTOR2 --> CPU_VCC end subgraph "Scenario 2: Intelligent Cooling System - Thermal Management" direction TB FAN_BUS["12V/24V Fan Bus"] --> H_BRIDGE1["H-Bridge Fan Driver 1"] FAN_BUS --> H_BRIDGE2["H-Bridge Fan Driver 2"] FAN_BUS --> H_BRIDGEN["H-Bridge Pump Driver N"] subgraph "Half-Bridge MOSFET Pairs" HB1["VBA3316G
Dual N-MOSFET
30V/6.8A"] HB2["VBA3316G
Dual N-MOSFET
30V/6.8A"] HB3["VBA3316G
Dual N-MOSFET
30V/6.8A"] end H_BRIDGE1 --> HB1 H_BRIDGE2 --> HB2 HB1 --> FAN1["BLDC Cooling Fan"] HB2 --> FAN2["BLDC Cooling Fan"] HB3 --> PUMP["Liquid Cooling Pump"] subgraph "Cooling Controller" MCU_COOL["MCU/PWM Controller"] DRV8313["DRV8313 Gate Driver"] end MCU_COOL --> DRV8313 DRV8313 --> HB1 DRV8313 --> HB2 DRV8313 --> HB3 end subgraph "Scenario 3: High-Voltage PFC/Auxiliary Power - Infrastructure" direction LR AC_IN["85-265VAC Input"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> PFC_BRIDGE["Bridge Rectifier"] PFC_BRIDGE --> PFC_STAGE["PFC Boost Stage"] subgraph "PFC Power MOSFET" Q_PFC["VBM18R11S
800V/11A
Superjunction MOSFET"] end PFC_STAGE --> Q_PFC Q_PFC --> HV_BUS["400V HVDC Bus"] subgraph "PFC Controller" PFC_CTRL["PFC Controller IC"] GATE_DRV_PFC["Isolated Gate Driver"] end PFC_CTRL --> GATE_DRV_PFC GATE_DRV_PFC --> Q_PFC HV_BUS --> AUX_CONV["Auxiliary DC-DC Converter"] AUX_CONV --> SYSTEM_RAILS["12V/5V/3.3V System Rails"] end end %% Thermal Management System subgraph "Three-Tier Thermal Management Architecture" TIER1["Tier 1: Heatsink + Forced Air
VRM MOSFETs"] TIER2["Tier 2: PCB Copper Pour
Fan Drive MOSFETs"] TIER3["Tier 3: Natural Convection
Control ICs"] TIER1 --> Q_HIGH1 TIER1 --> Q_LOW1 TIER2 --> HB1 TIER2 --> HB2 TIER3 --> PWM_CTRL TIER3 --> PFC_CTRL end %% Protection & Monitoring subgraph "System Protection & Monitoring" direction LR TEMP_SENSORS["NTC Temperature Sensors"] --> PROTECTION_MCU["Protection MCU"] CURRENT_SENSE["Current Sense Amplifiers"] --> PROTECTION_MCU VOLTAGE_MON["Voltage Monitoring"] --> PROTECTION_MCU PROTECTION_MCU --> OTP["Overtemperature Protection"] PROTECTION_MCU --> OCP["Overcurrent Protection"] PROTECTION_MCU --> OVP["Overvoltage Protection"] OTP --> SHUTDOWN_SIGNAL["System Shutdown"] OCP --> SHUTDOWN_SIGNAL OVP --> SHUTDOWN_SIGNAL end %% EMC & Reliability Circuits subgraph "EMC & Reliability Enhancement" TVS_ARRAY["TVS Diode Array
ESD Protection"] SNUBBER_CIRCUITS["RC/RCD Snubber Circuits"] FERRITE_BEADS["Ferrite Beads
High-Frequency Filtering"] BYPASS_CAPS["Bypass Capacitors
Low-ESR Ceramic"] TVS_ARRAY --> VRM_IN TVS_ARRAY --> FAN_BUS TVS_ARRAY --> AC_IN SNUBBER_CIRCUITS --> Q_PFC SNUBBER_CIRCUITS --> Q_HIGH1 FERRITE_BEADS --> GATE_DRIVER BYPASS_CAPS --> HB1 BYPASS_CAPS --> HB2 end %% Style Definitions style Q_HIGH1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style HB1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_PFC fill:#fff3e0,stroke:#ff9800,stroke-width:2px style PWM_CTRL fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the rapid advancement of artificial intelligence and high-performance computing, AI industrial servers have become the core infrastructure for data processing and autonomous decision-making. The power delivery and thermal management systems, serving as the "lifeblood and cooling engine" of the entire unit, must provide robust and efficient power conversion for critical loads such as multi-phase VRMs, high-speed cooling fans, and auxiliary power rails. The selection of power MOSFETs directly determines system power integrity, thermal performance, power density, and long-term reliability under harsh conditions. Addressing the stringent requirements of industrial servers for wide-temperature operation (e.g., -40°C to 105°C ambient), 24/7 uninterrupted service, high efficiency, and superior transient response, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with demanding industrial operating conditions:
Sufficient Voltage Margin & Wide-Temperature Rating: For server power rails (12V, 48V, high-voltage AC-DC front ends), reserve a rated voltage withstand margin of ≥60% to handle transients and surges. Prioritize devices specified for wide junction temperature ranges (e.g., -55°C ~ 175°C) to ensure stable operation across extended temperature cycles.
Prioritize Low Loss & High Frequency: Prioritize devices with ultra-low Rds(on) (minimizing conduction loss in high-current paths) and excellent FOM (Qg Rds(on)) to reduce switching loss, adapting to high-frequency multiphase buck converters and improving overall power efficiency.
Package Matching for Power & Thermal Density: Choose packages like TO-220, TO-247, or TO-263 with excellent thermal performance for high-power stages (e.g., CPU/GPU VRM, PFC). Select compact, low-parasitic packages like DFN8 or SOP8 for point-of-load (POL) converters and fan drives, balancing power density and thermal management complexity.
Reliability & Ruggedness: Meet mission-critical 24/7 durability requirements, focusing on high avalanche energy rating, strong ESD robustness, and proven long-term reliability under thermal stress, adapting to industrial and edge computing environments.
(B) Scenario Adaptation Logic: Categorization by Load Type
Divide loads into three core scenarios based on function and power level: First, CPU/GPU Multi-Phase VRM (Power Core), requiring extremely high current, high efficiency, and fast transient response. Second, Intelligent Cooling System Drive (Thermal Management), requiring high reliability, PWM control for fans/pumps, and often bridge configurations. Third, High-Voltage Auxiliary & PFC Stage (Infrastructure), requiring high-voltage blocking capability and good efficiency at medium power. This enables precise parameter-to-need matching.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: CPU/GPU Multi-Phase VRM (High Current, High Frequency) – Power Core Device
Modern AI server processors demand very high current (hundreds of amps) supplied by multiphase synchronous buck converters, requiring MOSFETs with ultra-low loss for both high efficiency and thermal management.
Recommended Model: VBGMB1105 (N-MOS, 100V, 60A, TO-220F)
Parameter Advantages: SGT technology achieves a low Rds(on) of 4.7mΩ at 10V, minimizing conduction loss. 100V rating provides ample margin for 48V intermediate bus applications. TO-220F package offers excellent thermal performance (low RthJC) for direct attachment to heatsinks. 60A continuous current suits high-current phases.
Adaptation Value: Significantly reduces power loss in each phase. Enables high-frequency switching (300kHz-1MHz) for faster transient response and reduced inductor size. The robust package supports intensive heatsinking, crucial for maintaining junction temperature in high-density server power supplies.
Selection Notes: Verify phase current requirements and parallel devices if necessary. Ensure proper gate drive capability (≥2A peak) for fast switching. Must be used with a multiphase PWM controller featuring adaptive voltage positioning and comprehensive protection.
(B) Scenario 2: Intelligent Cooling Fan/Pump Drive (Bridge Configuration) – Thermal Management Device
Server cooling systems utilize BLDC fans or pumps controlled by H-bridges, requiring compact, efficient half-bridge MOSFET pairs for PWM speed control.
Recommended Model: VBA3316G (Half-Bridge N+N, 30V, 6.8A/10A, SOP8)
Parameter Advantages: Integrated dual N-MOSFETs in SOP8 save over 50% PCB space compared to discrete solutions. 30V rating is ideal for 12V/24V fan buses. Low Rds(on) (18mΩ at 10V) minimizes heat generation in the drive stage. Low Vth of 1.7V allows compatibility with 3.3V/5V gate driver outputs.
Adaptation Value: Enables compact, high-efficiency H-bridge design for multiple fan channels. Supports high-frequency PWM for precise speed control and low acoustic noise. The integrated package simplifies layout and improves reliability by reducing interconnect parasitics.
Selection Notes: Match continuous current per MOSFET to fan/pump rated current with margin. Pair with a dedicated gate driver IC (e.g., DRV8313) for safe high-side drive. Implement dead-time control to prevent shoot-through.
(C) Scenario 3: High-Voltage PFC or Auxiliary Power Stage – Infrastructure Device
Server power supplies often include Power Factor Correction (PFC) stages or high-voltage auxiliary converters (e.g., from 400V HVDC), requiring MOSFETs with high voltage rating and good switching performance.
Recommended Model: VBM18R11S (N-MOS, 800V, 11A, TO-220)
Parameter Advantages: Superjunction Multi-EPI technology provides an excellent balance of low Rds(on) (500mΩ at 10V) and high voltage rating (800V). 11A continuous current is suitable for medium-power PFC or flyback converter designs. TO-220 package facilitates robust thermal management via heatsinks.
Adaptation Value: Enables efficient high-voltage switching in PFC circuits (e.g., 85-265VAC input), improving system power factor and compliance. The high voltage rating offers strong margin for surge events common in industrial grids. Good switching characteristics help minimize EMI.
Selection Notes: Suited for continuous conduction mode (CCM) or critical conduction mode (CrM) PFC topologies. Gate drive design must manage high-voltage swing and minimize switching loss. Ensure proper snubber or clamping circuit for voltage spikes.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBGMB1105 (VRM): Pair with high-current, high-speed gate driver ICs (e.g., IR2110, UCC27524) located very close to the MOSFET. Use low-inductance gate loop layout. Consider gate resistors to fine-tune switching speed and damp ringing.
VBA3316G (Fan Drive): Can be driven directly by a dedicated half-bridge driver IC. Include bootstrap circuit for high-side drive. Add small RC snubbers across drain-source if needed to reduce EMI.
VBM18R11S (PFC): Use isolated or high-side gate drivers with sufficient voltage rating. Implement Miller clamp functionality if needed to prevent turn-on due to dV/dt. Pay careful attention to creepage and clearance distances.
(B) Thermal Management Design: Tiered Heat Dissipation
VBGMB1105 (VRM): Mandatory use of a heatsink attached to the TO-220F tab. Use thermal interface material (TIM). Thermal vias under the pad on PCB can help. Consider forced air cooling across the VRM bank.
VBA3316G (Fan Drive): SOP8 package relies on PCB copper pour for heat dissipation. Provide generous copper area (≥150mm²) connected to the exposed pad with multiple thermal vias. Airflow from system fans is usually sufficient.
VBM18R11S (PFC): Requires a heatsink in most applications due to medium power dissipation. Isolate the tab electrically if needed. Position within the power supply's airflow path.
(C) EMC and Reliability Assurance
EMC Suppression:
VRM Stage: Use low-ESR input ceramic capacitors very close to MOSFETs. Consider adding a small ferrite bead in series with the gate drive path.
Fan Drive Stage: Add bypass capacitors near the SOP8 package. For long motor leads, use twisted-pair wiring and/or common-mode chokes.
PFC Stage: Implement proper input filtering (X/Y caps, common-mode choke). Use RC snubbers across the MOSFET or diode to damp high-frequency ringing.
Reliability Protection:
Derating Design: Apply conservative derating (e.g., voltage ≤80% of rating, current ≤60-70% at max operating temperature).
Overtemperature Protection: Use temperature sensors on critical heatsinks or MOSFETs themselves, linked to system fan control or shutdown.
Surge/ESD Protection: Use TVS diodes on input power rails and gate pins if exposed. Ensure proper grounding and shielding.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Optimized Performance for Demanding Workloads: High-efficiency MOSFET selection reduces power loss and thermal stress, enabling sustained high performance of AI processors.
Enhanced Reliability for 24/7 Operation: Rugged devices and robust thermal design ensure stable operation over wide temperature ranges and extended lifetimes, critical for industrial and data center deployment.
Balanced Power Density and Cost: Selection of both high-power discrete devices and integrated solutions provides an optimal balance of performance, board space, and system cost for server applications.
(B) Optimization Suggestions
Higher Power VRM: For highest current phases (>80A per device), consider lower Rds(on) variants in TO-247 packages (e.g., VBP1151N, 150V/150A).
Higher Voltage/Current PFC: For higher power PFC stages, consider devices like VBL185R04 (850V/4A) in TO-263 package for better thermal performance.
Wide-Temperature Specialization: For extreme environment edge servers, verify and select automotive-grade or specially screened components for the extended temperature range.
Integration Path: For advanced designs, explore power stage modules that integrate drivers and MOSFETs to further simplify design and improve switching performance.

Detailed Topology Diagrams

CPU/GPU Multi-Phase VRM Topology Detail

graph LR subgraph "Multi-Phase Synchronous Buck Converter" direction TB subgraph "Single Phase Circuit" VIN["48V/12V Input"] --> Q_HS["VBGMB1105
High-Side MOSFET"] Q_HS --> SW_NODE["Switching Node"] SW_NODE --> Q_LS["VBGMB1105
Low-Side MOSFET"] Q_LS --> GND SW_NODE --> L_OUT["Output Inductor"] L_OUT --> COUT["Output Capacitors"] COUT --> VOUT["CPU/GPU Core Voltage"] end subgraph "Interleaved Phases" PHASE1["Phase 1"] --> VOUT PHASE2["Phase 2"] --> VOUT PHASE3["Phase N"] --> VOUT end subgraph "Control & Drive System" MP_CTRL["Multi-Phase PWM Controller"] GATE_DRV["Gate Driver IC"] CURRENT_BALANCE["Current Balancing"] TEMP_MON["Temperature Monitoring"] MP_CTRL --> GATE_DRV GATE_DRV --> Q_HS GATE_DRV --> Q_LS CURRENT_BALANCE --> MP_CTRL TEMP_MON --> MP_CTRL end end subgraph "Thermal Management - VRM Stage" HS_VRM["Heatsink + Thermal Interface"] FAN_VRM["Forced Air Cooling"] THERMAL_VIA["PCB Thermal Vias"] HS_VRM --> Q_HS HS_VRM --> Q_LS FAN_VRM --> HS_VRM THERMAL_VIA --> Q_HS end subgraph "EMC & Protection" GATE_RES["Gate Resistors
Switching Control"] SNUBBER["RC Snubber Network"] TVS_GATE["TVS Gate Protection"] GATE_RES --> GATE_DRV SNUBBER --> SW_NODE TVS_GATE --> Q_HS end style Q_HS fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LS fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intelligent Cooling System Drive Topology Detail

graph LR subgraph "H-Bridge BLDC Fan/Pump Drive" direction TB VCC["12V/24V Supply"] --> H_BRIDGE["Full H-Bridge Circuit"] subgraph "MOSFET Half-Bridge Pair" HB_TOP["VBA3316G
High-Side MOSFETs"] HB_BOT["VBA3316G
Low-Side MOSFETs"] subgraph "Integrated Dual N-MOS" HS1["High-Side 1"] LS1["Low-Side 1"] HS2["High-Side 2"] LS2["Low-Side 2"] end end H_BRIDGE --> HB_TOP H_BRIDGE --> HB_BOT HB_TOP --> MOTOR_TERM_A["Motor Terminal A"] HB_BOT --> MOTOR_TERM_A HB_TOP --> MOTOR_TERM_B["Motor Terminal B"] HB_BOT --> MOTOR_TERM_B MOTOR_TERM_A --> BLDC_MOTOR["BLDC Fan/Pump"] MOTOR_TERM_B --> BLDC_MOTOR end subgraph "Gate Drive & Control Circuit" DRIVER_IC["Half-Bridge Driver IC"] BOOTSTRAP["Bootstrap Circuit"] DEAD_TIME["Dead-Time Control"] PWM_GEN["PWM Generator"] PWM_GEN --> DRIVER_IC DRIVER_IC --> BOOTSTRAP BOOTSTRAP --> HB_TOP DRIVER_IC --> DEAD_TIME DEAD_TIME --> HB_TOP DEAD_TIME --> HB_BOT end subgraph "Thermal Management - Drive Stage" COPPER_POUR["PCB Copper Pour Area"] THERMAL_VIAS["Multiple Thermal Vias"] AIRFLOW["System Airflow Path"] COPPER_POUR --> HB_TOP COPPER_POUR --> HB_BOT THERMAL_VIAS --> COPPER_POUR AIRFLOW --> COPPER_POUR end subgraph "EMC & Motor Protection" BYPASS_CAP["Bypass Capacitor
Near Package"] COMMON_MODE["Common-Mode Choke"] TWISTED_PAIR["Twisted Pair Wiring"] FREE_WHEEL["Free-Wheel Diodes"] BYPASS_CAP --> VCC COMMON_MODE --> MOTOR_TERM_A COMMON_MODE --> MOTOR_TERM_B TWISTED_PAIR --> BLDC_MOTOR FREE_WHEEL --> HB_TOP FREE_WHEEL --> HB_BOT end style HB_TOP fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style HB_BOT fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

High-Voltage PFC/Auxiliary Power Topology Detail

graph LR subgraph "PFC Boost Converter Stage" AC_IN["AC Input
85-265VAC"] --> BRIDGE["Bridge Rectifier"] BRIDGE --> RECTIFIED["Rectified DC"] RECTIFIED --> PFC_INDUCTOR["Boost Inductor"] PFC_INDUCTOR --> SW_NODE_PFC["PFC Switching Node"] subgraph "Power Switch & Diode" Q_PFC_MOS["VBM18R11S
800V/11A MOSFET"] PFC_DIODE["High-Speed Diode"] end SW_NODE_PFC --> Q_PFC_MOS SW_NODE_PFC --> PFC_DIODE Q_PFC_MOS --> PFC_GND PFC_DIODE --> HV_BUS_PFC["High Voltage DC Bus
~400VDC"] HV_BUS_PFC --> OUTPUT_CAP["Output Capacitors"] OUTPUT_CAP --> PFC_OUT["Stabilized HVDC"] end subgraph "PFC Control & Drive Circuit" PFC_CONTROLLER["PFC Controller IC"] ISOLATED_DRIVER["Isolated Gate Driver"] MILLER_CLAMP["Miller Clamp Circuit"] VOLTAGE_FB["Voltage Feedback"] CURRENT_FB["Current Feedback"] PFC_CONTROLLER --> ISOLATED_DRIVER ISOLATED_DRIVER --> MILLER_CLAMP MILLER_CLAMP --> Q_PFC_MOS VOLTAGE_FB --> PFC_CONTROLLER CURRENT_FB --> PFC_CONTROLLER end subgraph "Thermal Management - PFC Stage" PFC_HEATSINK["Aluminum Heatsink"] ISOLATION_PAD["Thermal Pad - Electrically Isolating"] AIRFLOW_PFC["Forced Airflow Path"] PFC_HEATSINK --> ISOLATION_PAD ISOLATION_PAD --> Q_PFC_MOS AIRFLOW_PFC --> PFC_HEATSINK end subgraph "EMC & Protection Circuits" INPUT_FILTER["Input EMI Filter"] SNUBBER_PFC["RCD Snubber Network"] CREEPAGE["Creepage/ Clearance Design"] TVS_INPUT["Input TVS Protection"] INPUT_FILTER --> AC_IN SNUBBER_PFC --> Q_PFC_MOS CREEPAGE --> ISOLATED_DRIVER TVS_INPUT --> BRIDGE end subgraph "Auxiliary Power Generation" PFC_OUT --> FLYBACK["Flyback Converter"] FLYBACK --> AUX_TRANS["Auxiliary Transformer"] AUX_TRANS --> SYSTEM_RAILS_PFC["12V/5V/3.3V Rails"] end style Q_PFC_MOS fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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