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AI Object Storage Cluster Power MOSFET Selection Solution: Efficient and Reliable Power and Thermal Management System Adaptation Guide
AI Object Storage Cluster Power MOSFET Selection Topology

AI Object Storage Cluster Power MOSFET System Overall Topology

graph LR %% Power Supply Unit Section subgraph "High-Efficiency PSU & Power Conversion (Energy Core)" AC_IN["AC Input
100-240VAC"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> PFC_STAGE["PFC Stage"] PFC_STAGE --> HV_BUS["High-Voltage DC Bus"] subgraph "Primary Side Switching" Q_PFC["VBMB195R06
950V/6A
TO220F"] end HV_BUS --> DC_DC_PRIMARY["DC-DC Primary"] subgraph "48V to 12V/5V DC-DC" Q_PRIMARY_SW["VBGED1103
100V/180A
LFPAK56"] Q_SR["VBGED1103
100V/180A
LFPAK56"] TRANSFORMER["High-Frequency Transformer"] end DC_DC_PRIMARY --> Q_PRIMARY_SW Q_PRIMARY_SW --> TRANSFORMER TRANSFORMER --> Q_SR Q_SR --> OUTPUT_FILTER["Output Filter"] OUTPUT_FILTER --> DC_OUT["DC Output
12V/5V"] DC_OUT --> SERVER_LOAD["Storage Server Load"] end %% Thermal Management Section subgraph "Intelligent Fan Drive & Thermal Management (Cooling Core)" MCU["BMC/MCU
Control Unit"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> Q_FAN["VBA2333
-30V/-5.8A
SOP8"] Q_FAN --> FAN_LOAD["Fan Bank Load
40mm+ Fans"] TEMP_SENSORS["Temperature Sensors"] --> MCU MCU --> PWM_CONTROL["PWM Control Logic"] PWM_CONTROL --> LEVEL_SHIFTER end %% Power Distribution & Protection subgraph "High-Availability Power Routing & Control (Availability Core)" REDUNDANT_PSU["Redundant PSU
Input"] --> ORING_CONTROL["OR-ing Controller"] subgraph "Power OR-ing Circuit" Q_ORING1["VBMB195R06
950V/6A"] Q_ORING2["VBMB195R06
950V/6A"] end ORING_CONTROL --> Q_ORING1 ORING_CONTROL --> Q_ORING2 Q_ORING1 --> COMMON_BUS["Common Power Bus"] Q_ORING2 --> COMMON_BUS COMMON_BUS --> LOAD_DISTRIBUTION["Load Distribution"] end %% Protection Circuits subgraph "System Protection & Monitoring" SUB_SNUBBER["Snubber Circuits"] --> Q_PRIMARY_SW SUB_RC["RC Networks"] --> Q_SR PROT_TVS["TVS Diodes"] --> GATE_DRIVERS["Gate Drivers"] PROT_OCP["Over-Current Protection"] --> FAULT_LATCH["Fault Latch"] PROT_OTP["Over-Temp Protection"] --> FAULT_LATCH FAULT_LATCH --> SHUTDOWN_SIGNAL["Shutdown Signal"] SHUTDOWN_SIGNAL --> Q_PRIMARY_SW SHUTDOWN_SIGNAL --> Q_FAN end %% Thermal Management Hierarchy subgraph "Three-Level Thermal Management" COOLING_LEVEL1["Level 1: Heatsink Cooling
VBMB195R06 (TO220F)"] COOLING_LEVEL2["Level 2: PCB Thermal Vias
VBGED1103 (LFPAK56)"] COOLING_LEVEL3["Level 3: Copper Pour
VBA2333 (SOP8)"] COOLING_LEVEL1 --> Q_PFC COOLING_LEVEL1 --> Q_ORING1 COOLING_LEVEL2 --> Q_PRIMARY_SW COOLING_LEVEL2 --> Q_SR COOLING_LEVEL3 --> Q_FAN end %% System Monitoring & Control MCU --> CAN_BUS["CAN Bus Interface"] MCU --> CLOUD_MONITOR["Cloud Monitoring"] MCU --> EFFICIENCY_OPT["Efficiency Optimization
Algorithm"] %% Style Definitions style Q_PRIMARY_SW fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_FAN fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_ORING1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Driven by the exponential growth of data, AI object storage clusters have become the core infrastructure for massive cold and warm data. Their server power supply units (PSUs) and cooling systems, serving as the "heart and lungs" of the entire cluster, must provide highly efficient and stable power conversion and precise thermal management. The selection of power MOSFETs directly determines the system's power efficiency, power density, thermal performance, and operational reliability. Addressing the stringent requirements of data centers for power usage effectiveness (PUE), reliability, and scalability, this article centers on scenario-based adaptation to reconstruct the power MOSFET selection logic, providing an optimized solution ready for direct implementation.
I. Core Selection Principles and Scenario Adaptation Logic
Core Selection Principles
Voltage & Current Robustness: For PSU bus voltages (12V/48V/54V) and fan drive voltages (12V/48V), MOSFETs must have sufficient voltage margin (≥30-50%) and current rating to handle transient spikes and 7x24 continuous operation.
Ultra-Low Loss Priority: Prioritize devices with extremely low on-state resistance (Rds(on)) and favorable gate charge (Qg) to minimize conduction and switching losses, which is critical for PSU efficiency and reducing heat generation in high-density racks.
Package for Thermal & Density: Select packages like TO220F, LFPAK, DFN, or SOP based on power level and PCB layout constraints to balance high current handling, thermal dissipation, and power density.
High Reliability & Lifespan: Devices must meet the demands of continuous operation in controlled but demanding environments, with focus on thermal stability, avalanche ruggedness, and long-term parameter drift.
Scenario Adaptation Logic
Based on the core power chain within an AI storage server node, MOSFET applications are divided into three main scenarios: High-Efficiency PSU & Power Conversion (Energy Core), Intelligent Fan Drive & Thermal Management (Cooling Core), and High-Availability Power Routing & Control (Availability Core). Device parameters and characteristics are matched accordingly.
II. MOSFET Selection Solutions by Scenario
Scenario 1: High-Efficiency PSU & Power Conversion (e.g., 48V to 12V/5V, 800W-2000W+) – Energy Core Device
Recommended Model: VBGED1103 (Single-N, 100V, 180A, LFPAK56)
Key Parameter Advantages: Utilizes advanced SGT technology, achieving an ultra-low Rds(on) of 3.0mΩ at 10V Vgs. A continuous current rating of 180A easily meets the demands of high-current synchronous rectification and primary-side switching in multi-phase VRMs or DC-DC stages.
Scenario Adaptation Value: The LFPAK56 package offers excellent thermal performance (low Rth(j-a)) and low parasitic inductance, which is crucial for high-frequency, high-efficiency switching in PSUs. Its ultra-low conduction loss directly contributes to higher Platinum/Titanium PSU efficiency ratings, reducing overall cluster PUE and operating costs.
Applicable Scenarios: Synchronous rectification in server PSUs, primary-side switches in high-power DC-DC converters, and high-current buck converters for CPU/GPU rails (where applicable).
Scenario 2: Intelligent High-Speed Fan Drive (40mm+ Fans, 50W-150W) – Cooling Core Device
Recommended Model: VBA2333 (Single-P, -30V, -5.8A, SOP8)
Key Parameter Advantages: -30V voltage rating suitable for 12V/24V fan systems. Rds(on) as low as 33mΩ at 10V drive. Current capability of -5.8A meets the needs of multiple high-speed fans in parallel. Gate threshold voltage of -1.7V allows for direct drive by a BMC or MCU's GPIO (with simple level translation).
Scenario Adaptation Value: The SOP8 package is compact and facilitates PCB layout for fan control boards. Its low Rds(on) minimizes voltage drop and power loss in the fan power path. Enables precise PWM-based speed control for individual or grouped fans, supporting dynamic cooling algorithms based on storage drive and CPU temperatures, balancing acoustics and cooling capacity.
Applicable Scenarios: High-side switching and PWM control for cooling fan banks, power enable/disable for fan modules, and general low-voltage power distribution switching.
Scenario 3: High-Availability Power Routing & PFC Stage (Safety & Reliability Critical)
Recommended Model: VBMB195R06 (Single-N, 950V, 6A, TO220F)
Key Parameter Advantages: High voltage rating of 950V is ideal for PFC (Power Factor Correction) stages in 400V+ AC-input PSUs or as an isolation switch in redundant power paths. The TO220F fully insulated package enhances system safety and simplifies heatsink mounting.
Scenario Adaptation Value: The high-voltage capability provides crucial design margin for handling AC line surges and PFC bus voltages. The insulated package prevents short circuits in dense power layouts. It can be used to implement OR-ing circuits for redundant PSUs or as a robust switch in auxiliary power supplies, ensuring fault isolation and system availability.
Applicable Scenarios: Switching devices in PFC circuits, high-voltage side switches in AC-DC front ends, and isolation switches in N+1 redundant power supply architectures.
III. System-Level Design Implementation Points
Drive Circuit Design
VBGED1103: Requires a dedicated high-current gate driver IC. Attention must be paid to minimizing power loop inductance with a tight PCB layout. Use low-impedance gate drive paths.
VBA2333: Can be driven via a small-signal N-MOSFET or bipolar transistor for level shifting. Include a gate resistor to damp ringing. ESD protection is recommended.
VBMB195R06: Use an isolated or high-side gate driver IC suitable for high-voltage applications. Implement proper creepage and clearance distances on the PCB.
Thermal Management Design
Hierarchical Strategy: VBGED1103 may require a dedicated heatsink or connection to the PSU chassis via the LFPAK56 tab. VBMB195R06 benefits from its TO220F package being mounted on a main heatsink. VBA2333 typically relies on PCB copper pour for heat dissipation.
Derating Practice: Operate MOSFETs at or below 70-80% of their rated current under maximum ambient temperature (e.g., 40-50°C inlet). Ensure junction temperature remains with a safe margin from the maximum rating.
EMC and Reliability Assurance
Switching Noise Mitigation: Use snubber circuits or parallel RC networks across the drain-source of high-speed switching MOSFETs (VBGED1103) to control voltage spikes and reduce EMI.
Protection Features: Implement overcurrent protection (OCP) and overtemperature protection (OTP) at the system level. Utilize TVS diodes on input lines and near MOSFET gates for surge and ESD protection. Ensure proper input fusing.
IV. Core Value of the Solution and Optimization Suggestions
The power MOSFET selection solution for AI object storage clusters proposed in this article, based on scenario adaptation logic, achieves targeted optimization from high-efficiency power conversion to intelligent thermal management and high-availability power routing. Its core value is mainly reflected in the following three aspects:
Optimized PUE and TCO: By selecting the ultra-low-loss VBGED1103 for critical power conversion paths and the efficient VBA2333 for cooling control, power losses are minimized across both the computation/storage power chain and the essential cooling overhead. This directly contributes to a lower PUE, reducing the total cost of ownership (TCO) for the data center.
Intelligent Thermal Control and Reliability: The use of a directly controllable P-MOS like VBA2333 enables granular, software-defined fan control, allowing for dynamic cooling that adapts to real-time load, improving energy efficiency and acoustics. The high-voltage, rugged VBMB195R06 in critical power paths enhances electrical safety and system uptime through robust design and fault isolation capabilities.
Balance of Performance, Density, and Cost: The selected devices offer best-in-class performance for their respective roles (e.g., Rds(on), current rating) in packages that enable high power density. As mature, volume-produced components, they provide a superior cost-to-performance ratio compared to emerging wide-bandgap technologies, making them ideal for large-scale deployment in cost-sensitive storage clusters.
In the design of power and thermal management systems for AI object storage clusters, power MOSFET selection is a cornerstone for achieving efficiency, reliability, and scalability. This scenario-based selection solution, by precisely matching device characteristics to specific subsystem requirements and combining it with robust system-level design practices, provides a comprehensive, actionable technical roadmap. As data centers evolve towards higher rack densities, liquid cooling, and more advanced power architectures, MOSFET selection will increasingly focus on integration with digital controllers and compatibility with new topologies. Future exploration could involve co-packaged power stages and the application of SiC MOSFETs in high-voltage PFC stages, laying a solid hardware foundation for the next generation of ultra-efficient, high-density, and intelligent AI storage infrastructure.

Detailed Topology Diagrams

High-Efficiency PSU & Power Conversion Topology Detail

graph LR subgraph "PFC Stage (400V+ AC Input)" AC_INPUT["AC Input"] --> PFC_EMI["EMI Filter"] PFC_EMI --> RECTIFIER["Bridge Rectifier"] RECTIFIER --> PFC_INDUCTOR["PFC Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switch Node"] PFC_SW_NODE --> Q_PFC_DETAIL["VBMB195R06
950V/6A"] Q_PFC_DETAIL --> HV_BUS_OUT["~400VDC Bus"] PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> Q_PFC_DETAIL end subgraph "48V to 12V DC-DC Stage" HV_BUS_IN["400VDC Bus"] --> LLC_RESONANT["LLC Resonant Tank"] LLC_RESONANT --> HF_TRANS["High-Freq Transformer"] subgraph "Primary Side" Q_PRIMARY["VBGED1103
100V/180A"] end subgraph "Secondary Side (Sync Rect)" Q_SR1["VBGED1103
100V/180A"] Q_SR2["VBGED1103
100V/180A"] end HF_TRANS --> Q_PRIMARY Q_PRIMARY --> GND_PRIMARY HF_TRANS --> Q_SR1 HF_TRANS --> Q_SR2 Q_SR1 --> OUTPUT_LC["LC Filter"] Q_SR2 --> OUTPUT_LC OUTPUT_LC --> PSU_OUTPUT["12V/5V Output"] SR_CONTROLLER["Sync Rect Controller"] --> SR_DRIVER["Driver IC"] SR_DRIVER --> Q_SR1 SR_DRIVER --> Q_SR2 end style Q_PFC_DETAIL fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_PRIMARY fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Intelligent Fan Drive & Thermal Management Topology Detail

graph LR subgraph "BMC/MCU Control Unit" BMC["Baseboard Management
Controller"] --> GPIO["GPIO Ports"] GPIO --> TEMP_MONITOR["Temp Monitoring
Algorithm"] TEMP_MONITOR --> PWM_GEN["PWM Generator"] end subgraph "Fan Drive Circuit (High-Side Switch)" PWM_SIGNAL["PWM Signal"] --> LEVEL_SHIFTER_CIRCUIT["Level Shifter Circuit"] LEVEL_SHIFTER_CIRCUIT --> GATE_DRIVE_FAN["Gate Drive"] VCC_12V["12V Supply"] --> Q_FAN_DETAIL["VBA2333
-30V/-5.8A"] GATE_DRIVE_FAN --> Q_FAN_DETAIL Q_FAN_DETAIL --> FAN_CONNECTOR["Fan Connector"] FAN_CONNECTOR --> FAN_MOTOR["Fan Motor"] FAN_MOTOR --> GND_FAN subgraph "Multiple Fan Zones" ZONE_CPU["CPU Zone Fans"] ZONE_DRIVE["Drive Bay Fans"] ZONE_PSU["PSU Fans"] end FAN_CONNECTOR --> ZONE_CPU FAN_CONNECTOR --> ZONE_DRIVE FAN_CONNECTOR --> ZONE_PSU end subgraph "Temperature Sensing Network" SENSOR_CPU["CPU Temp Sensor"] --> ADC["ADC Input"] SENSOR_DRIVE["Drive Temp Sensor"] --> ADC SENSOR_INLET["Inlet Temp Sensor"] --> ADC ADC --> BMC end subgraph "Protection Circuits" ESD_PROT["ESD Protection"] --> Q_FAN_DETAIL CURRENT_LIMIT["Current Limit"] --> Q_FAN_DETAIL FUSE["Poly Fuse"] --> VCC_12V end style Q_FAN_DETAIL fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style BMC fill:#fce4ec,stroke:#e91e63,stroke-width:2px

High-Availability Power Routing & PFC Topology Detail

graph LR subgraph "N+1 Redundant Power Supply Architecture" PSU_A["PSU A Output"] --> ORING_CONTROL_CIRCUIT["OR-ing Controller"] PSU_B["PSU B Output"] --> ORING_CONTROL_CIRCUIT subgraph "OR-ing MOSFET Array" Q_ORING_A["VBMB195R06
950V/6A"] Q_ORING_B["VBMB195R06
950V/6A"] end ORING_CONTROL_CIRCUIT --> GATE_DRIVER_A["Isolated Gate Driver"] ORING_CONTROL_CIRCUIT --> GATE_DRIVER_B["Isolated Gate Driver"] GATE_DRIVER_A --> Q_ORING_A GATE_DRIVER_B --> Q_ORING_B Q_ORING_A --> COMMON_POWER_BUS["Common Power Bus"] Q_ORING_B --> COMMON_POWER_BUS COMMON_POWER_BUS --> LOAD_SERVERS["Storage Servers"] end subgraph "PFC Stage Detail" AC_IN_PFC["3-Phase AC Input"] --> PFC_RECT["3-Phase Rectifier"] PFC_RECT --> PFC_CHOKE["PFC Choke"] PFC_CHOKE --> PFC_SWITCH_NODE["Switch Node"] subgraph "PFC Switching MOSFETs" Q_PFC1["VBMB195R06
950V/6A"] Q_PFC2["VBMB195R06
950V/6A"] end PFC_SWITCH_NODE --> Q_PFC1 PFC_SWITCH_NODE --> Q_PFC2 Q_PFC1 --> PFC_OUTPUT["PFC Output Cap"] Q_PFC2 --> PFC_GND PFC_OUTPUT --> HV_BUS_PFC["380-400VDC"] PFC_CONTROLLER_IC["PFC Controller"] --> PFC_GATE_DRIVER["High-Voltage Driver"] PFC_GATE_DRIVER --> Q_PFC1 PFC_GATE_DRIVER --> Q_PFC2 end subgraph "Fault Detection & Isolation" CURRENT_SENSE_ORING["Current Sensing"] --> COMPARATOR["Comparator"] VOLTAGE_SENSE_ORING["Voltage Sensing"] --> COMPARATOR COMPARATOR --> FAULT_LOGIC["Fault Logic"] FAULT_LOGIC --> DISABLE_SIGNAL["Disable Signal"] DISABLE_SIGNAL --> ORING_CONTROL_CIRCUIT FAULT_LOGIC --> ALERT["System Alert"] end style Q_ORING_A fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_PFC1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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