With the proliferation of AI workloads and cloud computing, dual-socket virtualization servers have become the backbone of data center infrastructure. The power delivery and management systems, serving as the "lifeblood" of the server, must provide exceptionally stable, efficient, and intelligent power conversion for critical loads such as CPUs, GPUs, memory, and storage. The selection of power semiconductors (MOSFETs/IGBTs) is pivotal in determining system efficiency, power density, thermal performance, and ultimate reliability. Addressing the stringent requirements of AI servers for uninterrupted operation (24/7), high power efficiency (80 Plus Titanium targets), and superior thermal management, this article develops a practical, scenario-optimized selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Multi-Dimensional Co-Design
Selection requires a holistic co-design across electrical, thermal, and reliability parameters to ensure precise alignment with server operating profiles:
Voltage & Current Robustness: For main power rails (12V, 48V, high-voltage DC bus), reserve a voltage derating ≥30-50% to handle transients and ensure longevity. Current ratings must support peak loads (e.g., CPU turbo states) with sufficient margin.
Loss Minimization as Priority: Prioritize ultra-low Rds(on) to minimize conduction loss in high-current paths, and low gate charge (Qg) / output capacitance (Coss) to reduce switching losses at high frequencies (e.g., 300-500kHz VRMs), directly impacting PUE (Power Usage Effectiveness).
Package & Thermal Synergy: Choose packages (e.g., DFN, TOLL, TO-247) that offer low thermal resistance (RthJC) and are compatible with advanced cooling solutions (heat pipes, liquid cold plates). Parasitic inductance must be minimized for clean high-speed switching.
Reliability & Automotive-Grade Demands: Meet or exceed server-grade MTBF requirements. Focus on high junction temperature capability (Tj max ≥ 150°C), robust avalanche energy rating, and suitability for continuous high-stress operation.
(B) Scenario Adaptation Logic: Categorization by Power Stage Function
Divide server power stages into three core scenarios: First, High-Current CPU/GPU Voltage Regulator Modules (VRM), requiring the highest efficiency and power density. Second, AC-DC Power Supply Unit (PSU) & Power Factor Correction (PFC) stages, demanding high-voltage switching and reliability. Third, Auxiliary & Point-of-Load (POL) Regulation, needing compact, efficient solutions for various secondary rails. This enables precise device-to-task matching.
II. Detailed Semiconductor Selection Scheme by Scenario
(A) Scenario 1: High-Current CPU/GPU VRM – The Efficiency Critical Device
Multi-phase VRMs for modern CPUs/GPUs require handling extremely high currents (up to hundreds of Amps) with fast transient response and minimal loss.
Recommended Model: VBGE1121N (N-MOS, 120V, 60A, TO252)
Parameter Advantages: Utilizes advanced SGT (Shielded Gate Trench) technology, achieving an ultra-low Rds(on) of 11.5mΩ at Vgs=10V. A continuous current rating of 60A is suitable for individual phases in a multiphase buck converter. The TO252 (D2PAK) package offers a good balance of thermal performance and PCB footprint.
Adaptation Value: Drastically reduces conduction loss per phase. In a 12V-input, 1.8V-output VRM phase carrying 30A, conduction loss is approximately 10.4W, contributing to overall VRM efficiency >92%. Its fast switching characteristics support high-frequency operation (300-500kHz), enabling smaller inductors and capacitors for increased power density crucial in dense server layouts.
Selection Notes: Verify phase current requirements and thermal design. Utilize in synchronous buck topology with a dedicated multi-phase PWM controller. Implement careful PCB layout to minimize power loop inductance and ensure proper gate driving (≥2A gate driver recommended).
(B) Scenario 2: PFC & Main DC-DC Stage in PSU – The High-Voltage Workhorse
The PFC boost stage and primary-side DC-DC conversion in server PSUs operate at high voltages (~400V DC bus) and require robust, efficient switching.
Recommended Model: VBPB16R20S (N-MOS, 600V, 20A, TO3P)
Parameter Advantages: Features SJ_Multi-EPI (Super-Junction Multi-Epitaxial) technology, offering a competitive Rds(on) of 190mΩ at 600V rating. The 20A current rating and robust TO3P package are well-suited for continuous operation in hard-switched PFC circuits (e.g., critical conduction mode).
Adaptation Value: Provides a reliable and efficient switch for 80 Plus Titanium/Platinum level PSUs. Its high voltage rating offers ample margin for universal AC input (85-265VAC) and bus voltage spikes. The low Rds(on) minimizes conduction loss in the PFC choke current path, improving overall PSU efficiency.
Selection Notes: Suitable for PFC boost switches and primary-side switches in LLC resonant or active clamp flyback converters. Must be paired with an appropriate high-voltage gate driver (e.g., with bootstrap or isolated supply). Thermal management via heatsink on the TO3P package is essential.
(C) Scenario 3: High-Current, Low-Voltage POL & OR-ing – The Power Distribution Manager
Secondary-side synchronous rectification, low-voltage high-current POL conversion (e.g., for memory, chipset), and OR-ing for power redundancy require very low Rds(on) in compact packages.
Recommended Model: VBQF1306 (N-MOS, 30V, 40A, DFN8(3x3))
Parameter Advantages: Trench technology delivers an exceptionally low Rds(on) of 5mΩ at Vgs=10V. The 40A current rating and compact DFN8 package offer an outstanding current density. Low gate charge enables efficient high-frequency switching.
Adaptation Value: Ideal for synchronous rectification in secondary-side DC-DC converters (e.g., 12V to 5V/3.3V/1.8V) or as the main switch in high-current, non-isolated POL buck converters. Its low loss minimizes heat generation in densely packed server motherboard areas. Can also serve as an efficient OR-ing FET in redundant power supply paths.
Selection Notes: The DFN8 package requires a well-designed PCB thermal pad (≥200mm² with multiple vias) for heat dissipation. Ensure gate drive voltage is sufficient (≥4.5V recommended) to achieve the lowest Rds(on). Pay close attention to layout to minimize parasitic inductance in high di/dt paths.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Optimized for Speed and Robustness
VBGE1121N (VRM): Pair with dedicated high-current, high-speed multi-phase VRM controllers (e.g., Intersil ISLxxxx, Renesas IRxxxx series). Use gate drivers capable of sourcing/sinking >3A with short propagation delays. Implement adaptive gate drive strength if possible.
VBPB16R20S (PFC/Primary): Use isolated or high-side gate driver ICs (e.g., TI UCC2xxxx, Silicon Labs Si82xx). Incorporate Miller clamp circuitry if needed to prevent parasitic turn-on. Ensure clean, low-inductance gate drive loops.
VBQF1306 (POL/OR-ing): Can often be driven directly by POL controller integrated drivers. For OR-ing applications, use a dedicated OR-ing controller with fast turn-off to prevent back-feeding.
(B) Thermal Management Design: A Tiered Approach
VBGE1121N & VBPB16R20S (High Power): Mandatory attachment to heatsinks. Use thermal interface material (TIM) with low thermal resistance. For VRM phases, consider direct contact with server's primary cooling solution (heat pipe array or cold plate).
VBQF1306 (Medium Power): Rely on a large, multi-via PCB thermal pad connected to internal ground planes for heat spreading. In extreme cases, consider a small clip-on heatsink or thermal pad connection to the chassis.
System Airflow: Coordinate placement of power components with server fan zones. Position hottest devices (like VRM MOSFETs) in the path of highest airflow.
(C) EMC and Reliability Assurance
EMC Suppression:
Add small-value (100pF-2.2nF) high-frequency capacitors close to the drain-source of switching FETs.
Use snubber circuits (RC or RCD) across primary switches (VBPB16R20S) if needed to dampen ringing.
Implement proper input EMI filtering at the PSU inlet, including common-mode chokes and X/Y capacitors.
Reliability Protection:
Derating: Adhere to strict derating guidelines: Voltage derating ≥30%, current derating ≥50% at maximum expected case temperature.
Overcurrent Protection: Implement phase current sensing (e.g., using sense resistors or inductor DCR sensing) in VRM. Use controller-based cycle-by-cycle current limiting.
Overtemperature Protection: Monitor heatsink or case temperature near critical FETs. Utilize the OTP features of PWM controllers.
Transient Protection: Employ TVS diodes on input power rails (12V, 48V) and gate pins. Use varistors at the AC input of the PSU.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Power Efficiency: The selected devices directly contribute to achieving >96% efficiency in VRMs and >95% in PSUs, reducing data center operational costs (OPEX) and carbon footprint.
Enhanced Power Density and Reliability: The combination of low-loss FETs and robust high-voltage switches enables compact, reliable power designs that meet the stringent demands of 24/7 AI server operation.
Future-Proofing for Higher Power: The selected technologies (SGT, SJ) provide a scalable path for supporting next-generation CPUs/GPUs with even higher power demands.
(B) Optimization Suggestions
For Higher Power VRMs (>100A per phase): Consider parallel operation of VBGE1121N or evaluate devices in TOLL (TO-leadless) packages for lower thermal resistance.
For Advanced PSU Topologies (e.g., Totem-Pole PFC): Consider using VBGE1121N (120V) or similar in the critical fast-leg for its superior switching performance, paired with a SiC diode or MOSFET for ultimate efficiency.
For Space-Constrained POL: The VBQF1306 in DFN8 is ideal. For even lower voltage (<1V) high-current applications, consider devices with even lower Rds(on) at Vgs=4.5V.
For Hot-Swap and High-Availability Control: The VBQF2625 (P-MOS, -60V) can be considered for high-side power path control in redundant modules, thanks to its integrated dual channels in TSSOP8.
For Very High-Power PSUs (>3kW): The VBP16I75 (600V IGBT) could be evaluated for specific PFC or DC-DC topologies where its combination of high voltage and current is advantageous, though switching frequency may be lower than MOSFET-based designs.
Conclusion
The strategic selection of power semiconductors is fundamental to achieving the efficiency, density, and unwavering reliability required in AI and virtualization server platforms. This scenario-based methodology provides a clear framework for matching device capabilities to specific power stage challenges through coordinated electrical, thermal, and system design. Future evolution will involve deeper integration of Wide Bandgap (SiC, GaN) devices and intelligent power stages (IPMs), pushing the boundaries of data center power infrastructure to support the relentless growth of computational demand.

Detailed Topology Diagrams by Application Scenario