With the explosive growth of AI computing demands, high-performance training servers equipped with 8 GPUs have become the core infrastructure for deep learning. The power delivery system, serving as the "energy heart" of the entire server, must provide ultra-high current, high-efficiency, and precise power conversion for critical loads such as GPU VRMs, high-speed fans, and auxiliary controllers. The selection of power MOSFETs directly determines the system's power density, conversion efficiency, thermal performance, and overall reliability. Addressing the stringent requirements of AI servers for maximum uptime, energy efficiency, and power density, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with the severe operating conditions within a server:
Sufficient Voltage Margin: For server power rails (12V, 48V, high-voltage DC bus), reserve a rated voltage withstand margin of ≥60% to handle massive transient spikes and bus ringing caused by GPU load steps.
Ultra-Low Loss Priority: Prioritize devices with extremely low Rds(on) to minimize conduction loss under multi-hundred-ampere currents, and low Qg/Qoss to reduce switching loss at high frequencies (200kHz-1MHz), directly improving PSU efficiency and reducing thermal stress.
Package & Thermal Matching: Choose packages with ultra-low thermal resistance (e.g., TO-247-4L, TO263) and excellent current capability for GPU VRM and primary side stages. Select compact packages (DFN, SOT) for point-of-load (POL) and control circuits, balancing power density and manufacturability.
High Reliability & Ruggedness: Meet 24/7 data center operation requirements, focusing on high junction temperature capability (≥175°C), strong avalanche energy rating, and excellent gate oxide integrity to withstand harsh electrical environments.
(B) Scenario Adaptation Logic: Categorization by Power Stage
Divide server power stages into three core scenarios: First, GPU Voltage Regulator Module (VRM) and Primary Side Conversion, requiring the highest current handling and efficiency. Second, High-Current Auxiliary & Fan Drive, requiring robust switching for cooling and support systems. Third, Control, Isolation & Protection Circuits, requiring precise on/off control and fault isolation for system safety and management.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: GPU VRM & High-Current DC-DC Conversion – The Power Core
Multi-phase GPU VRMs (supporting 8 high-end GPUs) require handling continuous currents exceeding 1000A in aggregate, with extreme di/dt transients. Devices must offer ultra-low Rds(on) and optimized switching characteristics.
Recommended Model: VBGL1105 (Single-N, 100V, 125A, TO263)
Parameter Advantages: Utilizing advanced SGT technology, it achieves an ultra-low Rds(on) of 4mΩ at 10V. A continuous current rating of 125A (with high peak capability) is ideal for synchronous buck converter low-side or high-side applications in 48V intermediate bus architectures. The TO263 (D2PAK) package offers excellent power dissipation and is suitable for automated assembly.
Adaptation Value: Dramatically reduces conduction loss in multi-phase VRMs. For a 100A per-phase application, conduction loss can be below 4W per device, enabling VRM efficiency >94% at full load. Supports high-frequency multiphase operation, reducing the required output capacitance and improving transient response.
Selection Notes: Must be used in conjunction with a high-performance multiphase PWM controller. Careful PCB layout with a minimized high-current loop is critical. Parallel connection may be required for the highest current phases. Adequate heatsinking is mandatory.
(B) Scenario 2: High-Current Auxiliary Switching & Fan Drive – Support & Cooling
This includes control of server fan arrays (requiring high startup current) and switching for high-power auxiliary rails, demanding a balance of current capability, voltage rating, and ruggedness.
Recommended Model: VBM2625 (Single-P, -60V, -50A, TO220)
Parameter Advantages: A robust P-Channel MOSFET with Rds(on) as low as 19mΩ at 10V and a continuous drain current of -50A. The -60V drain-source voltage is suitable for high-side switching on 12V or 48V rails. The TO220 package provides a good balance of cost, current handling, and ease of heatsinking.
Adaptation Value: Excellent for high-side load switches controlling fan banks or auxiliary power modules. Its low Rds(on) minimizes voltage drop and power loss. The P-Channel configuration simplifies gate driving for high-side switches compared to N-Channel with bootstrap circuits.
Selection Notes: Verify the inrush current of the load (e.g., fan startup). Ensure the gate driver can provide sufficient sink current for fast turn-off. A TO220 package requires proper mounting to a chassis or heatsink for high continuous current operation.
(C) Scenario 3: Control, Protection & Point-of-Load (POL) Switching – System Intelligence
This encompasses low-voltage POL converters, hot-swap circuits, and safety isolation switches for various controller boards and sensors, requiring compact size, good efficiency, and logic-level compatibility.
Recommended Model: VBQD3222U (Dual-N+N, 20V, 6A per channel, DFN8(3x2)-B)
Parameter Advantages: A dual N-Channel MOSFET in a compact DFN package, saving significant PCB area. Features a low gate threshold (Vth) of 0.5-1.5V, making it directly drivable by 3.3V/5V MCU GPIO pins. Rds(on) is as low as 22mΩ at 4.5V Vgs.
Adaptation Value: Perfect for space-constrained POL switching, dual-channel load sharing, or as a synchronous switch in low-voltage DC-DC circuits. Enables intelligent power sequencing and granular power gating for different server components, reducing standby power.
Selection Notes: Keep load current well within the 6A per-channel rating, considering thermal limits of the small package. A minimal copper pad under the DFN package is necessary for heat dissipation. Use gate series resistors to dampen ringing in fast-switching control circuits.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBGL1105: Requires a dedicated high-current gate driver (e.g., 2A-4A source/sink capability) to achieve fast switching and minimize crossover loss. Proper gate resistor selection is critical to manage EMI and dv/dt.
VBM2625: Can be driven by a standard gate driver IC or a discrete bipolar stage. Ensure fast turn-off to prevent shoot-through in bridge configurations. A pull-up resistor on the gate is typically needed.
VBQD3222U: Can be driven directly by MCU pins for moderate speeds. For faster switching, a small buffer (e.g., transistor array) is recommended. Pay close attention to PCB trace inductance due to the high-speed switching loops.
(B) Thermal Management Design: Tiered and Aggressive Cooling
VBGL1105: Demands aggressive cooling. Mount on a dedicated heatsink attached to the server's thermal management system (cold plate or high-airflow zone). Use thermal interface material (TIM) of high quality. Extensive PCB copper pour with multiple thermal vias is essential.
VBM2625: Requires a heatsink for continuous high-current operation. The TO220 package allows for easy attachment to a chassis bar or a dedicated extruded heatsink.
VBQD3222U: Relies on PCB-level cooling. Provide a generous copper pad underneath the package connected to internal ground planes via thermal vias. Ensure adequate airflow over the board.
(C) EMC and Reliability Assurance
EMC Suppression: For VBGL1105 in VRM, use low-ESR/ESL input capacitors very close to the drain-source connection. Consider adding small RC snubbers across the drain-source of the high-side device to dampen high-frequency ringing. For VBM2625 controlling inductive fans, use flyback diodes or TVS for protection.
Reliability Protection:
Derating: Apply conservative derating. Operate VBGL1105 at ≤70-80% of its current rating under worst-case temperature.
Overcurrent Protection (OCP): Implement precise OCP at the VRM controller level. For discrete switches like VBM2625, use a current-sense amplifier or a fuse.
Transient Protection: Use TVS diodes on all power input lines and gate pins. Implement proper input filtering to suppress line-borne surges.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Power Density and Efficiency: The combination of ultra-low Rds(on) SGT/SiC devices and compact dual MOSFETs enables high-efficiency, high-frequency power conversion, allowing for more compact PSU designs and higher GPU power budgets.
Enhanced System Control and Safety: Granular control via logic-level MOSFETs enables advanced power management, while robust high-current devices ensure reliable operation under heavy computational loads.
Scalable and Serviceable Design: The use of standard, well-characterized packages (TO263, TO220, DFN) facilitates design scalability, testing, and potential field service.
(B) Optimization Suggestions
For Highest Efficiency (>98% Peak) in 48V-12V/1.xV Conversion: Consider pairing VBGL1105 with a SiC MOSFET (like VBP112MC50-4L for the primary side in isolated topologies) to minimize total system loss.
For Space-Critical POL Applications: For higher current needs in POL, consider the VBGE1102N (100V, 35A, TO252) as a robust alternative in a slightly larger package than DFN.
For Redundant Power & Hot-Swap Control: The P-Channel VBJ2456 (-40V, -6.2A, SOT223) offers a very compact solution for board-level hot-swap or OR-ing functions.
Special High-Voltage Applications: For PFC or offline auxiliary power supplies within the server PSU, the VBMB18R05S (800V, 5A, SJ_Multi-EPI) provides a cost-effective high-voltage solution.
Conclusion
Strategic MOSFET selection is paramount to unlocking the full performance potential of 8-GPU AI training servers, where power delivery is a key bottleneck. This scenario-adapted strategy provides a roadmap for optimizing efficiency, power density, and reliability through careful device matching and robust system design. Future evolution will involve deeper integration of wide-bandgap (SiC/GaN) devices and smart power stages to meet the ever-increasing power demands of next-generation AI hardware.

Detailed Topology Diagrams