Energy Management

Your present location > Home page > Energy Management
Practical Design of the Power Chain for High-End Modular UPS Systems: Balancing Power Density, Efficiency, and Reliability
High-End Modular UPS Power Chain Topology Diagram

High-End Modular UPS System Overall Power Chain Topology Diagram

graph TD %% Main Power Flow Section subgraph "Three-Phase Input & Rectification" AC_IN["Three-Phase 380VAC Input"] --> EMI_FILTER["EMI Filter & Surge Protection"] EMI_FILTER --> RECTIFIER["Three-Phase Rectifier Bridge"] RECTIFIER --> PFC_CIRCUIT["PFC Boost Circuit"] end subgraph "Main Inverter Section (Three-Level NPC/T-Type)" PFC_CIRCUIT --> DC_BUS["High-Voltage DC Bus
700-800VDC"] subgraph "Three-Level Inverter Phase Leg" Q_TOP["VBP16I25
650V/25A IGBT+FRD"] Q_MID1["VBP16I25
650V/25A IGBT+FRD"] Q_MID2["VBP16I25
650V/25A IGBT+FRD"] Q_BOT["VBP16I25
650V/25A IGBT+FRD"] end DC_BUS --> Q_TOP Q_TOP --> OUTPUT_NODE_A["Output Node A"] Q_MID1 --> OUTPUT_NODE_A OUTPUT_NODE_A --> Q_MID2 Q_MID2 --> NEUTRAL_POINT["Neutral Point
DC Bus Midpoint"] Q_BOT --> NEUTRAL_POINT NEUTRAL_POINT --> OUTPUT_FILTER["Output LCL Filter"] OUTPUT_FILTER --> AC_OUT["Three-Phase 380VAC Output"] AC_OUT --> CRITICAL_LOAD["Critical Load
(Servers, Equipment)"] end %% DC-DC Conversion & Battery Management subgraph "DC-DC Converter & Battery Management" BATTERY_BANK["48V Battery Bank"] --> ORING_MOSFETS["ORing/Backfeed Protection"] subgraph "High-Current ORing MOSFET Array" Q_ORING1["VBGQA1301
30V/170A SGT MOSFET"] Q_ORING2["VBGQA1301
30V/170A SGT MOSFET"] Q_ORING3["VBGQA1301
30V/170A SGT MOSFET"] end ORING_MOSFETS --> Q_ORING1 ORING_MOSFETS --> Q_ORING2 ORING_MOSFETS --> Q_ORING3 Q_ORING1 --> DC_DC_CONVERTER["High-Efficiency DC-DC Converter"] Q_ORING2 --> DC_DC_CONVERTER Q_ORING3 --> DC_DC_CONVERTER DC_DC_CONVERTER --> INTERMEDIATE_BUS["Intermediate DC Bus"] INTERMEDIATE_BUS --> PFC_CIRCUIT INTERMEDIATE_BUS --> AUX_POWER["Auxiliary Power Supplies"] end %% Control & Management System subgraph "Intelligent Control & Power Management" MAIN_CONTROLLER["Main System Controller/DSP"] --> GATE_DRIVERS["Isolated Gate Drivers"] GATE_DRIVERS --> Q_TOP GATE_DRIVERS --> Q_MID1 GATE_DRIVERS --> Q_MID2 GATE_DRIVERS --> Q_BOT subgraph "Auxiliary Power Management" FAN_CTRL["VBG3638 Fan Control"] MODULE_SW["VBL1310 Hot-Swap Control"] AUX_SW["VBL1310 Auxiliary Rail Switching"] end MAIN_CONTROLLER --> FAN_CTRL MAIN_CONTROLLER --> MODULE_SW MAIN_CONTROLLER --> AUX_SW FAN_CTRL --> COOLING_FANS["Cooling Fans"] MODULE_SW --> MODULE_BUS["Modular Unit Bus"] AUX_SW --> CONTROL_CIRCUITS["Control & Monitoring Circuits"] end %% Protection & Monitoring Circuits subgraph "Protection & Safety Systems" OVERVOLTAGE["Overvoltage Protection"] --> FAULT_LATCH["Fault Latch Circuit"] OVERCURRENT["Overcurrent Sensing"] --> FAULT_LATCH OVERTEMP["Overtemperature Sensors"] --> FAULT_LATCH FAULT_LATCH --> SHUTDOWN_SIGNAL["System Shutdown Signal"] SHUTDOWN_SIGNAL --> GATE_DRIVERS subgraph "Snubber & Clamping Circuits" RCD_SNUBBER["RCD Snubber Networks"] TVS_ARRAY["TVS Protection Array"] ACTIVE_INRUSH["Active Inrush Limiting"] end RCD_SNUBBER --> Q_TOP TVS_ARRAY --> GATE_DRIVERS ACTIVE_INRUSH --> BATTERY_BANK end %% Thermal Management System subgraph "Three-Level Thermal Management" LEVEL1["Level 1: Forced Air Cooling"] --> HEATSINK_IGBT["Common Heatsink"] HEATSINK_IGBT --> Q_TOP HEATSINK_IGBT --> Q_MID1 HEATSINK_IGBT --> Q_MID2 HEATSINK_IGBT --> Q_BOT LEVEL2["Level 2: PCB-Conducted Cooling"] --> THERMAL_VIAS["Thermal Via Arrays"] THERMAL_VIAS --> Q_ORING1 THERMAL_VIAS --> Q_ORING2 THERMAL_VIAS --> Q_ORING3 LEVEL3["Level 3: Ambient Airflow Cooling"] --> PCB_SURFACE["PCB Surface Area"] PCB_SURFACE --> FAN_CTRL PCB_SURFACE --> MODULE_SW PCB_SURFACE --> AUX_SW end %% Communication & Monitoring MAIN_CONTROLLER --> CAN_BUS["CAN Communication Bus"] MAIN_CONTROLLER --> ETHERNET["Ethernet Interface"] MAIN_CONTROLLER --> PREDICTIVE_AI["AI Predictive Health Management"] %% Style Definitions style Q_TOP fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_ORING1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style FAN_CTRL fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MAIN_CONTROLLER fill:#fce4ec,stroke:#e91e63,stroke-width:2px

As high-end modular UPS systems evolve towards higher power density, greater efficiency, and unmatched reliability, their internal power conversion and management subsystems are no longer simple backup units. Instead, they are the core determinants of system performance, energy savings, and total cost of ownership. A well-designed power chain is the physical foundation for these systems to achieve seamless transition, high-efficiency operation, and long-lasting durability under stringent commercial and industrial conditions.
However, building such a chain presents multi-dimensional challenges: How to balance ultra-high efficiency with thermal management and system cost? How to ensure the long-term reliability of power semiconductors in 24/7 continuous operation with varying loads? How to seamlessly integrate advanced topology, thermal management, and intelligent paralleling control? The answers lie within every engineering detail, from the selection of key components to system-level integration.
I. Three Dimensions for Core Power Component Selection: Coordinated Consideration of Voltage, Current, and Topology
1. Main Inverter/Converter IGBT: The Core of Power Processing and Efficiency
The key device is the VBP16I25 (650V/25A/TO-247, IGBT+FRD), whose selection requires deep technical analysis.
Voltage Stress and Topology Relevance: For three-phase UPS systems with 380VAC input/output, the DC bus voltage typically operates around 700-800VDC. A 650V IGBT is optimally suited for this voltage class in advanced three-level (T-Type or NPC) topologies, which are standard in high-end UPS for reduced filter size and higher efficiency. Using it in the neutral point clamped or switch position requires careful evaluation of voltage sharing and dynamic stress.
Dynamic Characteristics and Loss Optimization: The specified VCEsat of 1.9V @15V is critical for conduction loss at the typical high switching frequencies (16kHz-20kHz) used in UPS inverters to minimize audio noise and output filter size. The integrated Fast Recovery Diode (FRD) is essential for handling reactive power flow and ensuring robust performance during rectifier/regenerative modes.
Thermal Design for Continuous Operation: In a modular UPS, parallel operation is common. The TO-247 package must be mounted on a common heatsink with forced air cooling. Thermal calculations must ensure the junction temperature remains below 125°C at maximum ambient temperature and full load, considering both conduction and switching losses: Tj = Tc + (P_cond + P_sw) × Rθjc.
2. DC-DC Converter/Battery Charger MOSFET: The Backbone of Internal Bus and Battery Management
The key device selected is the VBGQA1301 (30V/170A/DFN8(5x6), SGT MOSFET), whose impact on power density and efficiency is transformative.
Efficiency and Power Density Enhancement: This device is ideal for critical intermediate bus converters (e.g., converting a 48V battery bank to a stable high-voltage DC bus) or high-current ORing/backfeed protection circuits. Its ultra-low RDS(on) of 0.97mΩ @10V virtually eliminates conduction loss, enabling efficiencies exceeding 98%. The compact DFN8 package offers an unparalleled power density, allowing for more compact and higher power modules.
Drive and Layout Considerations for Ultra-Low Inductance: The extremely fast switching capability of this SGT MOSFET demands a low-inductance layout. A dedicated driver IC placed very close to the gate, use of a Kelvin source connection (if applicable), and a minimized power loop with multilayer PCBs are mandatory. Careful gate resistor selection balances switching speed with EMI.
3. System Control and Auxiliary Power MOSFET: The Execution Unit for Intelligent Power Routing
The key device is the VBL1310 (30V/50A/TO-263, Trench MOSFET), enabling reliable and efficient low-voltage power distribution.
Typical Load Management Logic: Used in system control circuits for fan speed control (PWM), hot-swap control of modular units, and switching of auxiliary power rails within the control logic. Its robust TO-263 package is easier to handle in assembly than smaller DFN packages for these ancillary functions, while still offering excellent power handling.
Performance Balance: With an RDS(on) of 12mΩ @10V, it provides an excellent balance between low conduction loss and cost for these auxiliary functions. The higher voltage rating (30V) provides ample margin in 12V or 24V control systems, enhancing reliability against transients.
II. System Integration Engineering Implementation
1. Hierarchical Thermal Management Architecture
A multi-level cooling approach is essential for reliability.
Level 1: Forced Air Cooling on Common Heatsink: Targets the VBP16I25 IGBTs and other primary switches. Design involves an extruded aluminum heatsink with optimized fin density, coupled with speed-controlled fans based on load and temperature.
Level 2: PCB-Conducted Cooling: For high-density devices like the VBGQA1301 in DFN8. Implementation requires extensive thermal vias under the device's thermal pad, connected to large internal copper planes or an attached baseplate.
Level 3: Ambient Airflow Cooling: For devices like the VBL1310 in TO-263, which can be cooled by the general system airflow over the control PCB.
2. Electromagnetic Compatibility (EMC) and Safety Design
Conducted and Radiated EMI Suppression: Employ interleaved PFC/Inverter topologies to reduce input current harmonics. Use a combination of common-mode and differential-mode chokes, along with X/Y capacitors. For the high-frequency switching of the VBGQA1301, proper snubber design and shielding of magnetic components are critical.
Safety and Reliability Design: Implement comprehensive protection: DC bus over/under voltage, output short-circuit, overload, and overtemperature. Use isolated gate drivers for the primary IGBTs. Incorporate current sharing control for parallel modules to ensure equal stress on all power devices, including the VBGQA1301 in ORing circuits.
3. Reliability Enhancement Design
Electrical Stress Protection: Utilize RCD snubbers across the IGBTs to clamp turn-off voltage spikes. Implement active inrush current limiting for the battery charger circuits using MOSFETs like the VBL1310. Ensure all relay and contactor coils have flyback diodes.
Predictive Diagnostics: Monitor heatsink temperature near critical devices. Advanced systems can track the forward voltage drop of the IGBT (VCEsat) during a known test pulse to estimate health degradation.
III. Performance Verification and Testing Protocol
1. Key Test Items and Standards
Efficiency Test: Measure efficiency across the entire load spectrum (10%-100%) per IEC 62040-3, focusing on both normal and ECO modes.
Thermal Cycling and Burn-in Test: Operate at full load in a high-temperature chamber (e.g., 40°C ambient) for extended periods to validate thermal design and identify early failures.
Input Line and Output Load Transient Tests: Verify dynamic response and stability when facing abrupt input voltage changes or step load changes from 0-100%-0.
EMC Compliance Test: Must meet IEC/EN 62040-2 for both emissions and immunity.
2. Design Verification Example
Test data from a 50kVA modular UPS module (DC Bus: 800V, Input/Output: 400VAC 3PH) shows:
System peak efficiency (double conversion mode) reached 96.8%, with >96% efficiency maintained from 30% to 100% load.
Battery charger stage (utilizing VBGQA1301-based converters) efficiency exceeded 97%.
Key Point Temperature Rise: At 40°C ambient and full resistive load, IGBT heatsink temperature stabilized at 72°C. Critical PCB hotspot near DC-DC converters was 85°C.
Seamless transition times during bypass/online transfers were <2ms.
IV. Solution Scalability
1. Adjustments for Different Power Ratings and Topologies
Medium Power Modules (10-30kVA): Can utilize the VBP16I25 IGBTs in a standard two-level inverter topology for cost optimization.
High Power Modules (50-100kVA+): The same VBP16I25 can be used in parallel within a module or as part of a three-level topology. For higher current, modules with higher current IGBTs would be selected, but the design philosophy remains.
Internal DC-DC Stages: The VBGQA1301 platform is scalable by paralleling devices for higher current intermediate buses or battery currents.
2. Integration of Cutting-Edge Technologies
Wide Bandgap (SiC/GaN) Technology Roadmap: While current designs use optimized Si IGBTs and MOSFETs, future evolution involves:
Phase 1 (Next Generation): Introduce SiC MOSFETs in the PFC/Boost stage to drastically reduce losses and increase power density.
Phase 2 (Future): Migrate the main inverter to SiC devices, enabling higher switching frequencies, reduced filter size, and potentially higher efficiency points, especially at low loads.
AI-Driven Predictive Health Management: Utilize operational data (load profiles, temperature trends, switching device on-state resistance estimates) to predict capacitor aging, fan failure, and potential power device degradation, enabling proactive service.
Conclusion
The power chain design for high-end modular UPS systems is a multi-dimensional systems engineering task, requiring a balance among power density, conversion efficiency, 24/7 reliability, serviceability, and total cost of ownership. The tiered optimization scheme proposed—employing topology-optimized IGBTs at the main power conversion level, utilizing ultra-low-loss SGT MOSFETs at the critical DC-DC conversion level, and leveraging robust Trench MOSFETs for intelligent system control—provides a clear and scalable implementation path for next-generation UPS platforms.
As data center infrastructure demands greater efficiency and intelligence, future UPS power management will trend towards deeper digital control, interoperability, and the adoption of Wide Bandgap semiconductors. It is recommended that engineers adhere to international safety and performance standards within this framework, while strategically planning for the integration of SiC technology and AI-enhanced lifecycle management.
Ultimately, excellent UPS power design is foundational. It operates invisibly behind the server racks, yet it creates immense value for operators through maximized uptime, minimized energy costs, reduced cooling overhead, and extended service life. This is the true value of engineering precision in powering the digital world.

Detailed Topology Diagrams

Three-Level NPC/T-Type Inverter Topology Detail

graph LR subgraph "Three-Level NPC/T-Type Phase Leg" DC_POS["DC Bus Positive (+)"] --> Q1["VBP16I25 IGBT+FRD"] Q1 --> OUTPUT["AC Output Phase"] DC_POS --> Q2["VBP16I25 IGBT+FRD"] Q2 --> NEUTRAL["Neutral Point"] NEUTRAL --> Q3["VBP16I25 IGBT+FRD"] Q3 --> OUTPUT NEUTRAL --> Q4["VBP16I25 IGBT+FRD"] Q4 --> DC_NEG["DC Bus Negative (-)"] OUTPUT --> CLAMP_DIODES["Clamping Diodes"] CLAMP_DIODES --> NEUTRAL end subgraph "Gate Driving & Protection" CONTROLLER["PWM Controller"] --> ISOLATED_DRIVER["Isolated Gate Driver"] ISOLATED_DRIVER --> Q1_GATE["Gate Drive Signals"] ISOLATED_DRIVER --> Q2_GATE["Gate Drive Signals"] ISOLATED_DRIVER --> Q3_GATE["Gate Drive Signals"] ISOLATED_DRIVER --> Q4_GATE["Gate Drive Signals"] Q1_GATE --> Q1 Q2_GATE --> Q2 Q3_GATE --> Q3 Q4_GATE --> Q4 subgraph "Voltage Clamping" RCD_CLAMP["RCD Snubber Circuit"] TVS_PROTECTION["TVS Array"] end RCD_CLAMP --> Q1 RCD_CLAMP --> Q4 TVS_PROTECTION --> ISOLATED_DRIVER end subgraph "Current Sensing & Feedback" CURRENT_SENSOR["Hall-Effect Current Sensor"] --> SIGNAL_COND["Signal Conditioning"] SIGNAL_COND --> ADC["ADC Input"] ADC --> CONTROLLER OUTPUT --> CURRENT_SENSOR end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q2 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

DC-DC Converter & ORing Protection Topology Detail

graph LR subgraph "Battery ORing/Backfeed Protection Circuit" BAT_POS["Battery Positive (+)"] --> ORING_NODE["ORing Node"] BAT_NEG["Battery Negative (-)"] --> COMMON_GND["Common Ground"] subgraph "Parallel ORing MOSFETs" Q_OR1["VBGQA1301
SGT MOSFET"] Q_OR2["VBGQA1301
SGT MOSFET"] Q_OR3["VBGQA1301
SGT MOSFET"] end ORING_NODE --> Q_OR1 ORING_NODE --> Q_OR2 ORING_NODE --> Q_OR3 Q_OR1 --> LOAD_NODE["Load Node"] Q_OR2 --> LOAD_NODE Q_OR3 --> LOAD_NODE LOAD_NODE --> CURRENT_SHARING["Current Sharing Control"] CURRENT_SHARING --> Q_OR1_GATE["Gate Control"] CURRENT_SHARING --> Q_OR2_GATE["Gate Control"] CURRENT_SHARING --> Q_OR3_GATE["Gate Control"] end subgraph "High-Efficiency DC-DC Converter" LOAD_NODE --> BUCK_CONVERTER["Synchronous Buck Converter"] subgraph "Converter Power Switches" Q_HIGH["VBGQA1301 High-Side"] Q_LOW["VBGQA1301 Low-Side"] end BUCK_CONVERTER --> Q_HIGH BUCK_CONVERTER --> Q_LOW Q_HIGH --> SW_NODE["Switching Node"] Q_LOW --> SW_NODE SW_NODE --> OUTPUT_INDUCTOR["Output Inductor"] OUTPUT_INDUCTOR --> OUTPUT_CAP["Output Capacitors"] OUTPUT_CAP --> HIGH_VOLTAGE_BUS["High-Voltage DC Bus"] end subgraph "Thermal Management & Layout" THERMAL_PAD["DFN8 Thermal Pad"] --> THERMAL_VIAS["Thermal Via Array"] THERMAL_VIAS --> INNER_LAYERS["Inner Copper Layers"] INNER_LAYERS --> BASE_PLATE["Metal Baseplate"] subgraph "Low-Inductance Layout" GATE_DRIVER["Dedicated Driver IC"] KELVIN_CONN["Kelvin Source Connection"] MIN_LOOP["Minimized Power Loop"] end GATE_DRIVER --> Q_OR1_GATE GATE_DRIVER --> Q_HIGH_GATE["High-Side Gate"] KELVIN_CONN --> Q_OR1 MIN_LOOP --> Q_HIGH MIN_LOOP --> Q_LOW end style Q_OR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_HIGH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Control System & Auxiliary Power Management Topology Detail

graph LR subgraph "Main Control System Architecture" DSP_MCU["Main DSP/MCU Controller"] --> PWM_GENERATION["PWM Generation Module"] DSP_MCU --> ADC_INTERFACE["ADC Interface"] DSP_MCU --> COMMUNICATION["Communication Interfaces"] PWM_GENERATION --> ISOLATION["Digital Isolators"] ISOLATION --> GATE_DRIVERS["Gate Driver ICs"] ADC_INTERFACE --> VOLTAGE_SENSING["Voltage Sensing"] ADC_INTERFACE --> CURRENT_SENSING["Current Sensing"] ADC_INTERFACE --> TEMP_MONITORING["Temperature Monitoring"] COMMUNICATION --> CAN_MODULE["CAN Bus"] COMMUNICATION --> ETHERNET_PHY["Ethernet PHY"] COMMUNICATION --> MODBUS["Modbus RTU"] end subgraph "Auxiliary Power Distribution & Switching" AUX_12V["12V Auxiliary Rail"] --> SWITCHING_NODE["Switching Node"] subgraph "Load Switch Channels" FAN_SWITCH["VBL1310
Fan PWM Control"] HOTSWAP_SW["VBL1310
Hot-Swap Control"] AUX_SWITCH["VBL1310
Auxiliary Rail Switch"] end SWITCHING_NODE --> FAN_SWITCH SWITCHING_NODE --> HOTSWAP_SW SWITCHING_NODE --> AUX_SWITCH FAN_SWITCH --> FAN_LOAD["Cooling Fan Load"] HOTSWAP_SW --> MODULE_CONN["Module Connection"] AUX_SWITCH --> SENSORS_ICS["Sensors & ICs"] FAN_LOAD --> SYSTEM_GND MODULE_CONN --> SYSTEM_GND SENSORS_ICS --> SYSTEM_GND end subgraph "Protection & Monitoring Circuits" subgraph "Fault Detection" OVERVOLTAGE_CIRCUIT["Overvoltage Comparator"] OVERCURRENT_CIRCUIT["Overcurrent Comparator"] OVERTEMP_CIRCUIT["Overtemperature Comparator"] end VOLTAGE_SENSING --> OVERVOLTAGE_CIRCUIT CURRENT_SENSING --> OVERCURRENT_CIRCUIT TEMP_MONITORING --> OVERTEMP_CIRCUIT OVERVOLTAGE_CIRCUIT --> FAULT_LOGIC["Fault Logic OR Gate"] OVERCURRENT_CIRCUIT --> FAULT_LOGIC OVERTEMP_CIRCUIT --> FAULT_LOGIC FAULT_LOGIC --> SHUTDOWN_CTRL["Shutdown Control"] SHUTDOWN_CTRL --> GATE_DRIVERS SHUTDOWN_CTRL --> FAN_SWITCH end subgraph "Predictive Health Monitoring" HEALTH_MONITOR["Health Monitoring Module"] --> VCE_MONITOR["IGBT VCE(sat) Monitoring"] HEALTH_MONITOR --> CAP_AGING["Capacitor Aging Estimation"] HEALTH_MONITOR --> FAN_LIFE["Fan Life Prediction"] VCE_MONITOR --> Q1["Main IGBTs"] CAP_AGING --> DC_BUS_CAPS["DC Bus Capacitors"] FAN_LIFE --> FAN_LOAD HEALTH_MONITOR --> AI_ENGINE["AI Analysis Engine"] AI_ENGINE --> PREDICTIVE_ALERTS["Predictive Maintenance Alerts"] end style FAN_SWITCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style DSP_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px
Download PDF document
Download now:VBP16I25

Sample Req

Online

Telephone

400-655-8788

WeChat

Topping

Sample Req
Online
Telephone
WeChat