With the rapid development of fast charging technology and the increasing demand for seamless power delivery, wireless charging devices have become pivotal in consumer electronics and automotive applications. The power conversion and management systems, serving as the core of energy transfer, require precise control for key functions such as the primary-side inverter, secondary-side synchronous rectifier, and load switching. The selection of power MOSFETs directly determines the system's efficiency, thermal performance, power density, and charging safety. Addressing the stringent requirements for high efficiency, compact size, thermal stability, and robust communication, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy for wireless charging systems. I. Core Selection Principles and Scenario Adaptation Logic (A) Core Selection Principles: Four-Dimensional Collaborative Adaptation MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with the unique operating conditions of wireless charging: Sufficient Voltage Margin: For common input voltages (5V/9V/12V/15V/20V) and resonant tank operation, reserve a rated voltage withstand margin of ≥60% to handle high-voltage ringing and switching spikes. For example, prioritize devices with ≥60V for a 20V input system. Prioritize Low Loss: Prioritize devices with extremely low Rds(on) (minimizing conduction loss) and excellent Figure of Merit (FOM, Qg Rds(on)) (minimizing switching loss), adapting to high-frequency (100kHz-1MHz+) operation to maximize efficiency and power density. Package & Integration Matching: Choose thermally efficient packages like DFN for high-current paths (primary switches, sync rectifiers). Select compact, multi-channel packages like SOT23-6 for load switches and communication interface control, balancing space savings and layout complexity. Reliability Redundancy: Meet continuous operation and fast-charging thermal cycles, focusing on low thermal resistance, robust ESD protection, and a wide safe operating area (SOA). (B) Scenario Adaptation Logic: Categorization by Circuit Function Divide the application into three core scenarios based on circuit function: First, the Primary-Side Power Stage (Transmitter Inverter), requiring high-voltage, high-efficiency, and fast-switching devices. Second, the Secondary-Side Synchronous Rectifier (Receiver), requiring very low Rds(on) for minimal conduction loss. Third, Load Management & System Control, requiring low-power, space-saving, and multi-channel devices for intelligent power routing and protection. II. Detailed MOSFET Selection Scheme by Scenario (A) Scenario 1: Primary-Side Full/Half-Bridge Inverter (15W-100W+) – Power Core Device The inverter stage converts DC to high-frequency AC for the transmitter coil. It must handle high voltage stresses, high peak currents, and operate at high frequencies with minimal loss. Recommended Model: VBGQF1610 (Single N-MOS, 60V, 35A, DFN8(3x3)) Parameter Advantages: Advanced SGT technology achieves an ultra-low Rds(on) of 11.5mΩ at 10V. The 60V rating provides ample margin for 20V input systems. The 35A continuous current rating supports high-power applications. The DFN8 package offers excellent thermal performance (low RthJA) and very low parasitic inductance, critical for high-frequency switching and heat dissipation. Adaptation Value: Dramatically reduces both conduction and switching losses. Enables system efficiency >94% in high-power fast-charging scenarios. Supports high-frequency operation (up to several hundred kHz), allowing for smaller magnetics and higher power density. Selection Notes: Verify maximum input voltage and peak resonant current. Ensure gate driver capability (2A+ peak) to swiftly charge/discharge the gate. Implement a dedicated, low-inductance power loop layout with sufficient copper pour (≥150mm²) for heat dissipation. (B) Scenario 2: Secondary-Side Synchronous Rectifier (15W-100W+) – Efficiency-Critical Device The synchronous rectifier (SR) on the receiver side replaces diodes to minimize forward voltage drop, directly boosting overall efficiency. It requires extremely low Rds(on). Recommended Model: VB3222A (Dual N+N MOS, 20V, 6A per channel, SOT23-6) Parameter Advantages: Exceptionally low Rds(on) of 22mΩ at 10V per channel. The 20V rating is perfectly suited for rectified outputs up to 15V. The dual N-channel configuration in a tiny SOT23-6 package allows for a compact, high-efficiency center-tap or full-wave SR bridge. Adaptation Value: Eliminates the ~0.3V-0.4V diode drop, reducing rectification loss by over 70% compared to Schottky diodes. Crucial for achieving high receiver efficiency (>95%) and low thermal footprint in space-constrained receiver modules. Selection Notes: Can be driven by a dedicated SR controller or a comparator-based circuit. Ensure proper dead-time control to prevent shoot-through. The compact package requires attention to PCB thermal design for continuous high-current operation. (C) Scenario 3: Load Switch & Communication Power Control – System Management Device This involves intelligently enabling/disabling power paths to different modules (e.g., MCU, communication ICs like BLE/Qi protocol) and providing over-load protection. Recommended Model: VBQG4338 (Dual P+P MOS, -30V, -5.4A per channel, DFN6(2x2)-B) Parameter Advantages: Integrated dual P-channel in a miniature DFN6 package saves significant PCB area. -30V rating is robust for 5V/12V load switching. Low Rds(on) of 38mΩ at 10V ensures minimal voltage drop. P-channel allows easy high-side switching controlled by a low-voltage MCU GPIO (with a level shifter). Adaptation Value: Enables independent, low-loss switching of multiple system rails (e.g., MCU power, comms power). Facilitates advanced power saving modes by shutting down unused blocks. The integrated dual switch simplifies design and reduces component count. Selection Notes: Calculate the voltage drop at full load current to ensure it meets downstream IC requirements. A simple NPN or N-MOSFET can be used for gate driving. Add a small decoupling capacitor near the load side. III. System-Level Design Implementation Points (A) Drive Circuit Design: Matching Device Characteristics VBGQF1610 (Primary Inverter): Pair with a dedicated half/full-bridge driver IC (e.g., IRS2104, LM5113) with peak current capability >2A. Use a gate resistor (2-10Ω) to tune switching speed and control EMI. VB3222A (Sync Rectifier): Optimal when driven by a dedicated synchronous rectifier controller IC for precise timing. If using a self-driven scheme, ensure the gate drive voltage is sufficient and add snubbers for voltage spike protection. VBQG4338 (Load Switch): Can be driven directly from an MCU GPIO via a small NPN transistor (e.g., MMBT3904) for level shifting. Include a pull-up resistor on the gate. (B) Thermal Management Design: Tiered Approach VBGQF1610: Primary heat source. Use a generous copper pour (≥150mm²) on the drain pad with multiple thermal vias to inner layers or a ground plane. Consider a thermal interface material if the PCB is attached to a chassis. VB3222A: Heat is concentrated in a small package. Ensure the PCB pads are extended into small copper areas (≥30mm²) with thermal vias. Avoid placing heat-sensitive components nearby. VBQG4338: Provide symmetrical copper pads for both channels. A modest copper area (≥50mm² total) is typically sufficient due to lower average current. (C) EMC and Reliability Assurance EMC Suppression: Primary Side (VBGQF1610): Use an RC snubber across the drain-source of each switch to damp high-frequency ringing. Ensure a tight, low-inductance layout for the switching loop. Secondary Side (VB3222A): Place input and output filter capacitors very close to the MOSFETs. General: Implement proper input EMI filtering. Use ferrite beads on sensitive control lines. Reliability Protection: Overvoltage: Place TVS diodes (e.g., SMAJ series) at the input and on the rectified output. Overcurrent: Implement current sensing on the primary side (e.g., sense resistor with comparator) and/or use controllers with integrated cycle-by-cycle current limit. Overtemperature: Use an NTC thermistor on the primary-side PCB or a controller with die temperature monitoring to throttle power or shut down. IV. Scheme Core Value and Optimization Suggestions (A) Core Value End-to-End Efficiency Maximization: The combination of a high-performance primary switch (VBGQF1610) and an ultra-low Rds(on) sync rectifier (VB3222A) pushes overall system efficiency to >93%, even at high power levels, reducing thermal stress and enabling smaller form factors. High Integration and Intelligence: The use of dual-channel devices (VB3222A, VBQG4338) minimizes PCB footprint, freeing up space for additional features like multi-coil designs or enhanced communication modules. Cost-Effective Performance: This selection leverages mature trench and SGT MOSFET technologies, offering superior performance-to-cost ratio suitable for high-volume consumer applications. (B) Optimization Suggestions Power Scaling: For ultra-high-power wireless charging (>100W), consider parallelizing VBGQF1610 or selecting a higher current-rated device. For lower power (<15W), VB3658 (60V, Dual-N) can be a cost-effective choice for the primary side. Voltage Scaling: For systems strictly limited to 5V/9V input, VBB1240 (20V, 6A, SOT23-3) offers an extremely low Rds(on) alternative for secondary-side rectification or load switching. Space-Constrained Receivers: In extremely thin receivers (e.g., wearables), VBK1230N (20V, SC70-3) can serve as a minimalist load switch for micro-power rails. Enhanced Protection: For critical load switches, consider devices with integrated features like VBI1101M (100V rating) for inputs with higher potential voltage transients. Conclusion Strategic MOSFET selection is fundamental to achieving high efficiency, thermal robustness, and miniaturization in modern wireless charging devices. This scenario-based scheme, through precise matching of device characteristics to circuit function, provides a comprehensive roadmap for R&D engineers. Future exploration into integrated driver-MOSFET combos (DrMOS) and advanced wide-bandgap (GaN) devices will further push the boundaries of power density and efficiency, enabling the next generation of truly fast and ubiquitous wireless power.
Detailed Topology Diagrams
Primary Side Inverter Topology Detail (VBGQF1610)
graph LR
subgraph "Full-Bridge Inverter Configuration"
A["DC Input 5V-20V"] --> B["Input Capacitors Low-ESR"]
B --> C["DC Bus"]
subgraph "H-Bridge Switching Network"
C --> D["High-Side Switch Q1"]
D --> E["Switching Node A"]
C --> F["High-Side Switch Q2"]
F --> G["Switching Node B"]
E --> H["Low-Side Switch Q3"]
G --> I["Low-Side Switch Q4"]
H --> J["Ground"]
I --> J
end
subgraph "MOSFET Specifications"
D_spec["Q1/Q2/Q3/Q4: VBGQF1610 60V, 35A, 11.5mΩ DFN8(3x3)"]
end
E --> K["Resonant Tank LC Network"]
G --> K
K --> L["Transmitter Coil Primary Inductance"]
subgraph "Gate Driving Circuit"
M["Gate Driver IC IRS2104/LM5113"] --> N["Gate Resistor 2-10Ω"]
N --> D
N --> F
N --> H
N --> I
O["Bootstrap Circuit"] --> M
end
subgraph "Protection & Sensing"
P["RC Snubber Network"] --> D
P --> F
Q["Current Sense Resistor"] --> R["Comparator/ADC"]
R --> S["Over-Current Protection"]
T["NTC Thermistor"] --> U["Temperature Monitoring"]
end
end
style D_spec fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
Secondary Side Synchronous Rectifier Topology Detail (VB3222A)
graph LR
subgraph "Center-Tap Synchronous Rectifier"
A["Receiver Coil Secondary"] --> B["Center Tap"]
A --> C["AC Terminal 1"]
A --> D["AC Terminal 2"]
subgraph "Dual N-Channel Synchronous Rectifier"
E["VB3222A Channel 1 20V, 6A, 22mΩ"]
F["VB3222A Channel 2 20V, 6A, 22mΩ"]
end
C --> E
D --> F
B --> G["Output Common"]
E --> H["Rectified Output Node"]
F --> H
subgraph "Control Methods"
I["Dedicated SR Controller"] --> J["Precise Timing Control"]
K["Comparator-Based Self-Driven"] --> L["Simple Implementation"]
M["MCU GPIO Controlled"] --> N["Software Timing"]
end
subgraph "Output Filtering"
H --> O["Output Inductor"]
O --> P["Output Capacitors Low-ESR"]
P --> Q["DC Output 5V-15V"]
end
subgraph "Timing & Protection"
R["Dead-Time Control Prevents Shoot-Through"] --> E
R --> F
S["Voltage Spike Protection"] --> E
S --> F
T["Thermal Vias ≥30mm² Copper"] --> E
T --> F
end
end
style E fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
style F fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
Load Management & Power Control Topology Detail (VBQG4338)
graph LR
subgraph "Intelligent Load Switching System"
A["System Power Rail 5V/12V"] --> B["Input Protection"]
B --> C["Load Switch Input"]
subgraph "Dual P-Channel Load Switch"
D["VBQG4338 Dual P+P MOSFET -30V, -5.4A, 38mΩ DFN6(2x2)-B"]
end
C --> D
subgraph "Channel 1: MCU & Sensors"
D --> E["Channel 1 Output"]
E --> F["MCU Power Rail"]
E --> G["Sensor Array Power"]
F --> H["Ground"]
G --> H
end
subgraph "Channel 2: Communication & Display"
D --> I["Channel 2 Output"]
I --> J["BLE/Wi-Fi Module"]
I --> K["Display Backlight"]
I --> L["User Interface"]
J --> M["Ground"]
K --> M
L --> M
end
subgraph "Control Interface"
N["MCU GPIO 3.3V/5V"] --> O["Level Shifter Circuit"]
subgraph "Level Shifter Options"
P["NPN Transistor MMBT3904"]
Q["N-MOSFET Level Shifter"]
end
O --> R["Gate Control Signals"]
R --> D
end
subgraph "Protection Features"
S["Pull-Up Resistor Gate Discharge"] --> D
T["Decoupling Capacitor Load Side"] --> E
T --> I
U["Over-Current Detection"] --> V["Fault Indicator"]
end
subgraph "Thermal Management"
W["Copper Pour Area ≥50mm²"] --> D
X["Symmetrical Layout"] --> D
end
end
style D fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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