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MOSFET Selection Strategy and Device Adaptation Handbook for High-Performance Island Commuter eVTOLs with Extreme Reliability and Power Density Requirements
eVTOL MOSFET Selection Strategy System Topology Diagram

eVTOL Power System Overall Topology with MOSFET Selection Strategy

graph LR %% High-Voltage Energy Source & Distribution subgraph "High-Voltage Energy Storage & Primary Distribution" BAT_PACK["High-Voltage Battery Pack
400V-800V DC"] --> MAIN_CONTACTOR["Main Contactor"] MAIN_CONTACTOR --> HV_DC_BUS["HV DC Power Bus
400V-800V"] HV_DC_BUS --> SSPC_ARRAY["Solid-State Power Controller (SSPC) Array"] end %% Core Propulsion System subgraph "Main Propulsion Motor Inverters (Multi-Rotor)" HV_DC_BUS --> INV_LEG1["Inverter Phase Leg 1"] HV_DC_BUS --> INV_LEG2["Inverter Phase Leg 2"] HV_DC_BUS --> INV_LEG3["Inverter Phase Leg 3"] INV_LEG1 --> MOTOR1["Propulsion Motor 1
High Torque"] INV_LEG2 --> MOTOR2["Propulsion Motor 2
High Torque"] INV_LEG3 --> MOTOR3["Propulsion Motor 3
High Torque"] subgraph "MOSFET Array: VBP1606 (60V/150A)" Q_INV_H1["High-Side Switch"] Q_INV_L1["Low-Side Switch"] Q_INV_H2["High-Side Switch"] Q_INV_L2["Low-Side Switch"] end INV_LEG1 --> Q_INV_H1 INV_LEG1 --> Q_INV_L1 INV_LEG2 --> Q_INV_H2 INV_LEG2 --> Q_INV_L2 Q_INV_H1 --> MOTOR1 Q_INV_L1 --> MOTOR_GND["Motor Ground"] Q_INV_H2 --> MOTOR2 Q_INV_L2 --> MOTOR_GND end %% Power Distribution & Protection subgraph "High-Voltage Power Distribution & Protection (SSPC)" SSPC_ARRAY --> SSPC_CH1["SSPC Channel 1
Avionics"] SSPC_ARRAY --> SSPC_CH2["SSPC Channel 2
De-icing"] SSPC_ARRAY --> SSPC_CH3["SSPC Channel 3
Cabin HVAC"] SSPC_ARRAY --> SSPC_CH4["SSPC Channel 4
Auxiliary Systems"] subgraph "SSPC MOSFET: VBMB165R20SFD (650V/20A)" Q_SSPC1["Power Switch
Isolated Package"] Q_SSPC2["Power Switch
Isolated Package"] end SSPC_CH1 --> Q_SSPC1 SSPC_CH2 --> Q_SSPC2 Q_SSPC1 --> LOAD_AVIONICS["Avionics Load"] Q_SSPC2 --> LOAD_DEICE["De-icing Load"] end %% Auxiliary & Actuator Systems subgraph "Mission-Critical Auxiliary & Actuator Loads" AUX_DC_BUS["Auxiliary DC Bus
28V/48V"] --> ACTUATOR_CTRL["Actuator Controller"] AUX_DC_BUS --> PUMP_CTRL["Pump Motor Controller"] AUX_DC_BUS --> VALVE_CTRL["Valve Controller"] subgraph "Dual MOSFET: VBQF3101M (100V/12.1A per Ch)" Q_DUAL1["Channel 1
DFN8 Package"] Q_DUAL2["Channel 2
DFN8 Package"] end ACTUATOR_CTRL --> Q_DUAL1 ACTUATOR_CTRL --> Q_DUAL2 Q_DUAL1 --> SERVO_ACTUATOR["Servo Actuator
Flight Control"] Q_DUAL2 --> LANDING_GEAR["Landing Gear Motor"] end %% Control & Management subgraph "Flight Control & Power Management" FCU["Flight Control Unit
MCU"] --> GATE_DRIVER_INV["Motor Gate Driver"] FCU --> GATE_DRIVER_SSPC["SSPC Gate Driver"] FCU --> GATE_DRIVER_AUX["Auxiliary Load Driver"] FCU --> SENSING_NETWORK["Sensing Network"] SENSING_NETWORK --> CURRENT_SENSE["Current Sensors"] SENSING_NETWORK --> TEMP_SENSE["Temperature Sensors"] SENSING_NETWORK --> VOLTAGE_SENSE["Voltage Sensors"] end %% Thermal Management subgraph "Multi-Level Thermal Management" COOLING_SYS["Cooling System Controller"] --> LIQUID_COOLING["Liquid Cooling
Propulsion Inverters"] COOLING_SYS --> FORCED_AIR["Forced Air Cooling
SSPC & Distribution"] COOLING_SYS --> PCB_COOLING["PCB Thermal Design
Auxiliary MOSFETs"] LIQUID_COOLING --> Q_INV_H1 LIQUID_COOLING --> Q_INV_L1 FORCED_AIR --> Q_SSPC1 FORCED_AIR --> Q_SSPC2 PCB_COOLING --> Q_DUAL1 PCB_COOLING --> Q_DUAL2 end %% Protection & Safety subgraph "Protection & Safety Systems" PROTECTION_LOGIC["Protection Logic"] --> DESAT_DETECT["Desaturation Detection"] PROTECTION_LOGIC --> OC_PROTECT["Overcurrent Protection"] PROTECTION_LOGIC --> OV_UV_PROTECT["Over/Under Voltage"] PROTECTION_LOGIC --> OT_PROTECT["Overtemperature Protection"] DESAT_DETECT --> Q_INV_H1 OC_PROTECT --> Q_SSPC1 OV_UV_PROTECT --> HV_DC_BUS OT_PROTECT --> TEMP_SENSE end %% Communication Interfaces FCU --> CAN_AVIONICS["CAN Bus
Avionics Network"] FCU --> REDUNDANT_BUS["Redundant Communication Bus"] FCU --> DIAGNOSTICS["Diagnostics & Health Monitoring"] %% Style Definitions style Q_INV_H1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SSPC1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_DUAL1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style FCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the advancement of urban air mobility and the specific demand for efficient island connectivity, high-performance electric Vertical Take-Off and Landing (eVTOL) aircraft have emerged as a transformative solution. The propulsion, power distribution, and critical auxiliary systems, serving as the "heart, arteries, and nerves" of the vehicle, require ultra-efficient and robust power switching. The selection of power MOSFETs is pivotal in determining overall system efficiency, weight (power density), electromagnetic compatibility (EMC), and most critically, operational safety and reliability. Addressing the extreme requirements of eVTOLs for fault tolerance, specific power, thermal management, and harsh operating environments, this article develops a scenario-optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Multi-Dimensional Co-Design
MOSFET selection must be a co-design process across voltage, loss (efficiency), package (power density/weight), and ruggedness, ensuring perfect alignment with the stringent aviation operational profile.
Voltage Ruggedness with Margin: For high-voltage propulsion buses (e.g., 400V-800V DC), select devices with a voltage rating offering a minimum of 20-30% margin above the maximum bus voltage, including transients. For lower-voltage auxiliary buses (e.g., 28V, 48V), a ≥50% margin is recommended.
Ultra-Low Loss Priority: Minimizing conduction loss (Rds(on)) and switching loss (Qg, Coss) is non-negotiable for maximizing flight time (energy efficiency) and reducing thermal management weight. Superjunction (SJ) or advanced Trench technologies are essential for high-voltage links.
Package for Power Density & Cooling: Prioritize packages with excellent thermal impedance (RthJC) and power handling per gram. TO-247/TO-220 are workhorses for high-power stages where heatsinking is viable. Compact DFN packages are ideal for space/weight-critical distributed nodes.
Extreme Reliability & Ruggedness: Devices must operate flawlessly across wide temperature ranges (-55°C to 175°C), exhibit high avalanche energy rating, and possess robust gate oxide integrity. Qualification to automotive-grade or similar high-reliability standards is a baseline.
(B) Scenario Adaptation Logic: Categorization by Critical Function
Divide applications into three core domains: First, the Main Propulsion Motor Drive, requiring the highest efficiency, current capability, and fault tolerance. Second, the High-Voltage DC Power Distribution & Protection, requiring high-voltage blocking, moderate current, and compact solutions. Third, Mission-Critical Auxiliary & Actuator Loads, requiring high reliability, fast switching, and space-saving integration for distributed control.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: Main Propulsion Motor Inverter (High-Power Phase Leg) – The Power Core
Multi-rotor propulsion motors demand extremely high continuous and peak currents (hundreds of Amps) with high switching frequencies for precise control, making efficiency and thermal performance paramount.
Recommended Model: VBP1606 (Single-N, 60V, 150A, TO247)
Parameter Advantages: An exceptionally low Rds(on) of 7mΩ (typ @10V) minimizes conduction loss in each switch. A massive continuous current rating of 150A meets the demands of high-thrust motors. The TO247 package offers superior thermal dissipation capability when mounted on a cooled heatsink.
Adaptation Value: Enables inverter efficiency >98.5%, directly extending range. The low loss reduces heatsink size and weight. Its high current rating provides headroom for peak torque demands and enhances system ruggedness.
Selection Notes: Requires a high-performance gate driver with >2A drive capability. Parallel devices may be needed for higher power motors. Careful attention to power loop layout inductance is critical. Must be used with comprehensive overcurrent and overtemperature protection circuits.
(B) Scenario 2: High-Voltage Bus Distribution & Protection (Solid-State Power Controller - SSPC) – The Power Router
This scenario involves switching and protecting 400V-800V DC power to various subsystems (avionics, de-icing, cabin HVAC). Key needs are high voltage blocking, fast fault isolation, and moderate current in a potentially compact form.
Recommended Model: VBMB165R20SFD (Single-N, 650V, 20A, TO220F)
Parameter Advantages: The 650V rating is ideal for 400V bus applications with ample margin. Advanced SJ_Multi-EPI technology achieves a competitive Rds(on) of 175mΩ for its voltage class. The 20A current is suitable for many subsystem branches. The TO220F (fully isolated) package simplifies insulation and mounting.
Adaptation Value: Enables the implementation of lightweight, intelligent SSPCs replacing mechanical breakers. Facilitates rapid (<100µs) fault isolation and remote power management. The isolated package enhances safety and simplifies thermal interface design.
Selection Notes: Ensure gate drive is referenced to the correct floating source. Implement active clamping or use devices with high UIS rating for inductive load disconnection. Pair with current sensing for precise trip characteristics.
(C) Scenario 3: Mission-Critical Auxiliary Loads & Actuators (Flight Control, Landing Gear) – The Reliability Node
These are numerous, distributed loads (e.g., servo actuators, pump motors, valve controllers) often on a 28V or 48V bus. Requirements include high reliability, space/weight savings, and often dual-channel control for redundancy or H-bridge configurations.
Recommended Model: VBQF3101M (Dual-N+N, 100V, 12.1A per channel, DFN8(3x3)-B)
Parameter Advantages: The dual N-channel integration in a tiny DFN8 package saves over 60% PCB area compared to two discrete devices, crucial for distributed controllers. A 100V rating provides robust margin on 48V systems. Low Vth of 1.8V allows for efficient drive by modern 3.3V/5V flight controllers.
Adaptation Value: Perfect for building compact, redundant half-bridge drivers for actuators or intelligent high-side/low-side switches. The minimal package parasitics support clean, high-frequency switching, improving actuator response.
Selection Notes: Pay meticulous attention to PCB thermal design for the shared die. Independent gate resistors are recommended for each channel to prevent cross-talk. Ideal for use in modular, line-replaceable unit (LRU) designs.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matched to Device Dynamics
VBP1606: Requires a dedicated, powerful gate driver IC (e.g., isolated gate driver) with low-impedance paths. Use Kelvin source connection if available. Implement active miller clamping to prevent shoot-through.
VBMB165R20SFD: Use galvanically isolated gate drivers for high-side switches. Include sufficient gate pull-down resistance for robust off-state in noisy environments.
VBQF3101M: Can be driven directly from microcontroller PWM outputs via a buffer stage. Include series gate resistors (e.g., 2.2Ω - 10Ω) close to the package to damp ringing.
(B) Thermal Management Design: Mission-Critical Cooling
VBP1606: Mount on a liquid-cooled or forced-air-cooled heatsink. Use high-performance thermal interface materials (TIM). Monitor junction temperature via thermal sensor or model-based estimator.
VBMB165R20SFD: Mount on a chassis or dedicated heatsink. The isolated package eliminates need for insulation pads, improving thermal transfer.
VBQF3101M: Provide a generous, symmetric copper pad on the PCB (≥30mm² per channel) with multiple thermal vias to inner ground planes for heat spreading. Board layout is the primary heatsink.
(C) EMC & Reliability Assurance for Airworthiness
EMC Suppression: Employ tight DC-link busing with low-ESR/ESL ceramic capacitors. Use RC snubbers across switches for high-frequency ringing control. Implement proper shielding and filtering for all gate drive signals. Zone the PCB into noisy (power) and quiet (control) areas.
Reliability Protection:
Derating: Apply stringent derating rules (e.g., voltage ≤80%, current ≤60-70% at max junction temperature).
Fault Protection: Design for short-circuit withstand time. Use desaturation detection for VBP1606. Implement redundant current sensing paths.
Environmental Hardening: Conformal coating may be required. All selections must be validated for operation under vibration, humidity, and altitude pressure changes.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Powertrain Efficiency & Range: Ultra-low loss devices directly contribute to industry-leading specific power and extended mission duration.
Enhanced Safety through Intelligent Power Distribution: Enables fault-tolerant, software-defined electrical systems, moving beyond traditional fused wiring.
Optimized System Weight & Volume: Strategic use of compact, high-performance packages (DFN, TO220F) reduces the weight and size of power electronics, a critical metric for eVTOLs.
Foundation for High-Reliability Design: The selected devices form a robust basis for building systems capable of meeting stringent aviation reliability targets (e.g., DO-254/DO-160).
(B) Optimization Suggestions
Higher Power / Voltage: For 800V+ bus systems or larger motors, consider devices like VBM16R08SE (600V) in parallel or modules.
Higher Integration: For auxiliary loads, explore intelligent power switches (IPS) with integrated protection and diagnostics.
Technology Evolution: Monitor the maturation of Silicon Carbide (SiC) MOSFETs for the highest voltage and frequency stages in future generation designs.
Specialized Functions: For battery disconnect units, consider using the VBMB165R20SFD in conjunction with pre-charge circuitry.
Conclusion
The meticulous selection and application of power MOSFETs is foundational to achieving the trifecta of performance, safety, and reliability in eVTOL electrical systems. This scenario-based strategy, leveraging devices optimized for propulsion, distribution, and critical loads, provides a clear roadmap for engineers developing next-generation urban air mobility platforms. Continued focus on advancing device technology and system integration will be key to unlocking the full potential of sustainable island and urban commuter aviation.

Detailed Application Topology Diagrams

Main Propulsion Motor Inverter Topology Detail

graph LR subgraph "Three-Phase Inverter Bridge" HV_BUS["HV DC Bus 400V-800V"] --> PHASE_LEG_U["Phase Leg U"] HV_BUS --> PHASE_LEG_V["Phase Leg V"] HV_BUS --> PHASE_LEG_W["Phase Leg W"] subgraph "Phase Leg U - VBP1606 (60V/150A)" Q_UH["High-Side VBP1606
Rds(on)=7mΩ"] Q_UL["Low-Side VBP1606
Rds(on)=7mΩ"] end subgraph "Phase Leg V - VBP1606 (60V/150A)" Q_VH["High-Side VBP1606"] Q_VL["Low-Side VBP1606"] end subgraph "Phase Leg W - VBP1606 (60V/150A)" Q_WH["High-Side VBP1606"] Q_WL["Low-Side VBP1606"] end PHASE_LEG_U --> Q_UH PHASE_LEG_U --> Q_UL PHASE_LEG_V --> Q_VH PHASE_LEG_V --> Q_VL PHASE_LEG_W --> Q_WH PHASE_LEG_W --> Q_WL Q_UH --> MOTOR_U["Motor Phase U"] Q_UL --> INV_GND["Inverter Ground"] Q_VH --> MOTOR_V["Motor Phase V"] Q_VL --> INV_GND Q_WH --> MOTOR_W["Motor Phase W"] Q_WL --> INV_GND end subgraph "Gate Drive & Control" GATE_DRIVER["High-Current Gate Driver
Isolated"] --> Q_UH GATE_DRIVER --> Q_UL CONTROLLER["Motor Controller
DSP/FPGA"] --> GATE_DRIVER CURRENT_FEEDBACK["Phase Current Sensing"] --> CONTROLLER DESAT_CIRCUIT["Desaturation Detection"] --> PROTECTION["Protection Logic"] PROTECTION --> SHUTDOWN["Shutdown Signal"] SHUTDOWN --> GATE_DRIVER end subgraph "Thermal Management" LIQUID_PLATE["Liquid Cold Plate"] --> Q_UH LIQUID_PLATE --> Q_UL TEMP_SENSOR["Temperature Sensor"] --> CONTROLLER CONTROLLER --> COOLING_CTRL["Cooling Control"] end style Q_UH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_UL fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

High-Voltage Distribution & SSPC Topology Detail

graph LR subgraph "Solid-State Power Controller (SSPC) Channel" HV_IN["HV Bus Input"] --> FUSE["Protective Fuse"] FUSE --> CURRENT_SENSE["Current Sense Resistor"] CURRENT_SENSE --> Q_SSPC["VBMB165R20SFD
650V/20A
TO220F Isolated"] Q_SSPC --> LOAD_OUTPUT["Load Output"] LOAD_OUTPUT --> LOAD["Subsystem Load
(Avionics/De-ice/HVAC)"] end subgraph "Control & Protection Circuitry" CONTROL_MCU["SSPC Controller"] --> ISOLATED_DRIVER["Isolated Gate Driver"] ISOLATED_DRIVER --> Q_SSPC CURRENT_SENSE --> AMP["Current Sense Amplifier"] AMP --> COMPARATOR["Comparator"] COMPARATOR --> TRIP_LOGIC["Trip Logic"] TRIP_LOGIC --> CONTROL_MCU CONTROL_MCU --> STATUS_LED["Status Indicator"] end subgraph "Fault Protection Features" subgraph "Active Clamping" CLAMP_DIODE["Clamping Diode"] CLAMP_CAP["Clamping Capacitor"] end CLAMP_DIODE --> Q_SSPC CLAMP_CAP --> Q_SSPC UIS_PROTECT["UIS Protection"] --> Q_SSPC OVERVOLTAGE_TVS["TVS Overvoltage Protection"] --> LOAD_OUTPUT end subgraph "Thermal Management" HEATSINK["Aluminum Heatsink"] --> Q_SSPC THERMAL_PAD["Thermal Interface Material"] --> Q_SSPC TEMP_MONITOR["Temperature Monitor"] --> CONTROL_MCU CONTROL_MCU --> DERATING["Power Derating Logic"] end style Q_SSPC fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Auxiliary & Actuator Load Management Topology Detail

graph LR subgraph "Dual-Channel Load Switch Configuration" AUX_POWER["28V/48V Aux Bus"] --> CH1_IN["Channel 1 Input"] AUX_POWER --> CH2_IN["Channel 2 Input"] subgraph "VBQF3101M Dual N-MOSFET" Q_CH1["Channel 1
100V/12.1A"] Q_CH2["Channel 2
100V/12.1A"] end CH1_IN --> Q_CH1 CH2_IN --> Q_CH2 Q_CH1 --> CH1_OUT["Channel 1 Output"] Q_CH2 --> CH2_OUT["Channel 2 Output"] CH1_OUT --> LOAD1["Critical Load 1
Servo Actuator"] CH2_OUT --> LOAD2["Critical Load 2
Landing Gear"] LOAD1 --> GND_AUX["Auxiliary Ground"] LOAD2 --> GND_AUX end subgraph "Compact Gate Drive Solution" MCU_GPIO["MCU GPIO 3.3V/5V"] --> BUFFER["Buffer Stage"] BUFFER --> GATE_RES1["2.2Ω Gate Resistor"] BUFFER --> GATE_RES2["2.2Ω Gate Resistor"] GATE_RES1 --> Q_CH1 GATE_RES2 --> Q_CH2 PULLDOWN_RES["10kΩ Pull-down"] --> Q_CH1 PULLDOWN_RES --> Q_CH2 end subgraph "PCB Thermal Design & Layout" THERMAL_PAD_DFN["Thermal Pad (DFN8 3x3)"] --> Q_CH1 THERMAL_PAD_DFN --> Q_CH2 COPPER_POUR["PCB Copper Pour"] --> THERMAL_PAD_DFN THERMAL_VIAS["Thermal Vias Array"] --> COPPER_POUR GROUND_PLANE["Inner Ground Plane"] --> THERMAL_VIAS end subgraph "Redundant Control Interface" REDUNDANT_MCU["Redundant MCU"] --> OR_GATE["OR Logic Gate"] MCU_GPIO --> OR_GATE OR_GATE --> BUFFER DIAGNOSTICS_OUT["Diagnostics Output"] --> HEALTH_MONITOR["Health Monitor"] end style Q_CH1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_CH2 fill:#fff3e0,stroke:#ff9800,stroke-width:2px

System Protection & EMC Topology Detail

graph LR subgraph "EMC Suppression & Filtering" subgraph "DC-Link Bus Filtering" DC_LINK_CAP["Low-ESR/ESL Ceramic Capacitors"] BULK_CAP["Bulk Electrolytic Capacitors"] SNUBBER_RC["RC Snubber Network"] end HV_BUS_IN["HV Bus"] --> DC_LINK_CAP HV_BUS_IN --> BULK_CAP DC_LINK_CAP --> SNUBBER_RC SNUBBER_RC --> POWER_SWITCH["Power MOSFETs"] end subgraph "Gate Drive Protection" GATE_DRIVE["Gate Driver Output"] --> TVS_GATE["TVS Protection"] TVS_GATE --> GATE_RES["Series Gate Resistor"] GATE_RES --> MOSFET_GATE["MOSFET Gate"] PULLDOWN["Strong Pull-down"] --> MOSFET_GATE MILLER_CLAMP["Active Miller Clamp"] --> MOSFET_GATE end subgraph "System-Level Fault Protection" subgraph "Current Protection" DESAT_DETECT["Desaturation Detection"] SHUNT_SENSE["Shunt Current Sensing"] HALL_SENSE["Hall Effect Sensor"] end subgraph "Voltage Protection" OVERVOLTAGE["Overvoltage Clamp"] UNDERVOLTAGE["Undervoltage Lockout"] TVS_MAIN["Main TVS Array"] end subgraph "Thermal Protection" NTC_SENSORS["NTC Temperature Sensors"] THERMAL_MODEL["Model-Based Estimator"] SHUTDOWN_THERMAL["Thermal Shutdown"] end DESAT_DETECT --> FAULT_LOGIC["Fault Logic Controller"] SHUNT_SENSE --> FAULT_LOGIC OVERVOLTAGE --> FAULT_LOGIC NTC_SENSORS --> FAULT_LOGIC FAULT_LOGIC --> SAFE_SHUTDOWN["Safe Shutdown Sequence"] end subgraph "Environmental Hardening" CONFORMAL_COAT["Conformal Coating"] --> ALL_COMPONENTS["All PCB Components"] VIBRATION_MOUNT["Vibration-Resistant Mounting"] --> POWER_COMPONENTS["Power Components"] PRESSURIZATION["Pressurization/Sealing"] --> ENCLOSURE["System Enclosure"] end subgraph "Redundancy Architecture" PRIMARY_PATH["Primary Power Path"] --> VOTING_LOGIC["Voting Logic"] REDUNDANT_PATH["Redundant Power Path"] --> VOTING_LOGIC BACKUP_PATH["Backup Power Path"] --> VOTING_LOGIC VOTING_LOGIC --> LOAD_OUT["Protected Load Output"] end style POWER_SWITCH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style MOSFET_GATE fill:#e3f2fd,stroke:#2196f3,stroke-width:2px
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