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MOSFET Selection Strategy and Device Adaptation Handbook for High-End eVTOL Personnel Training Platforms with Demanding Power Density and Reliability Requirements
eVTOL Training Platform MOSFET Topology Diagrams

eVTOL Training Platform Overall Power Architecture

graph LR %% Main Power Distribution subgraph "High-Voltage DC Power Distribution" HV_BUS["48V/High-Voltage DC Bus"] --> PWR_DIST["Power Distribution Unit"] end %% Scenario 1: Main Propulsion Motor Drive subgraph "Scenario 1: Main Propulsion Motor Drive (Multi-kW)" INV_BRIDGE["Three-Phase Inverter Bridge"] subgraph "Motor Drive MOSFET Array" M1["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] M2["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] M3["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] M4["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] M5["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] M6["VBGQF1606
60V/50A
Rds(on)=6.5mΩ"] end INV_BRIDGE --> M1 INV_BRIDGE --> M2 INV_BRIDGE --> M3 INV_BRIDGE --> M4 INV_BRIDGE --> M5 INV_BRIDGE --> M6 M1 --> MOTOR_PHASE_A["Motor Phase A"] M2 --> MOTOR_PHASE_A M3 --> MOTOR_PHASE_B["Motor Phase B"] M4 --> MOTOR_PHASE_B M5 --> MOTOR_PHASE_C["Motor Phase C"] M6 --> MOTOR_PHASE_C MOTOR_PHASE_A --> LIFT_MOTOR["Lift/Cruise Motor
(5kW+)"] MOTOR_PHASE_B --> LIFT_MOTOR MOTOR_PHASE_C --> LIFT_MOTOR end %% Scenario 2: Flight Control Actuator subgraph "Scenario 2: Flight Control Actuator & Servo (100W-1kW)" SERVO_DRV["Servo Driver Controller"] subgraph "Actuator MOSFET Array" A1["VBBC1309
30V/13A
Rds(on)=8mΩ"] A2["VBBC1309
30V/13A
Rds(on)=8mΩ"] A3["VBBC1309
30V/13A
Rds(on)=8mΩ"] A4["VBBC1309
30V/13A
Rds(on)=8mΩ"] end SERVO_DRV --> A1 SERVO_DRV --> A2 SERVO_DRV --> A3 SERVO_DRV --> A4 A1 --> SERVO_MOTOR["Flight Control Servo
EMA/Actuator"] A2 --> SERVO_MOTOR A3 --> SERVO_MOTOR A4 --> SERVO_MOTOR end %% Scenario 3: Avionics Power Management subgraph "Scenario 3: Critical Avionics & Redundant Power" PDU["Power Distribution Unit"] subgraph "Redundant Power Switching" R1["VBBD5222
Dual N+P MOS
±20V/5.9A"] R2["VBBD5222
Dual N+P MOS
±20V/5.9A"] R3["VBBD5222
Dual N+P MOS
±20V/5.9A"] end PDU --> R1 PDU --> R2 PDU --> R3 R1 --> AVIONICS_1["Primary Avionics Bus"] R2 --> AVIONICS_2["Redundant Avionics Bus"] R3 --> SIM_SUBSYS["Simulation Subsystems"] subgraph "Ideal Diode OR-ing" OR1["VBBD5222
OR-ing Controller"] OR2["VBBD5222
OR-ing Controller"] end POWER_SOURCE_1["Primary Power Source"] --> OR1 POWER_SOURCE_2["Backup Power Source"] --> OR2 OR1 --> CRITICAL_LOAD["Critical Loads"] OR2 --> CRITICAL_LOAD end %% Control & Monitoring subgraph "System Control & Health Monitoring" MCU["Main Control MCU/FPGA"] subgraph "Gate Drivers" DRV_HV["High-Current Gate Driver
(>2A)"] DRV_MED["Medium-Power Driver"] DRV_LOGIC["Logic-Level Driver"] end MCU --> DRV_HV MCU --> DRV_MED MCU --> DRV_LOGIC DRV_HV --> M1 DRV_HV --> M2 DRV_MED --> A1 DRV_LOGIC --> R1 subgraph "Protection & Sensing" CURRENT_SENSE["Current Sensing
(Shunt+Comparator)"] TEMP_SENSE["Temperature Sensors"] TVS_ARRAY["TVS Protection
(15V Bidirectional)"] end CURRENT_SENSE --> MCU TEMP_SENSE --> MCU TVS_ARRAY --> DRV_HV TVS_ARRAY --> DRV_MED end %% Thermal Management subgraph "Three-Level Thermal Management" COOLING_L1["Level 1: Liquid Cold Plate"] --> M1 COOLING_L1 --> M2 COOLING_L2["Level 2: Forced Air Cooling"] --> A1 COOLING_L2 --> A2 COOLING_L3["Level 3: PCB Thermal Design"] --> R1 COOLING_L3 --> R2 TEMP_SENSE --> COOLING_CTRL["Cooling Controller"] COOLING_CTRL --> COOLING_L1 COOLING_CTRL --> COOLING_L2 end %% Power Flow Connections PWR_DIST --> INV_BRIDGE PWR_DIST --> SERVO_DRV PWR_DIST --> PDU %% Style Definitions style M1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style A1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style R1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the rapid advancement of urban air mobility (UAM) and the growing need for certified pilot training, electric Vertical Take-Off and Landing (eVTOL) simulators and training platforms have become critical for developing essential flight skills. The powertrain and actuator control systems, serving as the "propulsion and nervous system" of these platforms, require precise and robust power switching for key loads such as lift/cruise motor drives, servo actuators for flight controls, and critical avionics power management. The selection of power MOSFETs directly determines system efficiency, power density, thermal performance, and mission-critical reliability. Addressing the stringent requirements of eVTOL training platforms for safety, high dynamic response, extreme reliability, and compactness, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Optimization for Aviation
MOSFET selection requires coordinated optimization across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with the rigorous operating conditions of aviation training environments:
High Voltage Margin & Ruggedness: For typical 48V or higher HV DC buses in eVTOL architectures, reserve a rated voltage margin ≥100% to handle severe voltage transients, regenerative braking spikes, and ensure operational safety. Prioritize devices with high VDS ratings and robust VGS limits.
Ultra-Low Loss for High Power Density: Prioritize devices with extremely low Rds(on) (minimizing conduction loss in high-current paths) and optimized gate charge Qg (enabling fast switching for high-frequency motor drives), crucial for maximizing efficiency and minimizing thermal load in confined spaces.
Package for Thermal & Weight Constraints: Choose advanced packages like DFN with excellent thermal impedance (RthJA) and low parasitic inductance for high-power motor drives. Select ultra-compact packages like SC70 or DFN for low-power, weight-sensitive control circuits, balancing thermal performance, power density, and PCB real estate.
Mission-Critical Reliability & Wide Temperature Range: Exceed standard industrial requirements. Focus on exceptional thermal stability, high ESD robustness, and an extended junction temperature range (e.g., -55°C to 175°C) to adapt to harsh environmental conditions and ensure fail-safe operation during intensive training scenarios.
(B) Scenario Adaptation Logic: Categorization by Flight-Critical Function
Divide loads into three core operational scenarios: First, Main Propulsion Motor Drive (High-Power Core), requiring very high current, ultra-efficient, and high-frequency switching. Second, Flight Control Actuator & Servo Drive (High-Dynamics Control), requiring medium power with excellent transient response and reliability. Third, Critical Avionics & Redundant Power Distribution (Safety-Critical Management), requiring compact, low-loss switching for power sequencing, load shedding, and redundant bus control.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: Main Propulsion Motor Drive (Multi-kW Range) – High-Power Core Device
eVTOL lift and cruise motors demand handling of very high continuous and peak surge currents (during take-off/landing simulations), necessitating ultra-low loss, high-frequency capable devices.
Recommended Model: VBGQF1606 (Single N-MOS, 60V, 50A, DFN8(3x3))
Parameter Advantages: Advanced SGT (Shielded Gate Trench) technology achieves an ultra-low Rds(on) of 6.5mΩ at 10V. A high continuous current of 50A (with high peak capability) is suitable for 48V+ bus architectures. The DFN8(3x3) package offers superior thermal performance (low RthJA) and minimal parasitic inductance, essential for high-efficiency, high-switching-frequency (>100 kHz) motor controller designs.
Adaptation Value: Dramatically reduces conduction and switching losses in multi-phase inverter bridges. For a 48V/5kW motor phase, conduction losses are minimized, enabling inverter efficiency >98%. Supports high-frequency PWM, reducing motor acoustic noise and allowing for smaller, lighter filter components, directly contributing to higher system power density.
Selection Notes: Verify motor peak phase current and DC bus voltage derating. Implement substantial PCB copper pours (≥300mm² per device) with thermal vias for heat sinking. Must be paired with high-performance gate drivers (≥2A source/sink) and controllers with comprehensive fault protection (OCP, OTP, DESAT).
(B) Scenario 2: Flight Control Actuator & Servo Drive (100W-1kW) – High-Dynamics Device
Electromechanical actuators (EMAs) or servo motors for flight control surfaces require precise, rapid current control, medium power handling, and high reliability.
Recommended Model: VBBC1309 (Single N-MOS, 30V, 13A, DFN8(3x3))
Parameter Advantages: Balanced performance with 30V VDS, suitable for 24V or lower actuator buses. Low Rds(on) of 8mΩ at 10V ensures low loss. DFN8 package provides a good thermal path for dissipating heat in potentially enclosed actuator housings. A standard Vth of 1.7V ensures compatibility with 3.3V/5V logic from control MCUs or FPGAs.
Adaptation Value: Enables high-bandwidth, high-fidelity current control loops essential for realistic control loading and force feedback in training platforms. Its compact size and efficiency support the integration of multiple redundant actuator channels within tight spaces.
Selection Notes: Ensure actuator stall current is within safe operating area (SOA) with margin. Pair with dedicated servo driver ICs or protected half-bridge drivers. Implement localized heatsinking (≥100mm² copper).
(C) Scenario 3: Critical Avionics & Redundant Power Distribution – Safety-Critical Device
Power distribution units (PDUs), redundant bus switches, and avionics rail controls require compact, efficient switching with the ability to implement OR-ing, load switching, and fault isolation.
Recommended Model: VBBD5222 (Dual N+P MOSFET, ±20V, 5.9A/-4.1A, DFN8(3x2)-B)
Parameter Advantages: Unique integrated complementary pair (N+P) in a single compact DFN package saves over 60% board space compared to discrete solutions. ±20V rating is ideal for 12V/28V avionic bus control. Symmetrical low Vth (±0.8V) allows for efficient low-voltage drive.
Adaptation Value: Perfect for building compact, efficient redundant power path controllers (ideal diode OR-ing circuits), hot-swap controllers, or intelligent high-side/low-side load switches. Enables sophisticated power sequencing and fault isolation for critical navigation, communication, and simulation sub-systems, enhancing overall platform safety and availability.
Selection Notes: Carefully manage power dissipation in the P-channel due to its higher Rds(on). Implement appropriate gate drive logic (often using the N-channel to drive the P-channel gate). Add current sensing and protection circuits for each switched path.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matched to Aviation Demands
VBGQF1606: Requires high-current, low-inductance gate drive circuits. Use dedicated aviation-grade gate driver ICs with high noise immunity. Minimize power loop inductance with an ultra-tight PCB layout. Consider active Miller clamp circuits.
VBBC1309: Can be driven directly from motor driver IC outputs. Include series gate resistors (2.2Ω-22Ω) to control slew rate and prevent ringing. Ensure driver has sufficient current capability for the required switching speed.
VBBD5222: Design gate control circuits to ensure clean, fast turn-on/off for both transistors, preventing cross-conduction in OR-ing applications. Use level shifters if control logic is referenced to a different ground.
(B) Thermal Management Design: Aggressive for Confined Spaces
VBGQF1606: Primary thermal focus. Use maximum possible copper area, multi-oz inner layers, and arrays of thermal vias to internal ground planes or dedicated thermal layers. Consider direct attachment to a cold plate or chassis in high-power density designs. Enforce strict current derating (e.g., ≤50% of Id at max Tj).
VBBC1309: Implement dedicated copper pours (≥150mm²) with thermal vias. In actuator housings, ensure thermal coupling to the housing structure if applicable.
VBBD5222: Provide symmetrical copper relief under the package. Thermal vias are critical due to the small package size and potential for concentrated heat from the P-channel.
System-Level: Integrate MOSFET thermal pads into the overall platform cooling strategy (liquid cooling, forced air). Place temperature sensors near high-stress devices.
(C) EMC and Reliability Assurance for Airworthiness
EMC Suppression:
VBGQF1606: Use low-ESR/ESL ceramic capacitors very close to drain-source terminals. Implement full three-phase LC filtering at motor outputs. Shield motor cables.
All Devices: Implement rigorous PCB zoning: separate high-power, high-speed, and sensitive analog/digital areas. Use ferrite beads on gate drives and local supplies. Employ full EMI filtering at all power inputs/outputs.
Reliability Protection:
Derating to Aviation Standards: Apply stringent derating rules (e.g., voltage ≤50%, current ≤60% at max operating temperature).
Comprehensive Fault Monitoring: Implement hardware-based overcurrent (shunt + comparator), overtemperature (sensor on PCB/package), and undervoltage lockout (UVLO) on all critical power stages.
Enhanced Ruggedness: Use TVS diodes on all gate drives (e.g., 15V bidirectional). Place robust TVS or varistors at power inputs and on outputs driving inductive loads (actuators). Design for high ESD immunity (HBM ≥ 2kV).
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximum Power Density & Efficiency: Enables compact, lightweight power and drive electronics essential for realistic, portable, or simulator-mounted eVTOL training systems. High efficiency reduces cooling burden and energy consumption.
Aviation-Grade Reliability: The selected devices and design approach prioritize fail-operational or fail-safe characteristics, directly supporting the development of training platforms that mimic the safety-critical nature of actual eVTOL operations.
System Integration & Scalability: The mix of high-power SGT MOSFETs, medium-power control MOSFETs, and integrated complementary pairs allows for scalable, modular designs adaptable to different training platform configurations and power levels.
(B) Optimization Suggestions
Higher Power Adaptation: For next-generation training platforms simulating larger eVTOLs (>20kW per motor), consider parallel operation of VBGQF1606 or evaluate upcoming 100V/80A+ SGT devices.
Increased Integration: For flight control actuator clusters, explore multi-channel half-bridge driver ICs pre-coupled with MOSFETs in a single package (IPM-like modules).
Extreme Environment Operation: For outdoor-capable training rigs, specify the extended temperature grade versions of all selected components (Tj,max = 175°C).
Redundancy Specialization: Use multiple VBBD5222 devices to design N-version redundant, independently switched power channels for the most critical avionics and control systems.
Conclusion
Power MOSFET selection is pivotal to achieving the high power density, dynamic performance, and uncompromising reliability required in eVTOL personnel training platforms. This scenario-based selection scheme, centered on the high-power VBGQF1606, the dynamic VBBC1309, and the integrative VBBD5222, provides a foundational technical roadmap. Future development should focus on integrating Wide Bandgap (SiC/GaN) devices for the highest efficiency segments and adopting smart power modules with embedded health monitoring, further advancing the fidelity and safety of next-generation eVTOL training solutions.

Detailed Topology Diagrams

Scenario 1: Main Propulsion Motor Drive Topology

graph LR subgraph "Three-Phase Inverter Bridge with VBGQF1606" DC_IN["48V DC Bus"] --> PHASE_A["Phase A Leg"] DC_IN --> PHASE_B["Phase B Leg"] DC_IN --> PHASE_C["Phase C Leg"] subgraph "Phase A" Q_AH["VBGQF1606
High-Side"] Q_AL["VBGQF1606
Low-Side"] end subgraph "Phase B" Q_BH["VBGQF1606
High-Side"] Q_BL["VBGQF1606
Low-Side"] end subgraph "Phase C" Q_CH["VBGQF1606
High-Side"] Q_CL["VBGQF1606
Low-Side"] end PHASE_A --> Q_AH PHASE_A --> Q_AL PHASE_B --> Q_BH PHASE_B --> Q_BL PHASE_C --> Q_CH PHASE_C --> Q_CL Q_AH --> MOTOR_A["Motor Phase A"] Q_AL --> MOTOR_A Q_BH --> MOTOR_B["Motor Phase B"] Q_BL --> MOTOR_B Q_CH --> MOTOR_C["Motor Phase C"] Q_CL --> MOTOR_C end subgraph "Gate Drive & Protection" DRIVER["High-Current Gate Driver
≥2A Source/Sink"] subgraph "Protection Circuits" DESAT["DESAT Detection"] MILLER_CLAMP["Active Miller Clamp"] TVS_GATE["TVS on Gate
(15V Bidirectional)"] end DRIVER --> Q_AH DRIVER --> Q_AL DRIVER --> Q_BH DRIVER --> Q_BL DRIVER --> Q_CH DRIVER --> Q_CL DESAT --> FAULT["Fault Signal"] MILLER_CLAMP --> DRIVER TVS_GATE --> DRIVER end subgraph "Thermal Management" COPPER["PCB Copper Pour
≥300mm² per device"] THERMAL_VIAS["Thermal Via Array"] COLD_PLATE["Liquid Cold Plate"] COPPER --> THERMAL_VIAS THERMAL_VIAS --> COLD_PLATE COLD_PLATE --> Q_AH COLD_PLATE --> Q_AL end subgraph "EMC Filtering" INPUT_CAP["Low-ESR/ESL Ceramic Caps
Close to Drain-Source"] MOTOR_FILTER["Three-Phase LC Filter"] SHIELDING["Shielded Motor Cables"] INPUT_CAP --> DC_IN MOTOR_FILTER --> MOTOR_A MOTOR_FILTER --> MOTOR_B MOTOR_FILTER --> MOTOR_C end style Q_AH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style DRIVER fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Scenario 2: Flight Control Actuator Topology

graph LR subgraph "Servo Motor Drive with VBBC1309" ACT_BUS["24V Actuator Bus"] --> HALF_BRIDGE["Half-Bridge Power Stage"] subgraph "H-Bridge Configuration" Q_H1["VBBC1309
High-Side 1"] Q_L1["VBBC1309
Low-Side 1"] Q_H2["VBBC1309
High-Side 2"] Q_L2["VBBC1309
Low-Side 2"] end HALF_BRIDGE --> Q_H1 HALF_BRIDGE --> Q_L1 HALF_BRIDGE --> Q_H2 HALF_BRIDGE --> Q_L2 Q_H1 --> SERVO_OUT1["Servo Output A"] Q_L1 --> SERVO_OUT1 Q_H2 --> SERVO_OUT2["Servo Output B"] Q_L2 --> SERVO_OUT2 SERVO_OUT1 --> SERVO_MTR["Flight Control Servo Motor"] SERVO_OUT2 --> SERVO_MTR end subgraph "Control & Drive Circuit" SERVO_CTRL["Servo Controller IC/FPGA"] subgraph "Gate Drive Network" GATE_RES["Series Gate Resistor
2.2Ω-22Ω"] BOOTSTRAP["Bootstrap Circuit"] LEVEL_SHIFT["Level Shifter if needed"] end SERVO_CTRL --> GATE_RES GATE_RES --> Q_H1 GATE_RES --> Q_L1 GATE_RES --> Q_H2 GATE_RES --> Q_L2 BOOTSTRAP --> Q_H1 BOOTSTRAP --> Q_H2 end subgraph "Current Control & Protection" CURRENT_LOOP["High-Bandwidth Current Loop"] subgraph "Protection" STALL_DET["Stall Current Detection"] SOA_MON["Safe Operating Area Monitor"] TEMP_MON["Local Temperature Monitoring"] end CURRENT_LOOP --> SERVO_CTRL STALL_DET --> SERVO_CTRL SOA_MON --> SERVO_CTRL TEMP_MON --> SERVO_CTRL end subgraph "Thermal Management" ACT_COPPER["Dedicated Copper Pour
≥150mm²"] ACT_VIAS["Thermal Vias"] HOUSING["Actuator Housing Thermal Coupling"] ACT_COPPER --> ACT_VIAS ACT_VIAS --> HOUSING HOUSING --> Q_H1 HOUSING --> Q_L1 end subgraph "EMC & Reliability" LOCAL_CAPS["Local Decoupling Capacitors"] FERRITE["Ferrite Beads on Gate Drives"] ZONING["PCB Zoning: Separate Power/Control"] LOCAL_CAPS --> ACT_BUS FERRITE --> GATE_RES end style Q_H1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SERVO_CTRL fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Scenario 3: Avionics & Redundant Power Topology

graph LR subgraph "Redundant Power Path Control with VBBD5222" PWR_SRC1["Primary Power Source
12V/28V"] --> ORING1["Ideal Diode OR-ing Circuit"] PWR_SRC2["Backup Power Source
12V/28V"] --> ORING2["Ideal Diode OR-ing Circuit"] subgraph "OR-ing Circuit Detail" Q_OR_N["VBBD5222 N-Channel
Controller Switch"] Q_OR_P["VBBD5222 P-Channel
Ideal Diode"] OR_CONTROL["OR-ing Control Logic"] end ORING1 --> Q_OR_N ORING1 --> Q_OR_P ORING2 --> Q_OR_N ORING2 --> Q_OR_P OR_CONTROL --> Q_OR_N OR_CONTROL --> Q_OR_P Q_OR_P --> REDUNDANT_BUS["Redundant Power Bus"] end subgraph "Load Switching & Distribution" REDUNDANT_BUS --> SWITCH_ARRAY["Load Switch Array"] subgraph "Intelligent Load Switches" SW_NAV["VBBD5222
Navigation System"] SW_COMM["VBBD5222
Communications"] SW_SIM["VBBD5222
Simulation Computer"] SW_SENSORS["VBBD5222
Sensors & Instruments"] end SWITCH_ARRAY --> SW_NAV SWITCH_ARRAY --> SW_COMM SWITCH_ARRAY --> SW_SIM SWITCH_ARRAY --> SW_SENSORS SW_NAV --> LOAD_NAV["Navigation Loads"] SW_COMM --> LOAD_COMM["Comm Loads"] SW_SIM --> LOAD_SIM["Simulation Loads"] SW_SENSORS --> LOAD_SENS["Sensor Loads"] end subgraph "Power Sequencing & Management" MCU_PWR["Power Management MCU"] subgraph "Sequencing Control" SEQ_LOGIC["Power Sequencing Logic"] FAULT_ISO["Fault Isolation Control"] LOAD_SHED["Load Shedding Control"] end MCU_PWR --> SEQ_LOGIC SEQ_LOGIC --> SW_NAV SEQ_LOGIC --> SW_COMM SEQ_LOGIC --> SW_SIM SEQ_LOGIC --> SW_SENSORS FAULT_ISO --> MCU_PWR LOAD_SHED --> MCU_PWR end subgraph "Gate Drive & Control" subgraph "Complementary Drive Circuit" LEVEL_SHIFTER["Level Shifter Circuit"] GATE_DRV["Gate Drive Buffer"] ANTI_SHOOT["Anti-Shoot-Through Logic"] end MCU_PWR --> LEVEL_SHIFTER LEVEL_SHIFTER --> GATE_DRV GATE_DRV --> Q_OR_N GATE_DRV --> Q_OR_P ANTI_SHOOT --> GATE_DRV end subgraph "Protection & Monitoring" subgraph "Per-Channel Protection" CURRENT_SENSE["Current Sensing per Path"] OCP["Over-Current Protection"] UVLO["Under-Voltage Lockout"] end CURRENT_SENSE --> MCU_PWR OCP --> MCU_PWR UVLO --> MCU_PWR end subgraph "Thermal Management" SYMM_COPPER["Symmetrical Copper Relief"] PWR_VIAS["Thermal Vias under Package"] SYMM_COPPER --> PWR_VIAS PWR_VIAS --> Q_OR_P end style Q_OR_P fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU_PWR fill:#fce4ec,stroke:#e91e63,stroke-width:2px
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