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Optimization of Power Chain for Industrial Variable Frequency Drives: A Precise MOSFET Selection Scheme Based on Front-End PFC, Inverter Bridge, and Internal Power Management
Industrial VFD Power Chain Optimization Topology Diagram

Industrial VFD Power Chain Overall Topology Diagram

graph LR %% Grid Input & Power Conditioning Section subgraph "Grid Input & Power Factor Correction (PFC)" GRID_IN["Three-Phase 380VAC Grid Input"] --> EMI_FILTER["EMI Filter
IEC 61000-3-2 Compliant"] EMI_FILTER --> RECTIFIER["Three-Phase Rectifier Bridge"] RECTIFIER --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] PFC_SW_NODE --> Q_PFC["VBMB165R32SE
650V/32A/89mΩ
TO-220F (Isolated)"] Q_PFC --> DC_LINK["High-Voltage DC-Link
~540-600VDC"] PFC_CTRL["PFC Controller IC"] --> GATE_DRV_PFC["Gate Driver"] GATE_DRV_PFC --> Q_PFC DC_LINK -->|Voltage Feedback| PFC_CTRL end %% Main Inverter Power Stage subgraph "Three-Phase Inverter Bridge (Motor Drive)" DC_LINK --> INVERTER_BUS["Inverter DC Bus"] subgraph "Phase U Bridge Leg" Q_UH["VBM1151N
150V/100A/8.5mΩ
TO-220"] Q_UL["VBM1151N
150V/100A/8.5mΩ
TO-220"] end subgraph "Phase V Bridge Leg" Q_VH["VBM1151N
150V/100A/8.5mΩ
TO-220"] Q_VL["VBM1151N
150V/100A/8.5mΩ
TO-220"] end subgraph "Phase W Bridge Leg" Q_WH["VBM1151N
150V/100A/8.5mΩ
TO-220"] Q_WL["VBM1151N
150V/100A/8.5mΩ
TO-220"] end INVERTER_BUS --> Q_UH INVERTER_BUS --> Q_VH INVERTER_BUS --> Q_WH Q_UH --> U_OUT["Phase U Output"] Q_VH --> V_OUT["Phase V Output"] Q_WH --> W_OUT["Phase W Output"] Q_UL --> GND_INV Q_VL --> GND_INV Q_WL --> GND_INV U_OUT --> Q_UL V_OUT --> Q_VL W_OUT --> Q_WL U_OUT --> MOTOR["Three-Phase AC Motor
Variable Frequency/Torque"] V_OUT --> MOTOR W_OUT --> MOTOR end %% Internal Auxiliary Power System subgraph "Internal Power Management & DC-DC Conversion" DC_LINK --> AUX_DC_IN["Auxiliary Power Input"] AUX_DC_IN --> Q_DCDC["VBP1601
60V/150A/1mΩ
TO-247"] Q_DCDC --> DCDC_INDUCTOR["Buck Inductor
High Current"] DCDC_INDUCTOR --> FILTER_CAP["Output Filter Capacitors"] FILTER_CAP --> 12V_RAIL["12V Rail
(Gate Drivers, Control)"] FILTER_CAP --> 24V_RAIL["24V Rail
(Fans, Relays, I/O)"] DCDC_CTRL["DC-DC Controller"] --> GATE_DRV_DCDC["Gate Driver"] GATE_DRV_DCDC --> Q_DCDC 12V_RAIL -->|Feedback| DCDC_CTRL end %% Control & Protection System subgraph "Control, Monitoring & Protection" MCU["Main DSP/FPGA Controller"] --> PWM_GEN["SVPWM Generator"] PWM_GEN --> GATE_DRV_LOGIC["Gate Driver Logic"] GATE_DRV_LOGIC --> GATE_DRV_U["Phase U Driver"] GATE_DRV_LOGIC --> GATE_DRV_V["Phase V Driver"] GATE_DRV_LOGIC --> GATE_DRV_W["Phase W Driver"] GATE_DRV_U --> Q_UH GATE_DRV_U --> Q_UL GATE_DRV_V --> Q_VH GATE_DRV_V --> Q_VL GATE_DRV_W --> Q_WH GATE_DRV_W --> Q_WL subgraph "Protection Circuits" DESAT_PROT["Desaturation Detection"] OC_SENSE["Current Sensing (Shunt/Hall)"] OVERVOLT["DC-Link Overvoltage"] TEMPERATURE["Thermal Sensors"] end OC_SENSE --> MCU OVERVOLT --> MCU TEMPERATURE --> MCU DESAT_PROT --> GATE_DRV_U DESAT_PROT --> GATE_DRV_V DESAT_PROT --> GATE_DRV_W end %% Thermal Management Hierarchy subgraph "Hierarchical Thermal Management" subgraph "Level 1: Forced Air Cooling" HEATSINK_INV["Central Forced-Air Heatsink"] --> Q_UH HEATSINK_INV --> Q_UL HEATSINK_INV --> Q_VH HEATSINK_INV --> Q_VL HEATSINK_INV --> Q_WH HEATSINK_INV --> Q_WL end subgraph "Level 2: Shared/Forced Cooling" HEATSINK_PFC["Shared Heatsink Section"] --> Q_PFC end subgraph "Level 3: PCB Conduction" PCB_COPPER["PCB Thermal Plane"] --> Q_DCDC end FAN_CONTROL["Fan PWM Control"] --> COOLING_FAN["Cooling Fan"] MCU --> FAN_CONTROL end %% Communication & Interfaces MCU --> COMM_MODULE["Communication Module
Modbus, Profibus, Ethernet"] MCU --> HMI["Human-Machine Interface"] %% Style Definitions style Q_PFC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_UH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_DCDC fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Preface: Engineering the "Power Heart" for Industrial Automation – A Systems Approach to Robustness and Efficiency
In the realm of industrial automation, the Variable Frequency Drive (VFD) stands as a critical actuator, converting grid power into precisely controlled mechanical motion. Its performance—encompassing efficiency, dynamic response, reliability, and power density—is fundamentally anchored in the selection and integration of its power semiconductor devices. Beyond mere electrical specifications, this choice represents a deep understanding of topological requirements, thermal constraints under continuous operation, and the harsh electromagnetic environment of industrial settings.
This article adopts a holistic, system-level design perspective to address the core challenges within a VFD's power chain: how to select an optimal set of power MOSFETs for the three critical functional blocks—front-end Active Power Factor Correction (PFC)/rectification, the main three-phase inverter bridge, and internal high-efficiency power conversion—under the stringent demands of high reliability, thermal robustness, cost-effectiveness, and compliance with industrial standards.
Within a VFD design, the power conversion stage dictates overall efficiency, torque output quality, cabinet size, and long-term service life. Based on comprehensive analysis of voltage stress, conduction/switching losses, package power handling, and system partitioning, this article selects three key devices to construct a balanced, high-performance power solution.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The Grid Interface Guardian: VBMB165R32SE (650V, 32A, 89mΩ, TO-220F) – Front-End Active PFC / Boost Switch
Core Positioning & Topology Deep Dive: Ideally suited for the boost switch in a continuous conduction mode (CCM) PFC stage or as an active component in a bridgeless PFC topology. Its 650V Super Junction (SJ) technology offers an exceptional balance between low specific on-resistance (Rds(on)) and low gate charge (Qg), which is critical for high-frequency (e.g., 50kHz-100kHz) operation to meet stringent harmonic standards (e.g., IEC 61000-3-2). The 650V rating provides robust margin for universal input voltage ranges (85-265VAC) and line transients.
Key Technical Parameter Analysis:
Efficiency-Centric Design: The 89mΩ Rds(on) ensures low conduction loss at rated current. The fast switching capability of the SJ MOSFET minimizes turn-on/turn-off losses, directly contributing to a high-efficiency (>98%) PFC stage, reducing heatsink requirements.
Integrated Fast Recovery Body Diode: The inherent body diode characteristics of SJ MOSFETs are adequate for the discontinuous current mode in PFC, but for hard-switching applications, its reverse recovery performance must be evaluated. The TO-220F (fully isolated) package simplifies insulation and thermal interface to the heatsink.
Selection Trade-off: Compared to standard planar MOSFETs, the SJ technology offers significantly lower FOM (Figure of Merit: Rds(on)Qg). This makes it superior for high-frequency PFC, where switching loss dominates.
2. The Workhorse of Motion Control: VBM1151N (150V, 100A, 8.5mΩ, TO-220) – Inverter Output Bridge Switch
Core Positioning & System Benefit: Positioned as the core switch in the three-phase inverter bridge for lower-voltage VFD applications (e.g., supplying 48V or lower three-phase motors) or as the switch in a multi-level topology segment. Its exceptionally low Rds(on) of 8.5mΩ at 10V is pivotal for minimizing conduction losses, which are the primary loss component in the inverter during high-load, low-speed operation.
Maximizing Output Capability & Efficiency: Low conduction loss translates directly into higher continuous and peak output current capability for a given thermal design, enabling the drive to handle heavy starting loads and overload conditions.
Thermal Design Simplification: The low Rds(on) reduces heat generation significantly. The standard TO-220 package offers excellent thermal coupling to a common heatsink shared by all six bridge switches, simplifying the cooling system.
Robustness for Industrial Environment: The 150V rating offers substantial derating for 48V or 72V DC bus systems, enhancing resilience against voltage spikes induced by long motor cables or regenerative events.
3. The Internal Energy Dispatcher: VBP1601 (60V, 150A, 1mΩ, TO-247) – High-Current, Low-Voltage DC-DC Converter Switch
Core Positioning & System Integration Advantage: This device is engineered for the most demanding low-voltage, high-current conversion points within the VFD. Its primary role is as the main switch in a high-efficiency, non-isolated DC-DC converter (e.g., Buck converter) that generates low-voltage rails (e.g., 12V, 24V) from the DC-Link to power gate drivers, controllers, fans, and relays.
Ultimate Efficiency for Auxiliary Power: An ultra-low Rds(on) of 1mΩ is critical here, as this converter often runs continuously. Minimizing loss here improves overall system efficiency and reduces internal heat buildup within the control cabinet.
Handling Intrush Currents: The high current rating (150A) and robust TO-247 package provide ample headroom to handle the intrush currents of multiple capacitive loads and fans, ensuring stable auxiliary power during dynamic operations.
Power Density Enabler: High efficiency allows for a smaller magnetics and a more compact layout for the internal power supply, freeing up valuable space within the drive enclosure.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Synergy
PFC Controller Synchronization: The gate drive for the VBMB165R32SE must be tightly integrated with the PFC controller IC to ensure stable input current shaping and fast response to line variations.
Inverter PWM Precision: The VBM1151N switches are the final executors of the space vector PWM (SVPWM) algorithm. Matched gate drivers with desaturation detection are essential for precise timing, shoot-through protection, and optimal harmonic performance.
Sequencing and Supervision: The VBP1601-based DC-DC converter should feature soft-start controlled by the main DSP/FPGA to ensure orderly power-up of control circuits. Its health can be monitored via output voltage feedback.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Air Cooling): The six VBM1151N inverter switches mounted on a central, forced-air-cooled heatsink constitute the primary thermal management focus.
Secondary Heat Source (Shared Cooling): The VBMB165R32SE for PFC can be mounted on the same primary heatsink or a dedicated section, considering its switching frequency and loss budget.
Tertiary Heat Source (PCB Conduction & Optional Cooling): The VBP1601, due to its very low loss, may be adequately cooled through a large copper area on the PCB and optional connection to the chassis. Its thermal performance must be validated under full auxiliary load.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBMB165R32SE: Requires careful snubber design across the drain-source to dampen ringing caused by PCB inductance and the boost diode's reverse recovery.
VBM1151N: The inverter bridge necessitates a comprehensive protection suite: DC-Link capacitors for bulk filtering, proper gate drive voltage margin, and an effective overcurrent/short-circuit protection scheme (e.g., using desat detection).
VBP1601: Input and output capacitors must be sized to handle high ripple currents. TVS diodes may be needed on its output if feeding long internal cables to inductive loads (fans, relays).
Enhanced Gate Drive Integrity: All gate drive loops must be minimized for low inductance. Series gate resistors should be optimized for a compromise between switching speed and EMI. Clamping Zeners (±15V to ±20V) are mandatory on all gate drivers to protect against transients.
Derating Practice:
Voltage Derating: Operational VDS/VDC for each device should be ≤ 80% of its rated voltage under worst-case conditions (including spikes).
Current & Thermal Derating: Maximum junction temperature (Tjmax) should be derated to ≤ 125°C for long-term reliability. Current ratings should be based on realistic case/PCB temperature and the device's transient thermal impedance, especially for VBP1601 during intrush events.
III. Quantifiable Perspective on Scheme Advantages and Competitor Comparison
Quantifiable Efficiency Gains: Using VBM1151N (8.5mΩ) versus a standard 150V MOSFET with higher Rds(on) can reduce inverter bridge conduction losses by over 25% at full load, directly lowering total drive losses and cooling requirements.
Quantifiable Power Density Improvement: The combination of a high-frequency PFC stage (enabled by VBMB165R32SE) and a highly efficient internal power supply (using VBP1601) allows for smaller passive components (inductors, capacitors, heatsinks), reducing the overall VFD volume by an estimated 15-20% for a given power rating.
Lifecycle Cost & Reliability Optimization: The robust package choices (TO-220F, TO-220, TO-247) and conservative derating lead to a lower failure rate in the field. This reduces warranty costs and unplanned downtime, maximizing the operational availability of the industrial equipment.
IV. Summary and Forward Look
This scheme provides a meticulously optimized power chain for industrial VFDs, addressing the critical nodes from grid interaction and motor control to internal housekeeping power. The philosophy is "right-sizing for the application":
Grid Interface Level – Focus on "High-Frequency Efficiency": Leverage advanced SJ technology to achieve high switching frequency, enabling compact EMI filters and high-power-factor operation.
Power Output Level – Focus on "Robust, Low-Loss Conduction": Employ trench MOSFETs with extremely low Rds(on) for the inverter, where conduction loss is king, ensuring reliable torque delivery.
Internal Power Level – Focus on "Ultra-High Current Density": Utilize the lowest possible Rds(on) device for high-current auxiliary conversion, eliminating it as a thermal bottleneck.
Future Evolution Directions:
Silicon Carbide (SiC) for Premium Performance: For next-generation ultra-compact or ultra-efficient VFDs, replacing the PFC switch (VBMB165R32SE) with a SiC MOSFET can push switching frequencies beyond 100kHz, dramatically shrinking the PFC inductor. The inverter bridge could also migrate to SiC for drastically reduced switching losses.
Integrated Modules & Intelligent Gate Drivers: For higher power levels, consider IPM (Intelligent Power Modules) or custom hybrid modules that integrate the inverter bridge and drivers. For discrete designs, using gate driver ICs with advanced protection and diagnostics simplifies development and enhances system monitoring.
Engineers can adapt and refine this framework based on specific VFD parameters such as input voltage range (e.g., 1-phase/3-phase), output power rating, motor voltage class, and required enclosure protection (IP rating), thereby designing robust, efficient, and reliable industrial variable frequency drives.

Detailed Topology Diagrams

Front-End PFC & Rectification Topology Detail

graph LR subgraph "Three-Phase Input Stage" A["Three-Phase 380VAC L1"] --> EMI1["EMI Filter"] B["Three-Phase 380VAC L2"] --> EMI2["EMI Filter"] C["Three-Phase 380VAC L3"] --> EMI3["EMI Filter"] EMI1 --> RECT1["Rectifier Diode"] EMI2 --> RECT2["Rectifier Diode"] EMI3 --> RECT3["Rectifier Diode"] end subgraph "CCM PFC Boost Converter" RECT1 --> PFC_INDUCTOR["PFC Inductor"] RECT2 --> PFC_INDUCTOR RECT3 --> PFC_INDUCTOR PFC_INDUCTOR --> SW_NODE["Boost Switching Node"] SW_NODE --> Q_PFC["VBMB165R32SE
650V/32A/89mΩ"] Q_PFC --> DC_PLUS["DC-Link Positive (+)"] SW_NODE --> BOOST_DIODE["Fast Recovery Diode"] BOOST_DIODE --> DC_PLUS RECT1 --> DC_MINUS["DC-Link Negative (-)"] RECT2 --> DC_MINUS RECT3 --> DC_MINUS DC_PLUS --> DC_CAP["DC-Link Capacitor Bank"] DC_MINUS --> DC_CAP end subgraph "Control & Protection" PFC_IC["PFC Controller"] --> GATE_DRV["Gate Driver"] GATE_DRV --> Q_PFC DC_PLUS --> VOLTAGE_DIV["Voltage Sensing"] VOLTAGE_DIV --> PFC_IC PFC_INDUCTOR --> CURRENT_SENSE["Current Sensing"] CURRENT_SENSE --> PFC_IC end subgraph "Protection Components" SNUBBER["RCD Snubber Network"] --> Q_PFC TVS_ARRAY["Transient Voltage Suppressors"] --> DC_PLUS TVS_ARRAY --> DC_MINUS end style Q_PFC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Three-Phase Inverter Bridge & Motor Drive Topology Detail

graph LR subgraph "Three-Phase Inverter Bridge" DC_PLUS["DC-Link Positive (+)"] DC_MINUS["DC-Link Negative (-)"] subgraph "Phase U Half-Bridge" Q_UH["VBM1151N
High-Side"] Q_UL["VBM1151N
Low-Side"] end subgraph "Phase V Half-Bridge" Q_VH["VBM1151N
High-Side"] Q_VL["VBM1151N
Low-Side"] end subgraph "Phase W Half-Bridge" Q_WH["VBM1151N
High-Side"] Q_WL["VBM1151N
Low-Side"] end DC_PLUS --> Q_UH DC_PLUS --> Q_VH DC_PLUS --> Q_WH Q_UH --> U_OUT["U Phase Output"] Q_VH --> V_OUT["V Phase Output"] Q_WH --> W_OUT["W Phase Output"] U_OUT --> Q_UL V_OUT --> Q_VL W_OUT --> Q_WL Q_UL --> DC_MINUS Q_VL --> DC_MINUS Q_WL --> DC_MINUS end subgraph "Gate Drive & Protection" subgraph "Phase U Gate Drive" DRV_U["Gate Driver IC"] --> DESAT_U["Desaturation Detection"] DRV_U --> Q_UH_GATE["Gate Signal"] DRV_U --> Q_UL_GATE["Gate Signal"] Q_UH_GATE --> Q_UH Q_UL_GATE --> Q_UL end subgraph "Phase V Gate Drive" DRV_V["Gate Driver IC"] --> DESAT_V["Desaturation Detection"] DRV_V --> Q_VH_GATE["Gate Signal"] DRV_V --> Q_VL_GATE["Gate Signal"] Q_VH_GATE --> Q_VH Q_VL_GATE --> Q_VL end subgraph "Phase W Gate Drive" DRV_W["Gate Driver IC"] --> DESAT_W["Desaturation Detection"] DRV_W --> Q_WH_GATE["Gate Signal"] DRV_W --> Q_WL_GATE["Gate Signal"] Q_WH_GATE --> Q_WH Q_WL_GATE --> Q_WL end PWM_GEN["SVPWM Generator"] --> DRV_U PWM_GEN --> DRV_V PWM_GEN --> DRV_W end subgraph "Current Sensing & Feedback" SHUNT_U["Shunt Resistor"] --> U_OUT SHUNT_V["Shunt Resistor"] --> V_OUT SHUNT_U --> AMP_U["Current Amplifier"] SHUNT_V --> AMP_V["Current Amplifier"] AMP_U --> MCU["Main Controller"] AMP_V --> MCU end subgraph "Output Filter & Motor Connection" U_OUT --> FILTER_U["Output Filter"] V_OUT --> FILTER_V["Output Filter"] W_OUT --> FILTER_W["Output Filter"] FILTER_U --> MOTOR_U["Motor Phase U"] FILTER_V --> MOTOR_V["Motor Phase V"] FILTER_W --> MOTOR_W["Motor Phase W"] end subgraph "Thermal Management" HEATSINK["Common Heatsink"] --> Q_UH HEATSINK --> Q_UL HEATSINK --> Q_VH HEATSINK --> Q_VL HEATSINK --> Q_WH HEATSINK --> Q_WL TEMP_SENSOR["Temperature Sensor"] --> MCU end style Q_UH fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_UL fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Internal Power Management & Auxiliary Supply Topology Detail

graph LR subgraph "High-Current Buck Converter" DC_IN["DC-Link Input (540-600V)"] --> HV_TO_LV["High-to-Low Voltage Converter"] HV_TO_LV --> BUCK_IN["Intermediate Bus (~48V)"] BUCK_IN --> Q_MAIN["VBP1601
60V/150A/1mΩ"] Q_MAIN --> SW_NODE["Switching Node"] SW_NODE --> POWER_INDUCTOR["High-Current Inductor
Low DCR"] POWER_INDUCTOR --> OUTPUT_CAPS["Low-ESR Capacitor Array"] OUTPUT_CAPS --> MAIN_12V["12V Main Rail"] OUTPUT_CAPS --> MAIN_24V["24V Main Rail"] BUCK_CONTROLLER["Buck Controller"] --> GATE_DRIVER["High-Current Gate Driver"] GATE_DRIVER --> Q_MAIN MAIN_12V --> VOLTAGE_FEEDBACK["Voltage Feedback"] VOLTAGE_FEEDBACK --> BUCK_CONTROLLER end subgraph "Load Distribution & Sequencing" MAIN_12V --> subgraph "12V Loads" GATE_DRV_PWR["Gate Driver Power"] MCU_PWR["DSP/FPGA Power"] SENSOR_PWR["Sensor Power"] end MAIN_24V --> subgraph "24V Loads" FAN_PWR["Cooling Fans"] RELAY_PWR["Control Relays"] IO_PWR["Digital I/O Circuits"] DISPLAY_PWR["HMI Display"] end POWER_SEQ["Power Sequencer"] --> SOFT_START["Soft-Start Control"] SOFT_START --> BUCK_CONTROLLER end subgraph "Protection & Monitoring" subgraph "Input Protection" TVS_IN["TVS Diode Array"] FUSE["Input Fuse"] INRUSH_LIMIT["Inrush Current Limiter"] end subgraph "Output Protection" OVP["Overvoltage Protection"] OCP["Overcurrent Protection"] OTP["Overtemperature Protection"] end subgraph "Current Monitoring" SHUNT["Precision Shunt"] CURRENT_AMP["Current Sense Amplifier"] CURRENT_AMP --> MCU_AUX["Auxiliary MCU"] end TVS_IN --> DC_IN FUSE --> DC_IN INRUSH_LIMIT --> BUCK_IN OVP --> MAIN_12V OCP --> POWER_INDUCTOR OTP --> Q_MAIN SHUNT --> MAIN_12V end subgraph "Thermal Design" PCB_THERMAL["PCB Thermal Plane
2oz Copper"] --> Q_MAIN HEATSINK_AUX["Optional Heatsink"] --> Q_MAIN THERMAL_PAD["Thermal Interface Material"] --> Q_MAIN end style Q_MAIN fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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