Industrial Automation

Your present location > Home page > Industrial Automation
MOSFET Selection Strategy and Device Adaptation Handbook for PLC Power Modules with High Reliability and Density Requirements
PLC Power Module MOSFET Topology Diagram

PLC Power Module MOSFET System Overall Topology Diagram

graph LR %% Input & Primary High-Voltage Section subgraph "Primary-Side High-Voltage Switching & PFC Stage" AC_IN["Three-Phase 380VAC Input"] --> EMI_FILTER["EMI Filter & Protection"] EMI_FILTER --> RECTIFIER["Three-Phase Rectifier"] RECTIFIER --> HV_BUS["High-Voltage DC Bus
~400VDC"] HV_BUS --> PFC_CIRCUIT["PFC/Forward/Flyback Circuit"] subgraph "Primary-Side MOSFET Array" Q_PRI1["VBM16R20SFD
600V/20A (TO-220)"] Q_PRI2["VBM16R20SFD
600V/20A (TO-220)"] end PFC_CIRCUIT --> Q_PRI1 PFC_CIRCUIT --> Q_PRI2 Q_PRI1 --> TRANSFORMER["Isolation Transformer
Primary"] Q_PRI2 --> TRANSFORMER end %% Secondary-Side & Power Conversion subgraph "Secondary-Side Synchronous Rectification & DC-DC Stage" TRANSFORMER --> TRANS_SEC["Isolation Transformer
Secondary"] TRANS_SEC --> SYNC_RECT["Synchronous Rectification Bridge"] subgraph "Synchronous Rectification MOSFETs" Q_SR1["VBQA1202
20V/150A (DFN8(5x6))"] Q_SR2["VBQA1202
20V/150A (DFN8(5x6))"] end SYNC_RECT --> Q_SR1 SYNC_RECT --> Q_SR2 Q_SR1 --> BUCK_CONVERTER["Buck/DC-DC Converter"] Q_SR2 --> BUCK_CONVERTER BUCK_CONVERTER --> OUTPUT_RAILS["Output Voltage Rails
24V/12V/5V"] end %% I/O & Peripheral Control Section subgraph "I/O Point Driver & Peripheral Power Switch Stage" OUTPUT_RAILS --> I_O_CONTROL["I/O Control Logic"] subgraph "Intelligent Load Switch Array" Q_IO1["VBA3316SD
30V/6.8A (SOP8 Half-Bridge)"] Q_IO2["VBA3316SD
30V/6.8A (SOP8 Half-Bridge)"] Q_IO3["VBA3316SD
30V/6.8A (SOP8 Half-Bridge)"] end I_O_CONTROL --> Q_IO1 I_O_CONTROL --> Q_IO2 I_O_CONTROL --> Q_IO3 Q_IO1 --> LOAD1["Relay/Solenoid Load"] Q_IO2 --> LOAD2["Sensor/Analog Module"] Q_IO3 --> LOAD3["Communication/Display"] end %% Control & Protection Section subgraph "Control & System Protection" MCU["Main Control MCU/PLC CPU"] --> GATE_DRIVER_PRI["Primary-Side Gate Driver"] MCU --> GATE_DRIVER_SR["Synchronous Rectification Driver"] MCU --> LEVEL_SHIFTER["Logic Level Shifter"] GATE_DRIVER_PRI --> Q_PRI1 GATE_DRIVER_PRI --> Q_PRI2 GATE_DRIVER_SR --> Q_SR1 GATE_DRIVER_SR --> Q_SR2 LEVEL_SHIFTER --> Q_IO1 LEVEL_SHIFTER --> Q_IO2 LEVEL_SHIFTER --> Q_IO3 subgraph "Protection Circuits" OVP["Overvoltage Protection"] OCP["Overcurrent Protection"] THERMAL["Thermal Management"] TVS["TVS/Snubber Circuits"] end OVP --> MCU OCP --> MCU THERMAL --> MCU TVS --> Q_PRI1 TVS --> Q_SR1 end %% Communication & System Interface MCU --> PLC_BUS["PLC Backplane Bus"] MCU --> INDUSTRIAL_IO["Industrial I/O Interface"] MCU --> COMM_MODULE["Communication Module
Ethernet/CAN"] %% Style Definitions style Q_PRI1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_IO1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the evolution of industrial automation towards greater intelligence and integration, Programmable Logic Controller (PLC) power modules, as the core foundation for system power supply and load drive, require power conversion solutions that are highly reliable, efficient, and compact. The selection of power MOSFETs is critical in determining the performance of key circuits such as primary-side switching, secondary-side synchronous rectification, and digital/analog I/O point driving. Addressing the stringent demands of PLC systems for stability, power density, electromagnetic compatibility (EMC), and wide-temperature operation, this article develops a practical and optimized MOSFET selection strategy based on scenario-specific adaptation.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with the harsh industrial environment and long-life operation:
Sufficient Voltage & Ruggedness: For mains-derived high-voltage DC buses (e.g., ~400V DC from 3-phase 380V AC) and low-voltage logic buses (24V/12V/5V), reserve ample voltage margin (≥30% for HV, ≥50% for LV). Prioritize devices with high dv/dt capability and robust gate structure for noise immunity.
Prioritize Low Loss & Efficiency: For always-on or frequently switched paths, prioritize low Rds(on) to minimize conduction loss and low Qg/Qoss to reduce switching loss, directly improving module efficiency and reducing thermal stress.
Package Matching for Density & Cooling: Choose compact, low-thermal-resistance packages (e.g., DFN, SOP8) for secondary-side and driver circuits to maximize power density. For primary-side or higher-power paths, select packages with excellent thermal performance (e.g., TO-220, TO-252) or consider dual-die/ half-bridge integrated configurations to save space and simplify layout.
Reliability & Industrial Grade: Devices must withstand extended temperature cycles, vibration, and electrical noise. Focus on wide junction temperature range (typically -55°C to 150°C or 175°C), high ESD tolerance, and qualification for industrial/automotive standards.
(B) Scenario Adaptation Logic: Categorization by Module Function
Divide the PLC power module into three core functional blocks: First, the primary-side high-voltage switching & PFC stage, requiring high-voltage blocking capability and good switching characteristics. Second, the secondary-side low-voltage synchronous rectification & DC-DC conversion stage, demanding ultra-low conduction loss and high current capability. Third, the digital/analog I/O point driver & peripheral power switching stage, requiring compact integration, logic-level drive, and robust protection. This enables precise device-to-function matching.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: Primary-Side High-Voltage Switching & PFC (Up to 1kW+) – Ruggedness Core
This stage handles rectified mains voltage (~400V DC) and requires high-voltage blocking, reliable switching, and good efficiency.
Recommended Model: VBM16R20SFD (N-MOS, 600V, 20A, TO-220)
Parameter Advantages: Super Junction (SJ_Multi-EPI) technology achieves a good balance between Rds(on) (175mΩ @10V) and switching loss. 600V VDS provides >50% margin for 400V bus, handling voltage spikes reliably. TO-220 package offers excellent thermal capability (RthJC typically <1°C/W) for effective heat sinking.
Adaptation Value: Enables efficient flyback/forward or PFC circuit design. The robust voltage rating and package ensure long-term reliability in demanding industrial environments with unstable mains. Suitable for PLC power modules ranging from 100W to over 1kW output.
Selection Notes: Verify peak current and switching frequency. Ensure proper gate drive (typically 10-12V) and snubber/clamp circuit design. Adequate heatsinking is mandatory for continuous high-power operation.
(B) Scenario 2: Secondary-Side Synchronous Rectification & High-Current DC-DC (5V/12V/24V @ High Current) – Efficiency Core
This stage requires minimal conduction loss to maximize efficiency for CPU core, I/O, and communication board power.
Recommended Model: VBQA1202 (N-MOS, 20V, 150A, DFN8(5x6))
Parameter Advantages: Extremely low Rds(on) of 1.7mΩ @4.5V (Vgs), enabling ultra-low conduction loss. Massive 150A continuous current rating. DFN8(5x6) package offers very low parasitic inductance and good thermal performance via a large exposed pad.
Adaptation Value: Ideal for synchronous buck or synchronous rectification in isolated converters generating 5V/12V/24V rails at currents up to tens of Amperes. Can increase conversion efficiency by 2-5% compared to standard MOSFETs, significantly reducing thermal load in a dense module.
Selection Notes: Requires careful PCB layout with substantial copper pour and thermal vias under the exposed pad for heat dissipation. Gate drive must be strong enough to handle the high intrinsic capacitance quickly. Parallel use may be considered for currents beyond 100A.
(C) Scenario 3: I/O Point Driver & Peripheral Power Switch (24V Logic, <10A) – Integration & Control Core
This stage drives relays, solenoid valves, sensors, and switches power for peripheral cards. Needs compact integration, logic-level compatibility, and protection.
Recommended Model: VBA3316SD (Half-Bridge N+N, 30V, 6.8A/10A, SOP8)
Parameter Advantages: Integrated dual N-MOSFETs in a half-bridge configuration within an SOP8 package, saving >60% board area versus two discrete devices. Low Rds(on) (18mΩ @10V per FET). 30V rating is perfect for 24V systems with margin. Standard Vth (1.7V) allows direct or easy drive from 3.3V/5V MCUs.
Adaptation Value: Provides a compact, high-efficiency solution for driving bidirectional loads (e.g., small DC motors) or constructing H-bridges. Can also be used independently as two high-side or low-side switches for multiple I/O channels, simplifying design and BOM.
Selection Notes: Confirm load type (inductive/resistive) and peak current. For inductive loads, ensure proper freewheeling paths are designed. Pay attention to power dissipation in the small package; provide adequate copper for heat spreading.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBM16R20SFD: Use dedicated gate driver ICs (e.g., IR2110, UCC27524) with peak output current >2A to ensure fast switching and minimize crossover loss. Include gate resistors (1-10Ω) to control dv/dt and damp ringing.
VBQA1202: Requires a very strong gate driver, often a dedicated synchronous rectifier controller (e.g., TPS281x series) or a driver IC capable of sourcing/sinking several Amps. Minimize gate loop inductance.
VBA3316SD: Can be driven directly from MCU GPIO pins for lower frequency switching. For higher frequencies or to reduce MCU stress, use a small buffer IC (e.g., TC4427). Include pull-down resistors on gates if driven by open-drain outputs.
(B) Thermal Management Design: Tiered Approach
VBM16R20SFD (Primary Side): Mount on a main heatsink. Use thermal interface material. Consider system airflow or conduction cooling to the chassis.
VBQA1202 (Secondary Side): Critical. Design a multi-layer PCB with a large, thick-copper (≥2oz) plane connected to the drain pad via multiple thermal vias. This plane acts as the primary heatsink. For very high currents, consider a small clip-on heatsink.
VBA3316SD (I/O Driver): Provide generous copper pours on all pins, especially the source pins connected to the power plane, to aid heat spreading. Typically does not require an external heatsink for rated current.
(C) EMC and Reliability Assurance
EMC Suppression:
Primary Side (VBM16R20SFD): Implement snubber networks (RC/RCD) across the transformer primary or switch node. Use a common-mode choke at the AC input. Ensure proper shielding and grounding of the transformer.
Secondary Side (VBQA1202): Minimize high di/dt loop areas. Use low-ESR bypass capacitors very close to the MOSFETs. Add small ferrite beads in series with output cables if necessary.
I/O Side (VBA3316SD): Use TVS diodes or RC snubbers across inductive loads (solenoids, relays). Implement filtering on I/O connector lines.
Reliability Protection:
Derating: Operate all MOSFETs at ≤80% of rated VDS and ≤70% of rated ID at maximum ambient temperature.
Overcurrent Protection: Implement cycle-by-cycle current limiting in primary-side controllers. Use sense resistors or desaturation detection for secondary-side FETs.
Transient Protection: Use MOVs and/or Gas Discharge Tubes (GDTs) at the AC input. Place TVS diodes on all external I/O and communication lines.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Optimized Performance Hierarchy: Matches high-voltage ruggedness, ultra-low-loss conversion, and high-density control in a single module, achieving overall efficiency >92% for the power supply.
Enhanced Reliability & Density: The selected packages and ratings ensure stable operation in 24/7 industrial environments while maximizing board space utilization for additional features.
Design Simplification: Using integrated half-bridge (VBA3316SD) and high-current single FET (VBQA1202) reduces component count, layout complexity, and assembly cost.
(B) Optimization Suggestions
Higher Power Primary: For PLC power modules >1.5kW, consider VBE16R15SFD (600V, 15A, TO-252) for a more compact footprint or parallel devices.
Higher Voltage Secondary: For generating 48V or higher intermediate buses, consider VBNC1405 (60V, 75A, TO-262) for synchronous rectification.
Compact High-Side Switch: For space-constrained 24V high-side switching, VBA4235 (Dual P+P, -20V, -5.4A, SOP8) offers a compact, integrated solution.
Low-Voltage High-Current Alternative: For very high current at ≤12V, VBFB1806 (80V, 75A, TO-251) provides a cost-effective, easy-to-mount option.
Conclusion
Strategic MOSFET selection is fundamental to building PLC power modules that are reliable, efficient, and compact. This scenario-based approach, leveraging devices like the rugged VBM16R20SFD, the ultra-efficient VBQA1202, and the integrated VBA3316SD, provides a clear roadmap for design engineers. Future developments can explore the use of wide-bandgap (SiC) devices for the primary side in ultra-high-efficiency designs and further integration via Intelligent Power Modules (IPMs) for motor drive sections, pushing the boundaries of PLC performance and functionality.

Detailed Topology Diagrams

Primary-Side High-Voltage Switching & PFC Stage

graph LR subgraph "Three-Phase Input & Rectification" A["Three-Phase 380VAC"] --> B["EMI Filter & MOV/GDT Protection"] B --> C["Three-Phase Rectifier Bridge"] C --> D["High-Voltage DC Bus
~400VDC"] end subgraph "PFC/Forward Converter Topology" D --> E["DC Bus Capacitors"] E --> F["VBM16R20SFD
High-Side Switch"] F --> G["PFC Inductor / Transformer Primary"] G --> H["VBM16R20SFD
Low-Side Switch"] H --> I["Primary Ground"] J["PFC/Flyback Controller"] --> K["Gate Driver IC"] K --> F K --> H L["Current Sense"] --> J M["Voltage Feedback"] --> J end subgraph "Protection & Snubber Networks" N["RCD Snubber Circuit"] --> F O["RC Absorption"] --> H P["TVS Array"] --> K end style F fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style H fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Secondary-Side Synchronous Rectification & High-Current DC-DC

graph LR subgraph "Synchronous Rectification Bridge" A["Transformer Secondary"] --> B["Synchronous Rectification Node"] B --> C["VBQA1202
High-Side MOSFET"] C --> D["Output Inductor"] D --> E["Output Capacitors"] E --> F["24V/12V/5V Output"] B --> G["VBQA1202
Low-Side MOSFET"] G --> H["Secondary Ground"] end subgraph "Multi-Rail DC-DC Buck Converters" F --> I["24V Buck Converter"] F --> J["12V Buck Converter"] F --> K["5V Buck Converter"] subgraph "Synchronous Buck MOSFETs" I1["VBQA1202
High-Side"] I2["VBQA1202
Low-Side"] J1["VBQA1202
High-Side"] J2["VBQA1202
Low-Side"] K1["VBQA1202
High-Side"] K2["VBQA1202
Low-Side"] end I --> I1 I --> I2 J --> J1 J --> J2 K --> K1 K --> K2 I1 --> L["24V Output Rail"] I2 --> M["24V Ground"] J1 --> N["12V Output Rail"] J2 --> O["12V Ground"] K1 --> P["5V Output Rail"] K2 --> Q["5V Ground"] end subgraph "Control & Drive" R["Synchronous Rectification Controller"] --> S["High-Current Gate Driver"] T["Buck Controller 24V"] --> U["Dual-Channel Driver"] V["Buck Controller 12V"] --> W["Dual-Channel Driver"] X["Buck Controller 5V"] --> Y["Dual-Channel Driver"] S --> C S --> G U --> I1 U --> I2 W --> J1 W --> J2 Y --> K1 Y --> K2 end style C fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style I1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

I/O Point Driver & Peripheral Power Switch Stage

graph LR subgraph "MCU Control Interface" MCU["PLC MCU
3.3V/5V Logic"] --> LEVEL_SHIFTER["Level Shifter Array"] end subgraph "Integrated Half-Bridge Driver Channels" LEVEL_SHIFTER --> CH1_IN["Channel 1 Control"] LEVEL_SHIFTER --> CH2_IN["Channel 2 Control"] LEVEL_SHIFTER --> CH3_IN["Channel 3 Control"] LEVEL_SHIFTER --> CH4_IN["Channel 4 Control"] subgraph "Dual Half-Bridge Devices" HB1["VBA3316SD
Dual N+N Half-Bridge"] HB2["VBA3316SD
Dual N+N Half-Bridge"] end CH1_IN --> HB1 CH2_IN --> HB1 CH3_IN --> HB2 CH4_IN --> HB2 end subgraph "Load Connections & Protection" HB1 --> LOAD1["Relay Coil / Solenoid"] HB1 --> LOAD2["Analog Sensor Module"] HB2 --> LOAD3["Communication Interface"] HB2 --> LOAD4["Display Unit"] subgraph "Load Protection Circuits" TVS1["TVS Diode Array"] --> LOAD1 SNUBBER1["RC Snubber"] --> LOAD2 TVS2["TVS Diode"] --> LOAD3 FILTER["EMI Filter"] --> LOAD4 end LOAD1 --> GND LOAD2 --> GND LOAD3 --> GND LOAD4 --> GND end subgraph "Power Distribution" PWR_24V["24V Power Rail"] --> HB1 PWR_24V --> HB2 PWR_24V --> LOAD1 PWR_24V --> LOAD2 PWR_24V --> LOAD3 PWR_24V --> LOAD4 end style HB1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style HB2 fill:#fff3e0,stroke:#ff9800,stroke-width:2px
Download PDF document
Download now:VBE16R15SFD

Sample Req

Online

Telephone

400-655-8788

WeChat

Topping

Sample Req
Online
Telephone
WeChat