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Preface: Forging the "Intelligent Power Hub" for Precision Motion – A Systems Approach to Power Device Selection in AI Industrial Servo Drives
AI Industrial Servo Drive Power Module System Topology Diagram

AI Industrial Servo Drive Power System Overall Topology Diagram

graph LR %% Input & High-Voltage Bus Generation Section subgraph "Three-Phase Input & High-Voltage Bus Generation" AC_IN["Three-Phase 480VAC Input"] --> EMI_FILTER["EMI Input Filter"] EMI_FILTER --> RECTIFIER["Three-Phase Rectifier Bridge"] RECTIFIER --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_SW_NODE["PFC Switching Node"] subgraph "High-Voltage PFC MOSFET Array" Q_PFC1["VBMB18R11SE
800V/11A SJ_Deep-Trench"] Q_PFC2["VBMB18R11SE
800V/11A SJ_Deep-Trench"] end PFC_SW_NODE --> Q_PFC1 PFC_SW_NODE --> Q_PFC2 Q_PFC1 --> HV_BUS["High-Voltage DC Bus"] Q_PFC2 --> HV_BUS HV_BUS --> MAIN_INV_NODE["Main Inverter Bridge Node"] subgraph "Main Inverter Bridge" Q_INV1["VBMB18R11SE
800V/11A"] Q_INV2["VBMB18R11SE
800V/11A"] end MAIN_INV_NODE --> Q_INV1 MAIN_INV_NODE --> Q_INV2 Q_INV1 --> GND_HV Q_INV2 --> GND_HV end %% Multi-Axis Servo Drive Section subgraph "Multi-Axis Servo Drive Inverter Stage" HV_BUS --> DC_DC["DC-DC Converter"] DC_DC --> LV_BUS["Low-Voltage DC Bus
48V/72V"] subgraph "Axis 1 Drive Bridge" Q_A1_H["VBM1807
80V/90A"] Q_A1_L["VBM1807
80V/90A"] end subgraph "Axis 2 Drive Bridge" Q_A2_H["VBM1807
80V/90A"] Q_A2_L["VBM1807
80V/90A"] end subgraph "Axis 3 Drive Bridge" Q_A3_H["VBM1807
80V/90A"] Q_A3_L["VBM1807
80V/90A"] end LV_BUS --> Q_A1_H LV_BUS --> Q_A2_H LV_BUS --> Q_A3_H Q_A1_H --> MOTOR_A1["Servo Motor Axis 1"] Q_A1_L --> MOTOR_A1 Q_A2_H --> MOTOR_A2["Servo Motor Axis 2"] Q_A2_L --> MOTOR_A2 Q_A3_H --> MOTOR_A3["Servo Motor Axis 3"] Q_A3_L --> MOTOR_A3 Q_A1_L --> GND_LV Q_A2_L --> GND_LV Q_A3_L --> GND_LV end %% Auxiliary Power & Intelligent Management Section subgraph "Auxiliary Power & System Management" AUX_POWER["Auxiliary Power Supply"] --> CONTROL_RAIL["12V/24V Control Rail"] subgraph "Intelligent Power Management Switches" SW_BRAKE["VBQG2216
Brake Circuit Control"] SW_FAN["VBQG2216
Cooling Fan Control"] SW_SENSOR["VBQG2216
Sensor Power"] SW_COMM["VBQG2216
Communication Interface"] end CONTROL_RAIL --> SW_BRAKE CONTROL_RAIL --> SW_FAN CONTROL_RAIL --> SW_SENSOR CONTROL_RAIL --> SW_COMM SW_BRAKE --> BRAKE_RES["Brake Resistor Circuit"] SW_FAN --> COOLING_FAN["Cooling Fans"] SW_SENSOR --> SENSORS["Position/Current Sensors"] SW_COMM --> COMM_MODULE["EtherCAT/CAN Interface"] end %% Control & Protection System subgraph "Control & Protection System" MAIN_MCU["Main Control MCU/DSP"] --> GATE_DRIVER_HV["High-Voltage Gate Driver"] MAIN_MCU --> GATE_DRIVER_LV["Low-Voltage Gate Driver"] MAIN_MCU --> SYS_MGMT["System Management IC"] GATE_DRIVER_HV --> Q_PFC1 GATE_DRIVER_HV --> Q_PFC2 GATE_DRIVER_HV --> Q_INV1 GATE_DRIVER_HV --> Q_INV2 GATE_DRIVER_LV --> Q_A1_H GATE_DRIVER_LV --> Q_A1_L GATE_DRIVER_LV --> Q_A2_H GATE_DRIVER_LV --> Q_A2_L GATE_DRIVER_LV --> Q_A3_H GATE_DRIVER_LV --> Q_A3_L SYS_MGMT --> SW_BRAKE SYS_MGMT --> SW_FAN SYS_MGMT --> SW_SENSOR SYS_MGMT --> SW_COMM subgraph "Protection Circuits" CURRENT_SENSE["High-Precision Current Sensing"] VOLTAGE_SENSE["Bus Voltage Monitoring"] TEMPERATURE_SENSE["NTC Temperature Sensors"] SNUBBER_CIRCUIT["RCD Snubber Network"] end CURRENT_SENSE --> MAIN_MCU VOLTAGE_SENSE --> MAIN_MCU TEMPERATURE_SENSE --> MAIN_MCU SNUBBER_CIRCUIT --> Q_PFC1 SNUBBER_CIRCUIT --> Q_PFC2 end %% Hierarchical Thermal Management subgraph "Three-Level Thermal Management" COOLING_LEVEL1["Level 1: Forced Air/Cold Plate
Multi-Axis Drive MOSFETs"] COOLING_LEVEL2["Level 2: Forced Air Cooling
High-Voltage MOSFETs"] COOLING_LEVEL3["Level 3: PCB Conduction
Control ICs & Small Switches"] COOLING_LEVEL1 --> Q_A1_H COOLING_LEVEL1 --> Q_A1_L COOLING_LEVEL1 --> Q_A2_H COOLING_LEVEL1 --> Q_A2_L COOLING_LEVEL1 --> Q_A3_H COOLING_LEVEL1 --> Q_A3_L COOLING_LEVEL2 --> Q_PFC1 COOLING_LEVEL2 --> Q_PFC2 COOLING_LEVEL2 --> Q_INV1 COOLING_LEVEL2 --> Q_INV2 COOLING_LEVEL3 --> MAIN_MCU COOLING_LEVEL3 --> SYS_MGMT COOLING_LEVEL3 --> VBQG2216 end %% Communication & Interface MAIN_MCU --> MOTION_BUS["EtherCAT Motion Bus"] MAIN_MCU --> SAFETY_IO["Safety I/O Interface"] MAIN_MCU --> AI_MODULE["AI Processing Module"] %% Style Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_A1_H fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SW_BRAKE fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MAIN_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

In the era of AI-driven industrial automation, a high-performance servo drive is far more than a simple motor controller. It is a dynamic, real-time "intelligent power hub" responsible for executing complex motion profiles with utmost precision, efficiency, and reliability. Its core capabilities—ultra-fast dynamic response, multi-axis synchronous control, and maximized energy efficiency—are fundamentally anchored in the performance of its power conversion chain. This article adopts a holistic, system-co-design perspective to address the critical challenge in AI servo drive development: selecting the optimal power MOSFETs for the key nodes of high-voltage bus generation, multi-axis low-voltage motor drive, and intelligent auxiliary power management, under stringent demands for power density, thermal performance, switching speed, and cost.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Voltage Gatekeeper: VBMB18R11SE (800V, 11A, SJ_Deep-Trench, TO-220F) – PFC / Main Inverter Bridge Switch
Core Positioning & Topology Deep Dive: Engineered for the critical front-end stage, such as Active Power Factor Correction (PFC) or the inverter bridge in drives operating from a 480VAC line. Its 800V drain-source voltage rating provides a robust safety margin for universal input voltages and surge events. The Super Junction Deep-Trench technology is pivotal for achieving low conduction loss (Rds(on)=350mΩ) and minimized switching losses simultaneously at high voltages, a key for high-efficiency PFC stages operating at elevated frequencies (e.g., 50-100kHz).
Key Technical Parameter Analysis:
Voltage Robustness & Technology Edge: The 800V rating future-proofs the design for harsh industrial grids. The Deep-Trench SJ process optimizes the charge balance, enabling faster switching compared to planar MOSFETs, which directly reduces turn-on/turn-off losses in hard-switching PFC topologies.
TO-220F Package Advantage: The fully isolated package simplifies thermal interface to heatsinks, enhancing isolation safety and improving heat dissipation in compact, multi-module designs.
Selection Trade-off: This device represents the optimal balance between high-voltage withstand capability, switching frequency potential, and cost for the main power inlet stage, compared to lower-voltage-rated devices or slower IGBTs.
2. The Muscle of Multi-Axis Drive: VBM1807 (80V, 90A, Trench, TO-220) – Multi-Channel Servo Motor Phase-Leg Switch
Core Positioning & System Benefit: This device is the workhorse for the individual axis drive inverter legs, typically supplied from a lower DC bus (e.g., 48V or 72V). Its exceptionally low Rds(on) of 7.7mΩ @10V is critical for minimizing conduction losses, which dominate at high continuous currents during torque production.
Maximized System Efficiency & Power Density: Lower conduction loss translates directly into higher drive efficiency, reduced heatsink size, and enables more compact multi-axis drive packaging.
Enhanced Dynamic Current Delivery: The low Rds(on) combined with a high continuous current rating (90A) ensures the drive can deliver the peak currents required for rapid acceleration/deceleration and overload conditions with minimal voltage drop.
Thermal Management Simplification: The low loss characteristic significantly reduces the thermal load, allowing for simpler cooling solutions or higher ambient temperature operation.
3. The Intelligent System Regulator: VBQG2216 (Dual -20V, -10A, Trench, DFN6(2x2)) – Low-Voltage Auxiliary & Brake Circuit Management Switch
Core Positioning & System Integration Advantage: This dual P-Channel MOSFET in a tiny DFN package is the cornerstone for intelligent, space-constrained power management within the drive. It is ideally suited for managing 12V/24V auxiliary rails (e.g., for control logic, fans, sensors) and for implementing dynamic brake control circuits.
Application Example: One channel can be used for enabling/disabling a brake resistor circuit under bus over-voltage conditions, while the other manages power to peripheral interfaces or cooling fans, all under digital control from the drive's microcontroller.
PCB Design Value: The ultra-compact DFN6 package offers immense space savings, crucial for modern, densely populated servo drive PCBs. The dual integration reduces component count and simplifies routing.
Reason for P-Channel Selection: As a high-side switch directly on the positive auxiliary rail, it can be controlled with simple logic-level signals without needing a charge pump, simplifying the gate drive circuitry and enhancing reliability for always-on or frequently switched auxiliary loads.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Loop Synergy
High-Frequency PFC Control: The gate drive for VBMB18R11SE must be low-inductance and capable of high peak currents to swiftly charge/discharge its gate, ensuring clean switching transitions that are synchronized with the PFC controller's high-frequency PWM to maintain high power factor and low THD.
Precision Multi-Axis Inverter Control: The VBM1807 devices, acting as the final power stage for each servo axis, require tightly matched gate drive timing and strength to ensure current loop fidelity in Field-Oriented Control (FOC). Dedicated gate drivers per phase leg are essential for signal integrity and protection.
Digital Power Management: The gates of VBQG2216 should be driven by GPIOs or PWM outputs from the drive's main processor or a dedicated system management IC, allowing for software-defined power sequencing, soft-start, and immediate shutdown in fault conditions.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Air/Cold Plate Cooling): The VBM1807 devices across multiple axes will collectively generate significant heat. They must be mounted on a common, carefully sized heatsink with forced air cooling or integrated into a liquid-cooled cold plate.
Secondary Heat Source (Forced Air Cooling): The VBMB18R11SE in the PFC stage, while potentially fewer in number, operates at high voltage and switching frequency. It requires its own dedicated cooling area on the main heatsink or a separate smaller heatsink.
Tertiary Heat Source (PCB Conduction & Natural Airflow): The VBQG2216, due to its low power dissipation and small package, relies on thermal vias and adequate copper pours on the PCB to dissipate heat to the internal layers and board surface.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBMB18R11SE: Snubber networks (RC or RCD) across the drain-source are critical to clamp voltage spikes caused by parasitic inductance in the high-current, high-di/dt PFC loop.
VBM1807: Attention must be paid to the body diode reverse recovery during dead-time. The use of external Schottky diodes in parallel might be considered for ultra-high switching frequency applications to reduce losses.
VBQG2216: For inductive auxiliary loads (e.g., small fans, solenoids), freewheeling paths must be provided to absorb the turn-off energy.
Enhanced Gate Protection: All gate drive loops should be compact with optimized series gate resistors. TVS diodes or Zener clamps (e.g., ±15V for VBM1807/VBQG2216, ±30V for VBMB18R11SE) from gate to source are mandatory to prevent Vgs overshoot/undershoot.
Derating Practice:
Voltage Derating: Ensure VDS stress on VBMB18R11SE remains below 640V (80% of 800V). For VBM1807, VDS should have margin above the maximum boosted DC bus voltage.
Current & Thermal Derating: Base the maximum continuous and pulsed current on the junction temperature rise calculated from Rds(on) vs. Tj curves, RθJC, and the actual heatsink temperature. Maintain Tj below 125°C under all operational profiles, including frequent overloads.
III. Quantifiable Perspective on Scheme Advantages
Quantifiable Efficiency Gain: In a multi-axis 10kW-class servo drive, employing VBM1807 with its ultra-low Rds(on) for the motor inverter bridges can reduce total conduction losses by over 25% compared to standard 80V MOSFETs, directly increasing overall drive efficiency and reducing cooling requirements.
Quantifiable Space Savings & Reliability: Using a single VBQG2216 to manage two critical auxiliary functions saves >70% PCB area compared to a dual discrete SOT-23 solution and reduces solder joints, thereby improving the MTBF of the power management section.
System Performance Enhancement: The fast switching capability of the VBMB18R11SE enables higher PFC switching frequencies, allowing for smaller magnetic components and contributing to a more compact and responsive front-end design.
IV. Summary and Forward Look
This scheme constructs a robust, efficient, and intelligent power chain tailored for next-generation AI industrial servo drives, addressing high-voltage input conditioning, multi-axis power delivery, and system-level power management.
Input Conditioning Level – Focus on "High-Voltage Efficiency & Robustness": Leverage advanced SJ technology for high-efficiency, high-frequency operation at the grid interface.
Multi-Axis Drive Level – Focus on "Ultra-Low Loss & High Current": Deploy trench MOSFETs with minimal Rds(on) to maximize continuous and peak output capability while minimizing thermal footprint.
Power Management Level – Focus on "Miniaturization & Intelligence": Utilize highly integrated, small-footprint devices to enable sophisticated digital power control without sacrificing board space.
Future Evolution Directions:
Wide Bandgap Adoption: For ultra-high-speed spindle drives or maximizing power density, the PFC and/or inverter stages could migrate to Silicon Carbide (SiC) MOSFETs, enabling dramatically higher switching frequencies and reduced losses.
Fully Integrated Motor Drive Modules: The trend towards complete "Drives-on-Chip" or highly integrated IPMs (Intelligent Power Modules) that combine control, gate drive, protection, and power FETs will further simplify design and enhance reliability.
Engineers can adapt this framework based on specific servo drive parameters such as axis count, bus voltage, peak/continuous power per axis, and enclosure thermal constraints to realize high-performance, reliable, and compact motion control solutions.

Detailed Topology Diagrams

PFC & High-Voltage Inverter Bridge Topology Detail

graph LR subgraph "Three-Phase PFC Stage" A["Three-Phase 480VAC"] --> B["EMI Filter"] B --> C["Three-Phase Rectifier"] C --> D["PFC Inductor"] D --> E["PFC Switching Node"] E --> F["VBMB18R11SE
800V/11A"] F --> G["High-Voltage DC Bus"] H["PFC Controller"] --> I["Gate Driver"] I --> F G -->|Voltage Feedback| H end subgraph "Main Inverter Bridge Stage" G --> J["DC Link Capacitors"] J --> K["Inverter Bridge Leg"] K --> L["VBMB18R11SE
High-Side"] K --> M["VBMB18R11SE
Low-Side"] L --> N["Motor Output Phase U"] M --> O["Circuit Ground"] P["Inverter Controller"] --> Q["Gate Driver"] Q --> L Q --> M end subgraph "Protection Circuits" R["RCD Snubber"] --> F S["RC Absorption"] --> L T["TVS Protection"] --> I U["Current Sense"] --> H U --> P end style F fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style L fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Multi-Axis Drive & Intelligent Power Management Topology Detail

graph LR subgraph "Multi-Axis Servo Drive Inverter" A["48V/72V DC Bus"] --> B["Axis 1 Bridge Leg"] A --> C["Axis 2 Bridge Leg"] A --> D["Axis 3 Bridge Leg"] subgraph B["Axis 1: Three-Phase Inverter"] direction LR B1["VBM1807
High-Side U"] B2["VBM1807
Low-Side U"] B3["VBM1807
High-Side V"] B4["VBM1807
Low-Side V"] B5["VBM1807
High-Side W"] B6["VBM1807
Low-Side W"] end subgraph C["Axis 2: Three-Phase Inverter"] direction LR C1["VBM1807
High-Side U"] C2["VBM1807
Low-Side U"] C3["VBM1807
High-Side V"] C4["VBM1807
Low-Side V"] C5["VBM1807
High-Side W"] C6["VBM1807
Low-Side W"] end B1 --> E["Motor Phase U"] B2 --> F["Ground"] B3 --> G["Motor Phase V"] B4 --> F B5 --> H["Motor Phase W"] B6 --> F C1 --> I["Motor Phase U"] C2 --> J["Ground"] C3 --> K["Motor Phase V"] C4 --> J C5 --> L["Motor Phase W"] C6 --> J end subgraph "Intelligent Auxiliary Power Management" M["12V/24V Control Rail"] --> N["VBQG2216 Dual Switch"] subgraph N["VBQG2216 Configuration"] direction LR N_IN1["Gate1"] N_IN2["Gate2"] N_S1["Source1"] N_S2["Source2"] N_D1["Drain1"] N_D2["Drain2"] end N_D1 --> O["Brake Resistor Circuit"] N_D2 --> P["Cooling Fan"] N_S1 --> Q["System Ground"] N_S2 --> Q R["System Management IC"] --> N_IN1 R --> N_IN2 end subgraph "Field-Oriented Control (FOC) Loop" S["Main MCU/DSP"] --> T["FOC Algorithm"] T --> U["PWM Generation"] U --> V["Gate Drivers"] V --> B1 V --> B2 V --> C1 V --> C2 W["Current Sensors"] --> X["ADC Interface"] X --> S Y["Position Encoder"] --> Z["Encoder Interface"] Z --> S end style B1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style N fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Thermal Management & Protection Topology Detail

graph LR subgraph "Three-Level Thermal Management Architecture" A["Level 1: Liquid Cold Plate/Forced Air"] --> B["Multi-Axis Drive MOSFETs
VBM1807 Array"] C["Level 2: Air-Cooled Heat Sink"] --> D["High-Voltage MOSFETs
VBMB18R11SE Array"] E["Level 3: PCB Thermal Design"] --> F["Control ICs & VBQG2216"] subgraph "Temperature Monitoring Network" G["NTC on Heat Sink 1"] --> H["ADC Interface"] I["NTC on Heat Sink 2"] --> H J["NTC on PCB"] --> H K["Motor Temperature"] --> H end subgraph "Cooling Control" L["MCU Thermal Management"] --> M["Fan PWM Controller"] L --> N["Pump Speed Controller"] M --> O["Cooling Fans"] N --> P["Liquid Cooling Pump"] end H --> L end subgraph "Comprehensive Protection Network" Q["Overcurrent Protection"] --> R["Current Sense Amplifiers"] S["Overvoltage Protection"] --> T["Voltage Dividers & Comparators"] U["Overtemperature Protection"] --> V["Temperature Threshold Detectors"] W["Short-Circuit Protection"] --> X["Desaturation Detection"] subgraph "Fault Handling" Y["Fault Latch Circuit"] --> Z["Hardware Shutdown"] AA["Fault Signal"] --> AB["MCU Interrupt"] end R --> Y T --> Y V --> Y X --> Y Z --> D Z --> B AB --> L end subgraph "Gate Drive Protection" AC["Gate Driver ICs"] --> AD["TVS Diodes
Gate-Source Clamp"] AC --> AE["Series Gate Resistors"] AC --> AF["Miller Clamp Circuits"] end style B fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style D fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style F fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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