With the rapid development of the global new energy vehicle industry, high-end charging piles, as critical energy replenishment infrastructure, have increasingly stringent requirements for power density, conversion efficiency, operational stability, and intelligent management. Their core power module (including PFC, DC-DC conversion, and auxiliary power supply) serves as the "energy heart" of the entire system, demanding highly reliable and efficient power semiconductor devices for precise electrical energy conversion and control. The selection of MOSFETs and IGBTs directly determines the module's efficiency level, thermal performance, cost structure, and service life. Focusing on the core demands of high-end charging piles for efficiency, power density, and reliability, this article reconstructs the device selection logic based on application scenarios, providing an optimized, ready-to-implement solution.
I. Core Selection Principles and Scenario Adaptation Logic
Core Selection Principles
Voltage and Current Margin: For PFC stages (typically 400V DC bus) and DC-DC primary sides, device voltage ratings must withstand switching spikes and grid anomalies. A safety margin of ≥30-50% is recommended. Current ratings must meet peak and continuous power demands.
Ultra-Low Loss Pursuit: Prioritize devices with low conduction loss (Rds(on)/Vce(sat)) and excellent switching characteristics (low Qg/Esw) to maximize system efficiency, especially crucial for high-power, continuous operation.
Package and Thermal Performance: Select packages (TO247, TO220, TO263, SOT89, etc.) based on power level and thermal design requirements. Low thermal resistance is essential for effective heat dissipation.
High Reliability and Ruggedness: Devices must withstand harsh grid environments, frequent load switching, and potential surge events, ensuring long-term, maintenance-free operation.
Scenario Adaptation Logic
Based on the functional architecture of the charging pile power module, device applications are divided into three key scenarios: High-Voltage PFC / DC-DC Primary Side (High-Power Core), DC-DC Secondary Side / Synchronous Rectification (Medium-Voltage High-Current), and Auxiliary Power & Intelligent Control (Low-Voltage Functional Support). Device parameters are matched accordingly to optimize performance and cost.
II. MOSFET/IGBT Selection Solutions by Scenario
Scenario 1: PFC / DC-DC Primary Side (Several kW to Tens of kW) – High-Power Core Device
Recommended Model: VBP110MR24 (Single N-MOS, 1000V, 24A, TO247)
Key Parameter Advantages: High voltage rating of 1000V provides ample margin for 400V bus systems and handles voltage spikes robustly. Planar technology offers stable performance and good cost-effectiveness for high-voltage applications.
Scenario Adaptation Value: The TO247 package provides excellent thermal dissipation capability, crucial for managing losses in high-power stages. Its 1000V rating ensures reliability against grid surges, forming a solid foundation for the front-end of high-power modules. Suitable for traditional hard-switching or lower-frequency LLC topologies where utmost cost-performance is critical.
Scenario 2: DC-DC Secondary Side / Synchronous Rectification (High-Current Path) – Medium-Voltage High-Efficiency Device
Recommended Model: VBM18R20S (Single N-MOS, 800V, 20A, TO220)
Key Parameter Advantages: Utilizes advanced Super Junction (SJ) Multi-EPI technology, achieving a very low Rds(on) of 240mΩ @10V. The 800V rating is ideal for secondary-side synchronous rectification in high-output voltage DC-DC stages.
Scenario Adaptation Value: Ultra-low conduction loss minimizes heat generation in the high-current output path, directly boosting full-load efficiency. The TO220 package balances power handling and board space, suitable for multi-phase parallel designs to increase current capacity. Excellent for high-frequency synchronous rectification, improving overall power density.
Scenario 3: Auxiliary Power Supply & Smart Control Circuit – Low-Voltage Intelligent Switch
Recommended Model: VBI8322 (Single P-MOS, -30V, -6.1A, SOT89-6)
Key Parameter Advantages: Low Rds(on) (22mΩ @10V) for a P-channel device minimizes voltage drop in power paths. Compact SOT89-6 package saves valuable PCB space. Low gate threshold voltage (-1.7V) facilitates direct drive by control ICs.
Scenario Adaptation Value: Enables efficient, intelligent power management for auxiliary circuits (e.g., control board, communication module, cooling fan). The P-MOS configuration simplifies high-side switching design. Its small size and low loss are perfect for distributed point-of-load (PoL) switching within the control system, supporting advanced energy-saving modes and functional isolation.
III. System-Level Design Implementation Points
Drive Circuit Design
VBP110MR24 / VBM18R20S: Require dedicated gate driver ICs with adequate current sourcing/sinking capability. Careful PCB layout to minimize power loop and gate loop inductance is critical. Use negative voltage turn-off for IGBTs/MOSFETs in bridge configurations if needed for robustness.
VBI8322: Can often be driven directly by a microcontroller or logic output with a simple level shifter if needed. Include a gate resistor to control rise/fall times and damp ringing.
Thermal Management Design
Graded Strategy: VBP110MR24 and VBM18R20S require mounted heatsinks (isolated or non-isolated based on design). Thermal interface material quality is key. VBI8322 relies on PCB copper pour for heat dissipation; ensure sufficient copper area.
Derating: Operate devices at ≤70-80% of their rated current and voltage under maximum ambient temperature. Maintain junction temperature well below the maximum rating (e.g., Tj < 125°C) for long lifespan.
EMC and Reliability Assurance
Snubber & Filtering: Use RC snubbers across primary switching devices (VBP110MR24) to damp voltage overshoot. Implement input/output EMI filters according to standards.
Protection: Integrate comprehensive protection (over-current, over-voltage, over-temperature) at the system controller level. Utilize TVS diodes on gate pins and bus voltages for surge/ESD protection. Ensure proper creepage and clearance distances for high-voltage nodes.
IV. Core Value of the Solution and Optimization Suggestions
The semiconductor selection solution for high-end charging pile modules proposed herein, based on scenario-driven logic, achieves comprehensive coverage from high-power AC-DC conversion to efficient DC-DC transformation, and down to intelligent auxiliary power management. Its core value is manifested in three key aspects:
1. Maximized System Efficiency Across the Power Chain: By matching optimized devices to each conversion stage—the robust VBP110MR24 for input, the ultra-efficient VBM18R20S for secondary-side rectification, and the low-loss VBI8322 for auxiliary control—conduction and switching losses are minimized throughout. This hierarchical optimization contributes directly to achieving peak system efficiency (>96% for high-end modules), reducing energy waste and thermal stress.
2. Optimal Balance of Power Density, Reliability, and Cost: The selected devices represent the best trade-off for their respective roles. Using a cost-effective 1000V planar MOSFET (VBP110MR24) for the primary side, a higher-performance SJ MOSFET (VBM18R20S) for the efficiency-critical secondary side, and a highly integrated P-MOS (VBI8322) for control, achieves an optimal system-level BOM cost without compromising key performance or reliability metrics required for 24/7 operation.
3. Enhanced System Intelligence and Manageability: The use of a compact, low-loss P-MOS like the VBI8322 facilitates sophisticated power domain control within the auxiliary system. This enables features like standby power reduction, independent module enable/disable for maintenance, and graceful shutdown sequences, paving the way for smarter, more manageable charging infrastructure.
In the design of high-end charging pile power modules, the selection of power semiconductors is a decisive factor in achieving high efficiency, high power density, and unwavering reliability. This scenario-based selection solution, by precisely matching device characteristics to specific functional demands and combining it with rigorous system-level design practices, provides a actionable and optimized technical roadmap for module developers. As charging technology advances towards ultra-fast charging, bidirectional power flow (V2X), and higher integration, future device selection will increasingly focus on wide-bandgap solutions (SiC, GaN) for the highest power stages and further intelligent integration. The foundational principles of scenario adaptation and system-level optimization outlined here will remain essential for developing the next generation of superior, market-leading high-end charging pile power modules.

Detailed Topology Diagrams