Energy Management

Your present location > Home page > Energy Management
MOSFET & IGBT Selection Strategy and Device Adaptation Handbook for High-Power, High-Reliability Energy Storage Systems in Thermal Power Flexibility Retrofits
ESS Power Semiconductor Topology Diagrams

ESS Power Conversion System Overall Topology Diagram

graph LR %% Grid Interface Section subgraph "Grid Interface & PCS" AC_GRID["Grid Connection
AC 400V/50Hz"] --> AC_FILTER["Grid Filter & Protection"] AC_FILTER --> PCS_IN["PCS AC Input"] subgraph "Three-Level T-Type/NPC Inverter" PCS_IN --> T_TYPE_INV["T-Type/NPC Inverter"] subgraph "Main Power Switches" Q_T1["VBPB165I80
600V/80A IGBT"] Q_T2["VBPB165I80
600V/80A IGBT"] Q_T3["VBP18R20SFD
800V/20A MOSFET"] Q_T4["VBP18R20SFD
800V/20A MOSFET"] end T_TYPE_INV --> Q_T1 T_TYPE_INV --> Q_T2 T_TYPE_INV --> Q_T3 T_TYPE_INV --> Q_T4 end Q_T1 --> DC_BUS["High-Voltage DC Bus
600-1000VDC"] Q_T2 --> DC_BUS Q_T3 --> DC_BUS Q_T4 --> DC_BUS end %% DC-DC Conversion Section subgraph "Bidirectional DC-DC Converter" DC_BUS --> BIDI_DCDC["Bidirectional DC-DC Converter"] subgraph "Synchronous Rectification Bridge" Q_SR1["VBGQA3303G
30V/75A Half-Bridge"] Q_SR2["VBGQA3303G
30V/75A Half-Bridge"] end BIDI_DCDC --> Q_SR1 BIDI_DCDC --> Q_SR2 Q_SR1 --> BATTERY_INTERFACE["Battery Interface"] Q_SR2 --> BATTERY_INTERFACE BATTERY_INTERFACE --> BATTERY_STACK["Battery Energy Storage
48V-400V Pack"] end %% Auxiliary & Protection Section subgraph "Auxiliary Power & Protection" AUX_POWER["Auxiliary Power Supply"] --> CONTROL_UNIT["Control Unit MCU"] subgraph "Pre-charge & Protection Circuits" PRE_CHARGE["Pre-charge Circuit"] --> Q_PRECHG["VBE2315
P-MOS -30V/-60A"] CONTACTOR_DRV["Contactor Driver"] --> Q_CONTACTOR["VBE2315
P-MOS -30V/-60A"] PROTECTION["Protection Switches"] --> Q_PROTECT["VBE2315
P-MOS -30V/-60A"] end CONTROL_UNIT --> PRE_CHARGE CONTROL_UNIT --> CONTACTOR_DRV CONTROL_UNIT --> PROTECTION Q_PRECHG --> BATTERY_STACK Q_CONTACTOR --> BATTERY_STACK Q_PROTECT --> BATTERY_STACK end %% Driving & Control Section subgraph "Driving & Monitoring" subgraph "Gate Drivers" GATE_DRV_IGBT["Isolated IGBT Driver
≥2A-5A Peak"] --> Q_T1 GATE_DRV_IGBT --> Q_T2 GATE_DRV_MOS["High-Voltage MOSFET Driver"] --> Q_T3 GATE_DRV_MOS --> Q_T4 GATE_DRV_SR["Half-Bridge Driver
≥2A Sink/Source"] --> Q_SR1 GATE_DRV_SR --> Q_SR2 end subgraph "Monitoring & Protection" CURRENT_SENSE["Current Sensors"] --> CONTROL_UNIT VOLTAGE_SENSE["Voltage Sensors"] --> CONTROL_UNIT TEMP_SENSE["Temperature Sensors"] --> CONTROL_UNIT DESAT_DETECT["Desaturation Detection"] --> GATE_DRV_IGBT OVERCURRENT["Overcurrent Protection"] --> CONTROL_UNIT end CONTROL_UNIT --> GATE_DRV_IGBT CONTROL_UNIT --> GATE_DRV_MOS CONTROL_UNIT --> GATE_DRV_SR end %% Thermal Management subgraph "Hierarchical Thermal Management" COOLING_LEVEL1["Level 1: Liquid/Forced Air
PCS Main Switches"] --> Q_T1 COOLING_LEVEL1 --> Q_T2 COOLING_LEVEL2["Level 2: PCB Heatsink
DC-DC Synchronous Switches"] --> Q_SR1 COOLING_LEVEL2 --> Q_SR2 COOLING_LEVEL3["Level 3: Natural Convection
Auxiliary Switches"] --> Q_PRECHG COOLING_LEVEL3 --> Q_CONTACTOR end %% Communication & Control CONTROL_UNIT --> GRID_COMM["Grid Communication
IEC 61850"] CONTROL_UNIT --> BMS_COMM["BMS Communication
CAN/Modbus"] CONTROL_UNIT --> CLOUD_MONITOR["Cloud Monitoring Interface"] %% Style Definitions style Q_T1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_T3 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_SR1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_PRECHG fill:#fce4ec,stroke:#e91e63,stroke-width:2px

With the global transition towards renewable energy integration, thermal power plants are undergoing flexibility retrofits, where large-scale energy storage systems (ESS) serve as critical buffers for grid stability and peak shaving. The power conversion systems (PCS), battery management systems (BMS), and DC/DC converters, acting as the "heart and arteries" of the ESS, require robust, efficient, and reliable power semiconductor devices. The selection of MOSFETs and IGBTs directly determines system conversion efficiency, power density, thermal management capability, and long-term operational stability. Addressing the stringent demands of ESS for high voltage, high current, continuous cycling, and harsh industrial environments, this article develops a practical and optimized device selection strategy based on scenario-specific adaptation.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Multi-Dimensional Co-optimization
Device selection requires coordinated adaptation across key dimensions—voltage rating, conduction/switching losses, package thermal performance, and ruggedness—ensuring precise matching with high-power, high-voltage ESS operating conditions:
High Voltage & Sufficient Margin: For ESS DC links (typically 600V-1000V), prioritize devices with rated voltages (VDS/VCE) exceeding the maximum DC bus voltage by ≥50-100% to withstand switching spikes, grid transients, and fault conditions. For a 600V DC bus, devices rated ≥800V-1200V are recommended.
Ultra-Low Loss for High Efficiency: Prioritize devices with extremely low Rds(on) or VCE(sat) to minimize conduction loss, and favorable switching characteristics (low Qg, Eon/off) to reduce switching loss at high frequencies. This is crucial for 24/7 cycling operation, maximizing round-trip efficiency and minimizing cooling requirements.
Package for High Power Dissipation: Choose packages with excellent thermal impedance (RthJC) and power handling capability (e.g., TO-247, TO-3P) for main power paths (PCS, DC/DC). Use compact packages (TO-251, TO-252, DFN) for auxiliary circuits, balancing power density and thermal design.
Industrial-Grade Reliability & Ruggedness: Meet requirements for long lifespan, wide temperature operation (-40°C to 150°C), and high robustness against avalanche energy, short-circuit events, and voltage surges, adapting to demanding power plant environments.
(B) Scenario Adaptation Logic: Categorization by System Function
Divide the ESS power stage into three core scenarios: First, the High-Voltage DC/AC Inverter (PCS Core), requiring high-voltage, high-current switching devices. Second, the Bidirectional DC/DC Converter (Battery Interface), requiring devices with ultra-low loss for high-frequency operation. Third, Auxiliary & Protection Circuits, requiring compact, cost-effective devices for system control and protection.
II. Detailed Device Selection Scheme by Scenario
(A) Scenario 1: High-Voltage DC/AC Inverter (PCS) – Main Power Switch
Three-level T-Type or NPC inverters in PCS handle high voltage (600-1000V DC) and large phase currents, demanding high-efficiency, robust devices.
Recommended Model 1 (High Voltage IGBT): VBPB165I80 (IGBT+FRD, 600/650V, 80A, TO-3P)
Parameter Advantages: FS (Field Stop) IGBT technology offers low VCE(sat) of 1.7V (typ. @15V), ensuring low conduction loss. Integrated Fast Recovery Diode (FRD) simplifies design. TO-3P package provides superior thermal performance for high power dissipation. High current rating (80A) suits medium-to-high power PCS segments.
Adaptation Value: Ideal for the main switches in T-Type neutral point clamped legs or as the main switch in two-level inverters. High current capability and low saturation voltage improve inverter efficiency, crucial for meeting stringent grid codes (>98% efficiency targets). Integrated FRD enhances system reliability.
Recommended Model 2 (High Voltage MOSFET for High-Frequency Legs): VBP18R20SFD (N-MOS, 800V, 20A, TO-247)
Parameter Advantages: Super-Junction Multi-EPI technology achieves a balanced Rds(on) of 205mΩ at 800V rating. High voltage margin (800V) for 400-500VAC systems. TO-247 package ensures good heat dissipation.
Adaptation Value: Suitable for the high-frequency switching positions in hybrid or optimized topologies, or as a robust switch for auxiliary circuits within the PCS. Its high VDS provides excellent surge immunity in harsh grid conditions.
Selection Notes: Verify system DC link voltage, max phase current, and switching frequency. IGBTs (VBPB165I80) are preferred for lower switching frequencies (<20kHz) where conduction loss dominates. Super-Junction MOSFETs (VBP18R20SFD) can be considered for higher frequency legs or snubber circuits. Ensure sufficient gate drive capability.
(B) Scenario 2: Bidirectional DC/DC Converter (Battery Interface) – High-Current, Low-Voltage Switch
Isolated or non-isolated DC/DC converters interface the high-voltage DC bus with battery stacks (e.g., 48V, 400V), requiring synchronous rectification with ultra-low loss.
Recommended Model: VBGQA3303G (Half-Bridge N+N, 30V, 75A per FET, DFN8(5x6)-C)
Parameter Advantages: SGT technology achieves an exceptionally low Rds(on) of 2.7mΩ at 10V per MOSFET. High continuous current of 75A per channel. DFN8 package offers very low thermal resistance and parasitic inductance, critical for high-frequency, high-current operation.
Adaptation Value: Perfect as the synchronous rectifier pair in LLC or phase-shifted full-bridge converters on the low-voltage (battery) side. Ultra-low Rds(on) drastically reduces conduction loss, directly boosting converter efficiency (target >97%). The half-bridge configuration saves PCB area and simplifies layout.
Selection Notes: Calculate RMS current on the LV side based on battery power. Ensure the package has adequate copper pour (≥300mm² per FET) and thermal vias for heat dissipation. Pair with a dedicated high-frequency gate driver IC.
(C) Scenario 3: Auxiliary Power, Pre-charge & Protection Circuits – Support & Safety Device
These circuits manage system startup, auxiliary power supplies, contactor control, and provide protection, requiring reliable and compact devices.
Recommended Model: VBE2315 (P-MOS, -30V, -60A, TO-252)
Parameter Advantages: Trench technology provides very low Rds(on) of 10mΩ at 10V. High current rating (-60A) in a compact TO-252 package. Low gate threshold (Vth = -2.5V) facilitates easy drive.
Adaptation Value: Excellent for high-side pre-charge control or main contactor driver circuits on the battery side. Its low Rds(on) minimizes voltage drop and power loss during pre-charge or when feeding auxiliary loads. Can also be used in DC/DC converter input protection switches.
Selection Notes: For pre-charge circuits, size the device based on the inrush current limiting resistor's power. Use a simple NPN/PNP level shifter or a dedicated high-side driver for the P-MOS gate. Add TVS for voltage clamping.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBPB165I80 / VBP18R20SFD: Use reinforced isolated gate drivers (e.g., based on SiO₂ or transformer isolation) with peak current capability ≥2A-5A. Implement negative gate bias or Miller clamp for robust turn-off. Keep gate loops extremely short.
VBGQA3303G: Pair with a high-performance half-bridge driver (e.g., IRS21867) with sufficient sink/source current (≥2A). Optimize layout to minimize power loop and gate loop inductance.
VBE2315: Can be driven by an MCU via a simple bipolar transistor stage. Include a gate pull-up resistor for safe default-off state.
(B) Thermal Management Design: Hierarchical Approach
VBPB165I80 / VBP18R20SFD / VBP18R20SFD: Mount on a substantial heatsink using thermal interface material. Consider forced air or liquid cooling for high-power racks. Monitor junction temperature via NTC or using driver IC's fault features.
VBGQA3303G: Requires a dedicated, well-designed PCB as a heatsink. Use a thick copper layer (≥2oz), large exposed copper areas (≥300mm² per FET), and multiple thermal vias to inner layers or a bottom-side heatsink.
VBE2315: A standard PCB copper pad (≥100mm²) is usually sufficient for its intended auxiliary roles.
(C) EMC and Reliability Assurance
EMC Suppression:
VBPB165I80 / VBP18R20SFD: Use snubber circuits (RC/RCD) across switches or bus. Implement carefully laid out DC-link capacitors with low ESL. Use ferrite cores on busbars or cables.
VBGQA3303G: Use small gate resistors to control dv/dt. Place high-frequency decoupling capacitors (MLCC) very close to device pins.
Reliability Protection:
Derating: Operate devices at ≤70-80% of rated voltage and current under worst-case temperature.
Overcurrent/Short-Circuit Protection: Use desaturation detection for IGBTs (VBPB165I80), or source-side current sensing with fast comparators for MOSFETs.
Surge/ESD Protection: Apply MOVs at AC input, TVS diodes at DC bus and sensitive control ports. Use gate series resistors and TVS for gate protection.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
High-Efficiency Energy Conversion: The combination of low-loss IGBTs, Super-Junction MOSFETs, and SGT MOSFETs enables system efficiency >98%, minimizing energy waste during frequent charge/discharge cycles.
High Power Density & Reliability: The use of advanced packages (DFN8, TO-3P) and robust technologies (FS IGBT, SGT) allows for compact, reliable designs suited for space-constrained retrofits and 24/7 operation.
System Cost Optimization: A targeted selection covering high-power, medium-power, and auxiliary needs provides an optimal performance-to-cost ratio for large-scale ESS deployment.
(B) Optimization Suggestions
Power Scaling: For higher power PCS (>250kW per module), consider paralleling VBPB165I80 or using higher current IGBT modules. For higher voltage systems (1000V+), consider 1200V SiC MOSFETs for the highest efficiency.
Integration Upgrade: For the DC/DC stage, consider using power modules that integrate the VBGQA3303G half-bridge with drivers and protection.
Specialized Scenarios: For extremely high ambient temperatures, prioritize devices with higher Tjmax (175°C) or enhanced thermal packages. For applications requiring extreme ruggedness, select parts with characterized avalanche energy ratings.
Conclusion
The strategic selection of MOSFETs and IGBTs is pivotal to achieving high efficiency, high reliability, and cost-effectiveness in thermal power plant energy storage systems. This scenario-based scheme, leveraging high-voltage IGBTs, ultra-low-loss SGT MOSFETs, and robust auxiliary devices, provides comprehensive technical guidance for ESS power stage design. Future exploration into wide-bandgap (SiC, GaN) devices will further push the boundaries of efficiency and power density, solidifying the role of energy storage in the flexible and stable grid of the future.

Detailed Topology Diagrams

PCS Three-Level Inverter Topology Detail

graph LR subgraph "Three-Level T-Type Inverter Phase Leg" DC_POS["DC+ (600-1000V)"] --> Q1["VBPB165I80
600V/80A IGBT"] DC_MID["DC Midpoint"] --> Q2["VBPB165I80
600V/80A IGBT"] DC_MID --> Q3["VBP18R20SFD
800V/20A MOSFET"] DC_NEG["DC- (GND)"] --> Q4["VBP18R20SFD
800V/20A MOSFET"] Q1 --> OUTPUT_NODE["Phase Output"] Q2 --> OUTPUT_NODE Q3 --> OUTPUT_NODE Q4 --> OUTPUT_NODE OUTPUT_NODE --> AC_FILTER["LC Output Filter"] AC_FILTER --> GRID_TIE["Grid Connection Point"] end subgraph "Driving & Protection Circuitry" GATE_DRIVER["Isolated Gate Driver"] --> Q1_GATE["Q1 Gate"] GATE_DRIVER --> Q2_GATE["Q2 Gate"] GATE_DRIVER --> Q3_GATE["Q3 Gate"] GATE_DRIVER --> Q4_GATE["Q4 Gate"] subgraph "Protection Networks" DESAT_CIRCUIT["Desaturation Detection"] --> Q1 DESAT_CIRCUIT --> Q2 SNUBBER_RCD["RCD Snubber"] --> Q1 SNUBBER_RCD --> Q2 SNUBBER_RC["RC Snubber"] --> Q3 SNUBBER_RC --> Q4 end CONTROL_SIGNAL["PWM Controller"] --> GATE_DRIVER end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q3 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Bidirectional DC-DC Converter Topology Detail

graph LR subgraph "Isolated LLC/Phase-Shifted Full Bridge" HV_BUS["HV DC Bus (600V)"] --> PRIMARY_SWITCHES["Primary Side Switches"] PRIMARY_SWITCHES --> TRANSFORMER["High-Frequency Transformer"] TRANSFORMER --> SYNCH_RECT["Synchronous Rectification"] subgraph "Synchronous Rectification Bridge" SR_HIGH["High-Side Switch"] --> Q_SR_H["VBGQA3303G
30V/75A MOSFET"] SR_LOW["Low-Side Switch"] --> Q_SR_L["VBGQA3303G
30V/75A MOSFET"] end SYNCH_RECT --> SR_HIGH SYNCH_RECT --> SR_LOW Q_SR_H --> OUTPUT_FILTER["LC Output Filter"] Q_SR_L --> OUTPUT_FILTER OUTPUT_FILTER --> BATTERY_PORT["Battery Port (48-400V)"] end subgraph "Control & Driving" DCDC_CONTROLLER["Bidirectional Controller"] --> PRIMARY_DRIVER["Primary Side Driver"] DCDC_CONTROLLER --> SR_DRIVER["Synchronous Rectification Driver"] SR_DRIVER --> Q_SR_H SR_DRIVER --> Q_SR_L subgraph "Current Sensing & Protection" CURRENT_SENSE_H["High-Side Current Sense"] --> DCDC_CONTROLLER CURRENT_SENSE_L["Low-Side Current Sense"] --> DCDC_CONTROLLER OVERCURRENT_COMP["Overcurrent Comparator"] --> PROTECTION_LOGIC["Protection Logic"] end PROTECTION_LOGIC --> SR_DRIVER end subgraph "Thermal Management" PCB_HEATSINK["PCB Copper Heatsink
≥2oz, 300mm² per FET"] --> Q_SR_H PCB_HEATSINK --> Q_SR_L THERMAL_VIAS["Multiple Thermal Vias"] --> PCB_HEATSINK end style Q_SR_H fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_SR_L fill:#fff3e0,stroke:#ff9800,stroke-width:2px

Auxiliary Power & Protection Topology Detail

graph LR subgraph "Pre-charge Control Circuit" BATTERY_POS["Battery Positive"] --> PRE_CHARGE_RES["Inrush Current Limiting Resistor"] PRE_CHARGE_RES --> PRE_CHARGE_SW["Pre-charge Switch"] PRE_CHARGE_SW --> Q_PRECHG["VBE2315
P-MOS -30V/-60A"] Q_PRECHG --> DC_BUS_CHARGE["DC Bus Capacitors"] CONTROL_MCU["MCU GPIO"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> Q_PRECHG_GATE["Gate Drive"] Q_PRECHG_GATE --> Q_PRECHG end subgraph "Contactor Control Circuit" CONTROL_MCU --> CONTACTOR_DRIVE["Contactor Drive Circuit"] CONTACTOR_DRIVE --> Q_CONTACTOR["VBE2315
P-MOS -30V/-60A"] Q_CONTACTOR --> CONTACTOR_COIL["Main Contactor Coil"] CONTACTOR_COIL --> GND PULLUP_RES["Gate Pull-up Resistor"] --> Q_CONTACTOR end subgraph "Protection & Auxiliary Switches" subgraph "Protection Switches Array" Q_PROT1["VBE2315
Auxiliary Load 1"] Q_PROT2["VBE2315
Auxiliary Load 2"] Q_PROT3["VBE2315
Protection Switch"] end CONTROL_MCU --> PROTECTION_DRIVER["Protection Driver"] PROTECTION_DRIVER --> Q_PROT1 PROTECTION_DRIVER --> Q_PROT2 PROTECTION_DRIVER --> Q_PROT3 Q_PROT1 --> LOAD1["Cooling Fan"] Q_PROT2 --> LOAD2["Communication Module"] Q_PROT3 --> SAFETY_CIRCUIT["Safety Interlock"] end subgraph "Voltage Protection" TVS_ARRAY["TVS Protection Array"] --> SENSITIVE_PORTS["Control Ports"] MOV_ARRAY["MOV Surge Protection"] --> AC_INPUT["AC Input Ports"] GATE_PROTECTION["Gate Resistor + TVS"] --> Q_PRECHG_GATE GATE_PROTECTION --> Q_CONTACTOR end style Q_PRECHG fill:#fce4ec,stroke:#e91e63,stroke-width:2px style Q_CONTACTOR fill:#fce4ec,stroke:#e91e63,stroke-width:2px style Q_PROT1 fill:#fce4ec,stroke:#e91e63,stroke-width:2px
Download PDF document
Download now:VBP18R20SFD

Sample Req

Online

Telephone

400-655-8788

WeChat

Topping

Sample Req
Online
Telephone
WeChat