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Power MOSFET Selection Analysis for High-Power EV Charging Pile Modules – A Case Study on Efficiency, Power Density, and Robustness
High-Power EV Charging Pile Power Module Topology Diagram

High-Power EV Charging Pile Power Module Overall Topology

graph TD %% Input and PFC Stage subgraph "Three-Phase Input & PFC Stage" AC_IN["Three-Phase 400VAC Input"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> RECTIFIER["Three-Phase Rectifier"] RECTIFIER --> PFC_INDUCTOR["PFC Boost Inductor"] PFC_INDUCTOR --> PFC_NODE["PFC Switching Node"] subgraph "PFC MOSFET Array" Q_PFC1["VBM185R07
850V/7A
TO-220"] Q_PFC2["VBM185R07
850V/7A
TO-220"] Q_PFC3["VBM185R07
850V/7A
TO-220"] end PFC_NODE --> Q_PFC1 PFC_NODE --> Q_PFC2 PFC_NODE --> Q_PFC3 Q_PFC1 --> HV_BUS["High-Voltage DC Bus
650-750VDC"] Q_PFC2 --> HV_BUS Q_PFC3 --> HV_BUS HV_BUS --> PFC_CONTROLLER["PFC Controller"] PFC_CONTROLLER --> GATE_DRIVER_PFC["PFC Gate Driver"] GATE_DRIVER_PFC --> Q_PFC1 GATE_DRIVER_PFC --> Q_PFC2 GATE_DRIVER_PFC --> Q_PFC3 end %% Isolated DC-DC Primary Side subgraph "Isolated DC-DC Converter Primary" HV_BUS --> RESONANT_TANK["LLC Resonant Tank"] RESONANT_TANK --> TRANSFORMER_PRI["High-Frequency Transformer
Primary"] TRANSFORMER_PRI --> LLC_NODE["LLC Switching Node"] subgraph "Primary Side MOSFET Array" Q_LLC1["VBM16R15SFD
600V/15A
SJ_Multi-EPI"] Q_LLC2["VBM16R15SFD
600V/15A
SJ_Multi-EPI"] Q_LLC3["VBM16R15SFD
600V/15A
SJ_Multi-EPI"] end LLC_NODE --> Q_LLC1 LLC_NODE --> Q_LLC2 LLC_NODE --> Q_LLC3 Q_LLC1 --> GND_PRIMARY Q_LLC2 --> GND_PRIMARY Q_LLC3 --> GND_PRIMARY LLC_CONTROLLER["LLC Controller"] --> GATE_DRIVER_LLC["LLC Gate Driver"] GATE_DRIVER_LLC --> Q_LLC1 GATE_DRIVER_LLC --> Q_LLC2 GATE_DRIVER_LLC --> Q_LLC3 end %% Secondary Side and Output Stage subgraph "Secondary Synchronous Rectification & Output" TRANSFORMER_SEC["Transformer Secondary"] --> SR_NODE["Synchronous Rectification Node"] subgraph "High-Current Synchronous Rectification Array" Q_SR1["VBGL1602
60V/190A
SGT Technology"] Q_SR2["VBGL1602
60V/190A
SGT Technology"] Q_SR3["VBGL1602
60V/190A
SGT Technology"] Q_SR4["VBGL1602
60V/190A
SGT Technology"] end SR_NODE --> Q_SR1 SR_NODE --> Q_SR2 SR_NODE --> Q_SR3 SR_NODE --> Q_SR4 Q_SR1 --> OUTPUT_FILTER["Output LC Filter"] Q_SR2 --> OUTPUT_FILTER Q_SR3 --> OUTPUT_FILTER Q_SR4 --> OUTPUT_FILTER OUTPUT_FILTER --> DC_OUT["DC Output
200-500VDC"] DC_OUT --> BATTERY["EV Battery Load"] SR_CONTROLLER["Synchronous Rectification Controller"] --> GATE_DRIVER_SR["High-Current Gate Driver"] GATE_DRIVER_SR --> Q_SR1 GATE_DRIVER_SR --> Q_SR2 GATE_DRIVER_SR --> Q_SR3 GATE_DRIVER_SR --> Q_SR4 end %% Control and Monitoring System subgraph "Digital Control & Monitoring" MAIN_MCU["Main Control MCU/DSP"] --> PFC_CONTROLLER MAIN_MCU --> LLC_CONTROLLER MAIN_MCU --> SR_CONTROLLER subgraph "System Monitoring" VOLTAGE_SENSE["High-Voltage Sensing"] CURRENT_SENSE["Precision Current Sensing"] TEMP_SENSE["Temperature Sensors"] end VOLTAGE_SENSE --> MAIN_MCU CURRENT_SENSE --> MAIN_MCU TEMP_SENSE --> MAIN_MCU MAIN_MCU --> COMMUNICATION["CAN/Cloud Communication"] MAIN_MCU --> DISPLAY["HMI Display"] end %% Protection and Thermal Management subgraph "Protection & Thermal Management" subgraph "Electrical Protection" RCD_SNUBBER["RCD Snubber Circuit"] RC_SNUBBER["RC Absorption Circuit"] TVS_PROTECTION["TVS Protection Array"] DESAT_PROTECTION["Desaturation Detection"] end RCD_SNUBBER --> Q_PFC1 RC_SNUBBER --> Q_LLC1 TVS_PROTECTION --> GATE_DRIVER_PFC TVS_PROTECTION --> GATE_DRIVER_LLC TVS_PROTECTION --> GATE_DRIVER_SR DESAT_PROTECTION --> Q_PFC1 DESAT_PROTECTION --> Q_LLC1 subgraph "Three-Level Thermal Management" COOLING_LEVEL1["Level 1: Liquid Cold Plate"] --> Q_SR1 COOLING_LEVEL1 --> Q_SR2 COOLING_LEVEL2["Level 2: Forced Air Cooling"] --> Q_PFC1 COOLING_LEVEL2 --> Q_LLC1 COOLING_LEVEL3["Level 3: Natural Convection"] --> PFC_CONTROLLER COOLING_LEVEL3 --> LLC_CONTROLLER end end %% Styling Definitions style Q_PFC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LLC1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style MAIN_MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

The evolution of electric vehicle fast-charging infrastructure demands charging pile modules that deliver exceptional efficiency, high power density, and unwavering reliability. The core of these modules—encompassing the Power Factor Correction (PFC) stage, the isolated DC-DC converter, and the final output stage—relies critically on the optimal selection of power semiconductor devices. The choice of MOSFETs and IGBTs directly dictates system performance, thermal management complexity, and long-term operational stability. This analysis targets the rigorous application scenario of DC fast-charging modules, providing an in-depth device selection rationale for key power nodes and presenting a complete, optimized recommendation scheme.
Detailed Device Selection Analysis
1. VBM185R07 (N-MOS, 850V, 7A, TO-220, Planar)
Role: Main switch for single or interleaved Boost PFC stage, or as the primary-side switch in an isolated DC-DC converter.
Technical Deep Dive:
Voltage Ruggedness & Safety Margin: With a rectified DC bus voltage from a 400VAC three-phase line exceeding 650V, and accounting for line transients and switching voltage spikes, the 850V rating provides a vital safety buffer. Its planar technology offers stable, avalanche-rated performance, ensuring robust operation in the face of grid disturbances commonly encountered at charging stations.
Efficiency & Current Handling: The 1700mΩ Rds(on) (at 10V) and 7A continuous current rating make it suitable for medium-power modules or as a unit in a multi-phase interleaved PFC architecture. The TO-220 package facilitates straightforward mounting on a common heatsink, enabling scalable power design through paralleling while maintaining manageable thermal resistance for effective cooling.
2. VBM16R15SFD (N-MOS, 600V, 15A, TO-220, SJ_Multi-EPI)
Role: Primary-side switch in high-efficiency, high-frequency LLC or phase-shifted full-bridge DC-DC converter stages.
Extended Application Analysis:
Ultra-Low Loss Conversion Core: Utilizing advanced Super Junction (SJ_Multi-EPI) technology, this device achieves an exceptionally low Rds(on) of 240mΩ at 10V. This drastically reduces conduction losses in the primary-side topology, which is critical for achieving peak system efficiency targets (>96%).
High-Frequency Capability & Power Density: The low gate charge characteristic of SJ MOSFETs, combined with the low Rds(on), enables efficient operation at elevated switching frequencies (tens to hundreds of kHz). This allows for significant reduction in the size of the isolation transformer and resonant components, directly contributing to higher power density of the charging module.
Robustness for Hard & Soft-Switching: The 600V rating is optimally suited for bus voltages derived from 400VAC input. Its technology provides excellent body diode characteristics and switching robustness, making it reliable in both hard-switching and soft-switching resonant converter applications common in isolated charger designs.
3. VBGL1602 (N-MOS, 60V, 190A, TO-263, SGT)
Role: Synchronous rectifier or primary switching element in the low-voltage, high-current secondary-side DC-DC stage.
Precision Power & Thermal Management:
Ultimate Efficiency for High-Current Path: The final energy delivery to the EV battery is characterized by very high currents at modest voltages. The VBGL1602, with its revolutionary Shielded Gate Trench (SGT) technology, delivers an ultra-low Rds(on) of 2.1mΩ at 10V and a massive 190A current rating. This minimizes conduction losses to an absolute minimum, which is the single largest factor in secondary-side efficiency.
Power Density & Thermal Challenge Mastery: The TO-263 (D2PAK) package offers an excellent balance of current-handling capability and thermal performance in a compact footprint. It is designed for direct mounting onto a liquid-cooled cold plate or an intensive forced-air heatsink, enabling the management of hundreds of amperes within a highly constrained module volume.
Dynamic Performance for High Frequency: Its extremely low gate charge allows for very fast switching, essential for synchronous rectification control. This high-speed switching capability further aids in reducing the size of output filter components, pushing the boundaries of power density.
System-Level Design and Application Recommendations
Drive Circuit Design Key Points:
High-Voltage Switches (VBM185R07 / VBM16R15SFD): Require dedicated gate drivers with adequate current capability. For the primary-side switches, attention must be paid to managing Miller plateau effects; using a negative turn-off voltage or an active Miller clamp circuit is recommended to enhance noise immunity and prevent spurious turn-on.
High-Current Switch Drive (VBGL1602): Demands a gate driver with very high peak current output (several amps) to rapidly charge and discharge its significant gate capacitance, minimizing switching losses. The layout must absolutely minimize power loop and gate loop parasitic inductances to ensure clean switching and prevent destructive voltage spikes.
Thermal Management and EMC Design:
Tiered Thermal Strategy: VBM185R07 and VBM16R15SFD should be mounted on a common aluminum heatsink with forced air cooling. The VBGL1602 must be interfaced directly to a high-performance cold plate via thermal interface material, as its losses, though low in resistance, are concentrated due to the immense current.
EMI Suppression: Employ RC snubbers across the drain-source of the primary switches (VBM185R07/VBM16R15SFD) to damp high-frequency ringing. Utilize low-ESL ceramic capacitors in parallel with the VBGL1602 at its terminals to provide a local high-frequency current path. Implement a laminated busbar structure for the high-current secondary-side loop to minimize parasitic inductance and reduce radiated EMI.
Reliability Enhancement Measures:
Adequate Derating: Operate the 850V MOSFET at no more than 70-75% of its rated voltage under worst-case conditions. Monitor the case temperature of the VBGL1602 rigorously, ensuring a sufficient margin to its maximum junction temperature even during peak load or cooling system stress.
Enhanced Protection: Integrate TVS diodes at the gate pins of all devices for ESD and voltage surge protection. Implement desaturation detection for the primary-side switches and precise, fast overcurrent protection using shunt resistors or isolated current sensors on the secondary side to achieve millisecond-level fault response.
Conclusion
In the design of next-generation, high-power EV charging pile modules, the strategic selection of power switching devices is paramount. This three-tier device scheme—comprising the high-voltage front-end switch (VBM185R07), the ultra-efficient primary-side SJ MOSFET (VBM16R15SFD), and the revolutionary high-current SGT MOSFET (VBGL1602)—embodies a holistic approach to achieving system-level excellence.
Core value is reflected in:
Full-Stack Efficiency Optimization: From high-rugge PFC conversion and low-loss primary-side switching to the minimal-conduction-resistance secondary-side path, this selection constructs a complete, highly efficient energy transfer chain from grid input to battery terminal.
Maximized Power Density: The combination of high-frequency capability (SJ MOSFET) and ultra-compact, high-current handling (SGT MOSFET) enables dramatic reductions in magnetic and filter component sizes, allowing for more compact and powerful charger modules.
Robustness for Demanding Environments: The selected devices offer appropriate voltage margins, advanced technologies for lower losses (and thus lower thermal stress), and packages suited for aggressive cooling, ensuring long-term reliability in outdoor, 24/7 operating conditions.
Future-Oriented Scalability: This modular selection philosophy allows for power scaling through device paralleling and supports the industry's trajectory towards higher output currents and voltages. As charging power levels move beyond 350kW, the principles demonstrated here—leveraging SJ technology for high-voltage switching and SGT technology for ultra-low resistance—will remain foundational, paving the way for the eventual adoption of even higher-performance wide-bandgap semiconductors.

Detailed Topology Diagrams

PFC Stage Topology Detail

graph LR subgraph "Three-Phase Interleaved PFC" A[Three-Phase 400VAC] --> B[EMI Filter] B --> C[Three-Phase Rectifier] C --> D[PFC Inductor Bank] D --> E[PFC Switching Node] subgraph "Interleaved MOSFET Array" M1["VBM185R07
850V/7A
TO-220"] M2["VBM185R07
850V/7A
TO-220"] M3["VBM185R07
850V/7A
TO-220"] end E --> M1 E --> M2 E --> M3 M1 --> F[High-Voltage DC Bus] M2 --> F M3 --> F G[PFC Controller] --> H[Gate Driver] H --> M1 H --> M2 H --> M3 F -->|Voltage Feedback| G end subgraph "Drive & Protection" I[12V Supply] --> J[Gate Driver IC] K["Negative Turn-off
or Active Miller Clamp"] --> H L["RC Snubber
Circuit"] --> M1 M["TVS Protection"] --> H N[Current Sense] --> O[Protection Logic] O --> G end style M1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

DC-DC Conversion Stage Detail

graph LR subgraph "Primary Side LLC Converter" A[650-750VDC Bus] --> B[LLC Resonant Tank] B --> C[Transformer Primary] C --> D[LLC Switching Node] subgraph "Primary MOSFET Array" Q1["VBM16R15SFD
600V/15A
SJ_Multi-EPI"] Q2["VBM16R15SFD
600V/15A
SJ_Multi-EPI"] end D --> Q1 D --> Q2 Q1 --> E[Primary Ground] Q2 --> E F[LLC Controller] --> G[Primary Gate Driver] G --> Q1 G --> Q2 end subgraph "Secondary Synchronous Rectification" H[Transformer Secondary] --> I[SR Switching Node] subgraph "Synchronous Rectifier Array" SR1["VBGL1602
60V/190A
SGT Technology"] SR2["VBGL1602
60V/190A
SGT Technology"] SR3["VBGL1602
60V/190A
SGT Technology"] end I --> SR1 I --> SR2 I --> SR3 SR1 --> J[Output Filter] SR2 --> J SR3 --> J J --> K[200-500VDC Output] L[SR Controller] --> M[High-Current Gate Driver] M --> SR1 M --> SR2 M --> SR3 end subgraph "High-Current Layout Design" N["Low-ESL Ceramic
Capacitors"] --> SR1 O["Laminated Busbar
Structure"] --> SR1 O --> SR2 O --> SR3 P["Local Gate Drive
Power Supply"] --> M end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Thermal Management & Protection Detail

graph LR subgraph "Three-Level Thermal Architecture" A["Level 1: Liquid Cooling"] --> B["VBGL1602 SGT MOSFETs
Direct Cold Plate Mounting"] C["Level 2: Forced Air"] --> D["VBM185R07 & VBM16R15SFD
Common Heatsink"] E["Level 3: Natural Cooling"] --> F["Control ICs & Gate Drivers"] G[Temperature Sensors] --> H[MCU] H --> I[Fan PWM Control] H --> J[Pump Speed Control] I --> K[High-Speed Fans] J --> L[Cooling Pump] end subgraph "Protection Network" M["Overvoltage Protection
TVS Array"] --> N["Gate Driver ICs"] O["Overcurrent Protection
Shunt/Current Sensor"] --> P["Fast Comparator"] Q["Desaturation Detection"] --> R["Primary MOSFETs"] S["Thermal Protection"] --> T["Shutdown Logic"] P --> T Q --> T T --> U["System Shutdown"] end subgraph "Reliability Enhancement" V["Voltage Derating
70-75% of Rating"] --> W["VBM185R07 850V MOSFET"] X["Thermal Margin
Monitoring"] --> Y["VBGL1602 Junction Temp"] Z["EMI Suppression
RC Snubbers"] --> AA["Primary Switches"] end style B fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style D fill:#e8f5e8,stroke:#4caf50,stroke-width:2px
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