With the growing demand for portable and renewable energy solutions, solar power banks have become essential for outdoor and emergency power needs. The power management system, serving as the "brain and heart" of the unit, provides critical functions such as solar input management, battery charge/discharge control, and multi-port output regulation. The selection of power MOSFETs directly determines system conversion efficiency, thermal performance, power density, and reliability. Addressing the stringent requirements of solar power banks for high efficiency, compact size, robust operation, and safety, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and reliability—ensuring precise matching with system operating conditions:
Sufficient Voltage Margin: For solar input voltages (up to ~24V open circuit) and battery buses (12V/5V), reserve a rated voltage withstand margin of ≥50% to handle solar spikes and inductive transients. For example, prioritize devices with ≥30V for a 5V/12V battery bus.
Prioritize Low Loss: Prioritize devices with low Rds(on) (reducing conduction loss in high-current paths) and low Qg (enabling fast, efficient switching), adapting to intermittent solar charging and continuous discharge cycles, maximizing energy harvest and battery runtime.
Package & Integration Matching: Choose compact, thermally efficient packages (DFN, SOT89) for high-current paths to save space and manage heat. Prioritize integrated configurations (e.g., Dual MOSFETs) for load switching to minimize PCB area and simplify design.
Reliability for Harsh Conditions: Meet demands for outdoor use, focusing on robust ESD rating, stable thresholds over temperature, and reliable operation across a wide temperature range.
(B) Scenario Adaptation Logic: Categorization by Function
Divide the system into three core power management scenarios: First, Solar Input & Battery Management (power conversion core), requiring devices with high voltage capability and efficient switching for MPPT/charging circuits. Second, Battery Discharge Path (high-current core), requiring very low Rds(on) to minimize loss during high-current output. Third, Multi-Port Output Switching & Protection (user interface & safety), requiring compact, integrated solutions for safe load switching and fault isolation. This enables precise parameter-to-need matching.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: Solar Input Management & Battery Charging Control – Power Conversion Device
Solar charge controllers (e.g., for 18-22Vmp panels) and battery charging circuits need to handle input voltage spikes and require efficient switching for MPPT or PWM operation.
Recommended Model: VBQF1695 (N-MOS, 60V, 6A, DFN8(3x3))
Parameter Advantages: 60V drain-source voltage provides ample margin for 12V/24V nominal solar inputs. DFN8(3x3) package offers excellent thermal performance for its size. Moderate Rds(on) (75mΩ @10V) and current rating (6A) are suitable for typical charging currents of 3A-5A.
Adaptation Value: Its high VDS rating safely accommodates open-circuit voltage from small solar panels. The low thermal resistance of the DFN package manages heat in compact enclosures. Balances cost and performance for mainstream solar charging ICs.
Selection Notes: Verify maximum solar panel Voc and maximum charging current. Ensure gate drive voltage (VGS) from controller is sufficient (≥4.5V preferred). Provide adequate copper pour for heat dissipation.
(B) Scenario 2: Battery Discharge Path & High-Current Output Switching – High-Efficiency Device
The path from the battery to the output boost converter or direct 5V output must have minimal resistance to maximize available energy, especially during high-current draws (e.g., 2A-3A output).
Recommended Model: VBQG7313 (N-MOS, 30V, 12A, DFN6(2x2))
Parameter Advantages: Very low Rds(on) (20mΩ @10V) is critical for minimizing conduction loss in the discharge path. High continuous current rating (12A) provides significant margin for surge currents. The ultra-compact DFN6(2x2) package saves valuable board space.
Adaptation Value: Dramatically improves overall discharge efficiency. For a 3A discharge current, conduction loss is only ~0.18W, prolonging battery life. The small footprint is ideal for space-constrained power bank designs.
Selection Notes: Must be used on the low-side of the battery (ground path) or with a dedicated driver if used on the high-side. Ensure PCB layout provides a low-inductance, high-current path to minimize voltage spikes.
(C) Scenario 3: Multi-Port Output Switching & Protection – Integrated Interface Device
Modern power banks feature multiple outputs (USB-A, USB-C) requiring individual on/off control, load detection, and short-circuit protection.
Recommended Model: VBI5325 (Dual N+P MOSFET, ±30V, ±8A, SOT89-6)
Parameter Advantages: Single SOT89-6 package integrates a complementary pair (N and P-channel), saving over 60% board area vs. two discrete devices. 30V rating is robust for 5V/9V/12V output ports. Good Rds(on) (18mΩ N-ch @10V / 32mΩ P-ch @10V) minimizes port voltage drop.
Adaptation Value: Enables sophisticated port control schemes. The P-channel can be used for high-side switching of VBUS, while the N-channel can control ground switching for load detection or full isolation. Facilitates safe hot-plug and automatic load switching.
Selection Notes: Ideal for use with dedicated USB port controller ICs. The integrated configuration simplifies gate driving logic. Ensure proper heatsinking for simultaneous high-current operation on both channels.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBQF1695: Typically driven by a solar charge controller IC. Ensure the controller's gate drive capability matches the Qg of the MOSFET. A small gate resistor (e.g., 10Ω) may be needed to damp ringing.
VBQG7313: Often driven by the enable pin of a boost converter IC or a dedicated load switch IC. Verify the drive voltage is sufficient to fully enhance the MOSFET (use 5V drive where possible). A pull-down resistor on the gate is recommended.
VBI5325: Requires careful gate drive sequencing if used for complementary switching. Use logic gates or a dedicated dual-MOSFET driver IC to ensure break-before-make action and prevent shoot-through.
(B) Thermal Management Design: Tiered Heat Dissipation
VBQG7313 (High-Current Path): Prioritize heat dissipation. Use maximum possible copper pour connected to the drain pins (thermal pad). 1oz copper minimum, 2oz preferred. Thermal vias to inner layers or a bottom-side ground plane can significantly help.
VBQF1695 (Solar Input): Provide a moderate copper area (≥150mm²) for heat dissipation, especially if operating in a high ambient temperature environment.
VBI5325 (Output Switching): Local copper pour under the SOT89-6 package (≥50mm²) is usually sufficient for typical USB port currents (<3A).
Overall: In sealed power bank enclosures, consider the thermal path to the outer casing. Avoid placing high-loss components directly next to the battery.
(C) EMC and Reliability Assurance
EMC Suppression:
VBQF1695: Add a small RC snubber or a TVS diode at the solar input terminals to clamp voltage spikes from long cable runs.
VBQG7313: Ensure input/output capacitors of the boost converter are placed close to the MOSFET to minimize high-frequency switching loop area.
Use ferrite beads on output lines to suppress high-frequency noise.
Reliability Protection:
Derating Design: Derate current ratings by at least 30% for operation above 50°C ambient.
Output Short-Circuit Protection: The VBI5325 can be part of a current-limiting circuit. Use a current-sense amplifier or a dedicated load switch IC with built-in protection to quickly disable the port in a fault.
ESD Protection: Add ESD protection diodes (e.g., USBLC6-4SC6) on all external USB data and power lines.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
End-to-End Efficiency Maximization: Optimized MOSFET selection from solar input to output port minimizes losses at every stage, extending usable battery capacity by 5-10%.
Compact & Feature-Rich Design: The use of DFN packages and integrated dual MOSFETs frees up space for additional features like wireless charging or a larger battery.
Robust Field Performance: Selected devices offer voltage margins and package reliability suitable for the variable conditions of outdoor use.
(B) Optimization Suggestions
For Higher Power (>30W) / USB-PD Applications: For the discharge path, consider VBGQF1408 (40V, 40A, Rds(on)=7.7mΩ) to handle higher currents with even lower loss.
For Ultra-Low Quiescent Current Designs: In the solar input path, consider a MOSFET with a lower gate threshold (Vth) like VBQG8218 (P-MOS, Vth=-0.8V) for more efficient driving from low-power management ICs.
For Space-Absolute-Minimum Designs: For output switching where only P-channel high-side switching is needed, VBQG2317 (P-MOS, -30V, -10A, DFN6) offers an extremely small footprint with high current capability.
Conclusion
Power MOSFET selection is central to achieving high efficiency, compact size, and reliable operation in solar power bank power management systems. This scenario-based scheme, utilizing VBQF1695 for solar input, VBQG7313 for the critical battery discharge path, and VBI5325 for intelligent output management, provides comprehensive technical guidance for R&D through precise function matching and system-level design. Future exploration can focus on even lower Rds(on) devices in advanced packages and integrated power stage modules, pushing the boundaries of power density and efficiency for next-generation portable energy solutions.

Detailed Topology Diagrams