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Optimization of Power Chain for Cold Chain Logistics Charging Piles: A Precise MOSFET Selection Scheme Based on Bidirectional Charging, Main Output Stage, and Auxiliary Power Management
Cold Chain Logistics Charging Pile Power Chain Optimization Topology

Cold Chain Logistics Charging Pile - Overall Power Chain Topology

graph TD %% Grid Interface & Bidirectional Conversion subgraph "Grid Interface & Bidirectional Power Stage" GRID["Grid Connection
AC Input"] --> FILTER["EMI/RFI Filter"] FILTER --> BIDI_BRIDGE["Three-Phase Bridge"] BIDI_BRIDGE --> PFC_INDUCTOR["PFC Boost Inductor"] subgraph "Bidirectional High-Voltage MOSFETs" HV_SW1["VBMB165R26S
650V/26A
SJ_Multi-EPI"] HV_SW2["VBMB165R26S
650V/26A
SJ_Multi-EPI"] HV_SW3["VBMB165R26S
650V/26A
SJ_Multi-EPI"] HV_SW4["VBMB165R26S
650V/26A
SJ_Multi-EPI"] end PFC_INDUCTOR --> HV_SW1 HV_SW1 --> DC_BUS["High-Voltage DC Bus
400-800VDC"] DC_BUS --> HV_SW2 HV_SW2 --> GND1 DC_BUS --> HV_SW3 HV_SW3 --> TRANSFORMER["Isolation Transformer"] TRANSFORMER --> HV_SW4 HV_SW4 --> GND2 end %% Main DC Output Stage subgraph "Main DC Output Stage & Synchronous Rectification" TRANSFORMER_SEC["Transformer Secondary"] --> SR_NODE["Synchronous Rectification Node"] subgraph "High-Current Synchronous Rectifiers" SR1["VBMB1105
100V/120A
Rds(on)=3.7mΩ"] SR2["VBMB1105
100V/120A
Rds(on)=3.7mΩ"] SR3["VBMB1105
100V/120A
Rds(on)=3.7mΩ"] SR4["VBMB1105
100V/120A
Rds(on)=3.7mΩ"] end SR_NODE --> SR1 SR_NODE --> SR2 SR_NODE --> SR3 SR_NODE --> SR4 SR1 --> OUTPUT_FILTER["Output LC Filter"] SR2 --> OUTPUT_FILTER SR3 --> OUTPUT_FILTER SR4 --> OUTPUT_FILTER OUTPUT_FILTER --> DC_OUTPUT["Main DC Output
200-500V/Up to 30kW"] DC_OUTPUT --> VEHICLE_BATTERY["Vehicle Battery Load"] end %% Auxiliary Power Management System subgraph "Intelligent Auxiliary Power Management" AUX_SUPPLY["Auxiliary Power Supply
12V/5V/3.3V"] --> MCU["Main Control MCU/DSP"] subgraph "Dual-Channel Intelligent Switches" SWITCH1["VBQF3638
Dual 60V/25A
DFN8(3x3)-B"] SWITCH2["VBQF3638
Dual 60V/25A
DFN8(3x3)-B"] SWITCH3["VBQF3638
Dual 60V/25A
DFN8(3x3)-B"] end MCU --> SWITCH1 MCU --> SWITCH2 MCU --> SWITCH3 SWITCH1 --> FAN_CONTROL["Cooling Fan Control"] SWITCH1 --> PUMP_CONTROL["Liquid Pump Control"] SWITCH2 --> COMM_MODULE["Communication Module"] SWITCH2 --> DISPLAY_HMI["Display & HMI"] SWITCH3 --> REFRIGERATION_UNIT["Refrigeration Unit Power"] SWITCH3 --> SAFETY_SYSTEM["Safety Monitoring System"] end %% Thermal Management Hierarchy subgraph "Three-Level Thermal Management Architecture" LEVEL1["Level 1: Forced Air Cooling"] --> HEATSINK1["Primary Heatsink
VBMB1105 MOSFETs"] LEVEL2["Level 2: Aided Convection"] --> HEATSINK2["Secondary Heatsink
VBMB165R26S MOSFETs"] LEVEL3["Level 3: PCB Thermal Design"] --> PCB_COOLING["Thermal Vias & Planes
VBQF3638 & Control ICs"] TEMP_SENSORS["Temperature Sensors"] --> THERMAL_MCU["Thermal Management Controller"] THERMAL_MCU --> FAN_SPEED["Fan PWM Control"] THERMAL_MCU --> PUMP_SPEED["Pump Speed Control"] FAN_SPEED --> LEVEL1 PUMP_SPEED --> LEVEL1 end %% Protection & Communication subgraph "Protection & System Communication" PROTECTION_SUB["Protection Circuits"] --> SNUBBERS["RCD/RC Snubbers"] SNUBBERS --> HV_SW1 SNUBBERS --> HV_SW3 CURRENT_SENSE["High-Precision Current Sensing"] --> PROTECTION_IC["Protection IC"] VOLTAGE_SENSE["Voltage Monitoring"] --> PROTECTION_IC PROTECTION_IC --> FAULT_LATCH["Fault Latch & Shutdown"] FAULT_LATCH --> HV_SW1 FAULT_LATCH --> SR1 MCU --> CAN_BUS["CAN Communication"] CAN_BUS --> VEHICLE_CAN["Vehicle CAN Network"] MCU --> CLOUD_COMM["Cloud Connectivity"] CLOUD_COMM --> REMOTE_MONITOR["Remote Monitoring System"] end %% Style Definitions style HV_SW1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SWITCH1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Preface: Building the "Energy Gateway" for Refrigerated Transportation – Discussing the Systems Thinking Behind Power Device Selection
In the critical infrastructure of cold chain logistics, charging piles are not merely energy replenishment points but vital hubs ensuring the continuity of the temperature-controlled supply chain. An outstanding charging pile system must achieve efficient, reliable, and intelligent power conversion and management under demanding conditions including wide temperature ranges, high humidity, frequent start-stop cycles, and potential grid fluctuations. Its core performance—fast charging capability, high energy efficiency, stable auxiliary power supply for refrigeration units, and robust operational lifespan—is fundamentally determined by the optimal selection and application of power semiconductor devices at key nodes.
This article adopts a holistic, system-level design approach to address the core challenges within the power path of cold chain logistics charging piles: how to select the optimal combination of power MOSFETs for the three critical functions—bidirectional AC-DC/DC-DC conversion, main DC output stage, and multi-channel auxiliary power management—under the stringent constraints of high power density, high reliability, harsh environmental adaptability, and lifecycle cost control.
Within the design of a cold chain charging pile, the power conversion and distribution module is the core determinant of charging speed, efficiency, thermal performance, and overall reliability. Based on comprehensive considerations of bidirectional energy flow for vehicle-to-grid (V2G) potential, high-current output capability, system intelligence, and thermal management, this article selects three key devices from the component library to construct a hierarchical, complementary power solution.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The High-Voltage Bridge: VBMB165R26S (650V, 26A, Rds(on)=115mΩ, TO-220F) – PFC / Bidirectional Isolated DC-DC Primary Side Switch
Core Positioning & Topology Deep Dive: Ideally suited for the critical high-voltage switching stage in charging pile topologies, such as the boost converter in an Active Power Factor Correction (PFC) circuit or the primary-side switches in an isolated bidirectional DC-DC converter (e.g., LLC, PSFB). Its 650V Super Junction (SJ_Multi-EPI) technology provides a high withstand voltage margin for universal input voltage ranges (85-265VAC) and 400VDC bus applications, ensuring robustness against line surges and switching voltage spikes.
Key Technical Parameter Analysis:
Super Junction Advantage: The SJ_Multi-EPI technology offers an excellent trade-off between low specific on-resistance and low gate charge (Qg), leading to lower overall conduction and switching losses compared to standard planar MOSFETs at this voltage rating. This is crucial for achieving high efficiency at elevated switching frequencies (e.g., 50kHz-100kHz).
Package & Thermal Performance: The TO-220F (fully isolated) package facilitates easy mounting on a heatsink, improving thermal management for a device that handles significant power in the front-end conversion stage.
Selection Trade-off: Compared to higher Rds(on) standard 600V+ MOSFETs or more expensive SiC alternatives, the VBMB165R26S presents a balanced, cost-effective solution for high-efficiency, high-frequency operation in the critical power factor correction and isolation stage of medium-to-high power charging piles.
2. The High-Current Output Workhorse: VBMB1105 (100V, 120A, Rds(on)=3.7mΩ, TO-220F) – Main DC Output Stage / Low-Voltage Side Synchronous Rectifier
Core Positioning & System Benefit: As the core switch in the final DC output stage (e.g., in a non-isolated buck converter for precise voltage/current control) or as the synchronous rectifier (SR) on the secondary side of an isolated DC-DC converter. Its exceptionally low Rds(on) of 3.7mΩ is the key to minimizing conduction losses in the high-current path, directly impacting:
Maximum Charging Efficiency & Power Density: Drastically reduces I²R losses during constant current (CC) charging phases, enabling higher efficiency and allowing for a more compact, cooler-running design.
Enhanced Thermal Headroom & Reliability: The ultra-low Rds(on) combined with the thermal performance of the TO-220F package provides significant headroom for handling high continuous and pulsed currents, ensuring stable operation under peak load conditions when simultaneously charging the vehicle battery and supporting auxiliary loads.
Drive Design Key Points: Although Rds(on) is extremely low, its total gate charge (Qg) needs evaluation to ensure the gate driver can provide sufficient current for fast switching, minimizing transition losses especially in synchronous rectification or high-frequency PWM applications.
3. The Intelligent Power Distributor: VBQF3638 (Dual 60V, 25A, Rds(on)=28mΩ @10V, DFN8(3x3)-B) – Multi-Channel Auxiliary & Control Power Management Switch
Core Positioning & System Integration Advantage: The dual N-Channel MOSFETs in a compact DFN8 package are ideal for intelligent, high-side or low-side switching of multiple auxiliary power rails within the charging pile. These rails power control boards, communication modules, fans, pumps, and critically, may provide standby or support power to the refrigeration unit of the connected refrigerated truck.
Application Example: Enables sequential power-up/power-down of internal subsystems, provides soft-start for capacitive loads, and allows for intelligent load shedding or prioritization based on thermal conditions or available power.
PCB Design Value: The ultra-compact DFN8(3x3)-B dual-MOSFET integration maximizes control board space utilization, simplifies routing for parallel or independent switch configurations, and enhances the power density and reliability of the auxiliary power management unit.
Reason for Dual N-Channel Selection: When used with a suitable gate driver IC (e.g., a bootstrap circuit for high-side control), N-Channel MOSFETs offer superior performance (lower Rds(on) for a given die size) compared to P-Channel devices. This configuration is perfect for space-constrained, high-reliability designs requiring efficient switching of multiple medium-current rails.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Loop Synergy
Front-End & Control Coordination: The switching of VBMB165R26S in the PFC/bidirectional stage must be tightly synchronized with its dedicated controller. Feedback signals (current, voltage) are crucial for the charging pile's main control unit to implement advanced charging protocols and grid interaction algorithms.
Precision Control of Output Stage: As the final actuator for charging curve control (CC/CV), the switching performance and paralleling capability of VBMB1105 are vital for output current ripple and regulation accuracy. Low-inductance layout and matched, potentially isolated, gate drivers are essential.
Digital Power Management: The gates of VBQF3638 are controlled via GPIO or PWM signals from the management MCU, enabling features like programmable current limiting, fault reporting (using the MOSFET's intrinsic body diode for sense FET configurations possible), and fast shutdown for overload protection.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Air Cooling): VBMB1105 on the main output stage is a primary heat generator. It must be mounted on a substantial heatsink, often with forced air cooling from internal fans, given the high continuous current during charging.
Secondary Heat Source (Aided Convection/Heatsink): VBMB165R26S in the front-end stage generates significant switching and conduction loss. It requires a dedicated heatsink, with thermal design considering the airflow path within the sealed charging pile enclosure.
Tertiary Heat Source (PCB Conduction): VBQF3638 and its associated driver circuitry typically dissipate lower power. Thermal vias under the DFN8 package connected to internal ground/power planes and the external chassis are key for effective heat spreading.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBMB165R26S: Snubber circuits (RC or RCD) across the MOSFET or the transformer primary are essential to clamp voltage spikes caused by leakage inductance, especially in hard-switching topologies.
VBMB1105: Careful PCB layout to minimize parasitic inductance in the high-current loop is critical to reduce voltage overshoot during switching. Schottky diodes in parallel with the SR MOSFETs can be considered for added safety.
Enhanced Gate Protection: All gate drive loops should be short and include optimized series resistors. TVS diodes or Zener clamps (appropriate to VGS rating) between gate and source protect against transients. Strong pull-downs ensure definite turn-off.
Derating Practice:
Voltage Derating: The maximum VDS for VBMB165R26S should not exceed 80% of 650V (520V) under worst-case transients. For VBMB1105, ensure VDS margin above the maximum output voltage (e.g., 60V for a 48V system).
Current & Thermal Derating: Base continuous current ratings on realistic junction temperature rises, using thermal impedance curves. For pulsed currents (during load steps), ensure operation within the Safe Operating Area (SOA). The high current capability of VBMB1105 must be derated based on actual heatsink temperature.
III. Quantifiable Perspective on Scheme Advantages and Competitor Comparison
Quantifiable Efficiency Gain: In a 30kW output stage, using VBMB1105 (3.7mΩ) versus a standard 100V MOSFET with 8mΩ can reduce conduction losses by over 50% at full load, directly increasing efficiency by >0.5% and reducing cooling requirements.
Quantifiable Space & Reliability Improvement: Using one VBQF3638 to control two independent 24V/10A auxiliary rails saves >70% PCB area compared to two discrete SO-8 MOSFETs and reduces component count, directly improving the MTBF of the management board.
Lifecycle Cost Optimization: The selection of robust, application-optimized devices like the Super Junction VBMB165R26S and the high-current VBMB1105, combined with proper derating and protection, minimizes field failures and maintenance downtime in harsh outdoor environments, lowering the total cost of ownership.
IV. Summary and Forward Look
This scheme presents a comprehensive, optimized power chain for cold chain logistics charging piles, addressing high-voltage AC-DC conversion, high-current DC output, and intelligent auxiliary power distribution. Its essence is "right-sizing for the application":
Energy Conversion Level – Focus on "Robust Efficiency": Utilize Super Junction technology for high-voltage switching, balancing performance, cost, and reliability.
Power Output Level – Focus on "Ultra-Low Loss": Deploy extreme low-Rds(on) MOSFETs in the high-current path to maximize efficiency and power density.
Power Management Level – Focus on "Compact Intelligence": Employ highly integrated, multi-channel switches in miniature packages to enable complex power sequencing and management in minimal space.
Future Evolution Directions:
Wide Bandgap Adoption: For next-generation ultra-fast charging piles, the PFC/isolated DC-DC stage could migrate to GaN HEMTs or SiC MOSFETs for even higher frequency and efficiency, dramatically reducing passive component size.
Fully Integrated Smart Switches: For auxiliary power management, consider solutions integrating the MOSFET, driver, protection, and diagnostic feedback into a single package (e.g., intelligent power switches), further simplifying design and enhancing system monitoring capabilities.
Engineers can refine this framework based on specific charging pile specifications such as output power level (e.g., 20kW/60kW/120kW), target protocols (CCS, ChaoJi, etc.), auxiliary load requirements, and the specific environmental class (temperature, humidity, corrosion) for deployment.

Detailed Topology Diagrams

Bidirectional PFC & Isolation Stage Topology Detail

graph LR subgraph "Three-Phase Bidirectional PFC Stage" AC_IN["AC Grid Input"] --> EMI_FILTER["EMI Filter"] EMI_FILTER --> RECTIFIER["Three-Phase Bridge"] RECTIFIER --> BOOST_INDUCTOR["PFC Boost Inductor"] subgraph "Super Junction MOSFET Array" Q1["VBMB165R26S
650V/26A/115mΩ"] Q2["VBMB165R26S
650V/26A/115mΩ"] Q3["VBMB165R26S
650V/26A/115mΩ"] Q4["VBMB165R26S
650V/26A/115mΩ"] end BOOST_INDUCTOR --> Q1 Q1 --> HV_BUS["High-Voltage DC Bus"] HV_BUS --> Q2 Q2 --> GND_PRI["Primary Ground"] PFC_CONTROLLER["PFC/Bidirectional Controller"] --> GATE_DRIVER["Gate Driver"] GATE_DRIVER --> Q1 GATE_DRIVER --> Q2 end subgraph "Isolated Bidirectional DC-DC Stage" HV_BUS --> RESONANT_TANK["LLC Resonant Tank"] RESONANT_TANK --> ISO_TRANS["Isolation Transformer"] ISO_TRANS --> Q3 Q3 --> SW_NODE["Switching Node"] SW_NODE --> Q4 Q4 --> GND_PRI LLC_CONTROLLER["LLC Controller"] --> ISO_DRIVER["Isolated Gate Driver"] ISO_DRIVER --> Q3 ISO_DRIVER --> Q4 ISO_TRANS --> SEC_OUTPUT["Secondary Output"] end subgraph "Protection & Control" SNUBBER_CIRCUIT["RCD Snubber Circuit"] --> Q1 SNUBBER_CIRCUIT --> Q3 CURRENT_FEEDBACK["Current Feedback"] --> PFC_CONTROLLER VOLTAGE_FEEDBACK["Voltage Feedback"] --> LLC_CONTROLLER end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Main Output Stage & Synchronous Rectification Detail

graph LR subgraph "Synchronous Rectification Bridge" TRANS_SEC["Transformer Secondary Winding"] --> SR_NODE["Common SR Node"] subgraph "Parallel High-Current MOSFETs" SR_TOP1["VBMB1105
100V/120A/3.7mΩ"] SR_TOP2["VBMB1105
100V/120A/3.7mΩ"] SR_BOT1["VBMB1105
100V/120A/3.7mΩ"] SR_BOT2["VBMB1105
100V/120A/3.7mΩ"] end SR_NODE --> SR_TOP1 SR_NODE --> SR_TOP2 SR_TOP1 --> OUTPUT_INDUCTOR["Output Filter Inductor"] SR_TOP2 --> OUTPUT_INDUCTOR OUTPUT_INDUCTOR --> OUTPUT_CAP["Output Capacitor Bank"] OUTPUT_CAP --> DC_OUT["DC Output Terminal"] SR_BOT1 --> GND_OUT["Output Ground"] SR_BOT2 --> GND_OUT end subgraph "Current Control & Protection" SENSE_RESISTOR["High-Precision Sense Resistor"] --> CURRENT_AMP["Current Sense Amplifier"] CURRENT_AMP --> CONTROLLER["Output Stage Controller"] CONTROLLER --> GATE_DRIVER_SR["Synchronous Rectification Driver"] GATE_DRIVER_SR --> SR_TOP1 GATE_DRIVER_SR --> SR_TOP2 GATE_DRIVER_SR --> SR_BOT1 GATE_DRIVER_SR --> SR_BOT2 VOLTAGE_SENSE_OUT["Output Voltage Sense"] --> CONTROLLER TEMP_SENSE_SR["MOSFET Temperature Sense"] --> CONTROLLER end subgraph "Layout & Thermal Considerations" PARASITIC_MIN["Minimized Parasitic Inductance
Layout"] --> SR_TOP1 HEATSINK_ASSEMBLY["Forced Air Heatsink Assembly"] --> SR_TOP1 HEATSINK_ASSEMBLY --> SR_TOP2 CURRENT_BALANCING["Active Current Balancing"] --> SR_TOP1 CURRENT_BALANCING --> SR_TOP2 end style SR_TOP1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Auxiliary Power Management & Thermal System Detail

graph LR subgraph "Intelligent Load Switching Channels" MCU_GPIO["MCU GPIO/PWM"] --> LEVEL_SHIFTER["Level Shifter Circuit"] subgraph "Dual-Channel MOSFET Switch Array" SW_CH1["VBQF3638 Channel 1
60V/25A/28mΩ"] SW_CH2["VBQF3638 Channel 2
60V/25A/28mΩ"] SW_CH3["VBQF3638 Channel 1
60V/25A/28mΩ"] SW_CH4["VBQF3638 Channel 2
60V/25A/28mΩ"] SW_CH5["VBQF3638 Channel 1
60V/25A/28mΩ"] SW_CH6["VBQF3638 Channel 2
60V/25A/28mΩ"] end LEVEL_SHIFTER --> SW_CH1 LEVEL_SHIFTER --> SW_CH2 LEVEL_SHIFTER --> SW_CH3 LEVEL_SHIFTER --> SW_CH4 LEVEL_SHIFTER --> SW_CH5 LEVEL_SHIFTER --> SW_CH6 AUX_12V["12V Auxiliary Rail"] --> SW_CH1 AUX_12V --> SW_CH2 AUX_12V --> SW_CH3 AUX_12V --> SW_CH4 AUX_12V --> SW_CH5 AUX_12V --> SW_CH6 SW_CH1 --> LOAD1["Cooling Fan Load"] SW_CH2 --> LOAD2["Liquid Pump Load"] SW_CH3 --> LOAD3["Communication Module"] SW_CH4 --> LOAD4["Display & HMI"] SW_CH5 --> LOAD5["Refrigeration Unit"] SW_CH6 --> LOAD6["Safety System"] LOAD1 --> SYSTEM_GND LOAD2 --> SYSTEM_GND LOAD3 --> SYSTEM_GND LOAD4 --> SYSTEM_GND LOAD5 --> SYSTEM_GND LOAD6 --> SYSTEM_GND end subgraph "Thermal Management System" TEMP_SENSOR1["MOSFET Temp Sensor"] --> THERMAL_CTRL["Thermal Controller"] TEMP_SENSOR2["Heatsink Temp Sensor"] --> THERMAL_CTRL TEMP_SENSOR3["Ambient Temp Sensor"] --> THERMAL_CTRL THERMAL_CTRL --> PWM_FAN["Fan PWM Control"] THERMAL_CTRL --> PWM_PUMP["Pump Speed Control"] THERMAL_CTRL --> LOAD_SHED["Intelligent Load Shedding"] PWM_FAN --> FAN_DRIVER["Fan Driver Circuit"] PWM_PUMP --> PUMP_DRIVER["Pump Driver Circuit"] LOAD_SHED --> MCU_GPIO end subgraph "PCB Thermal Design" DFN_PACKAGE["DFN8(3x3)-B Package"] --> THERMAL_VIAS["Thermal Vias Array"] THERMAL_VIAS --> GROUND_PLANE["Internal Ground Plane"] GROUND_PLANE --> CHASSIS["Chassis Connection"] POWER_PLANE["Power Plane Spreading"] --> DFN_PACKAGE end style SW_CH1 fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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