With the explosive growth of AI computing and the large-scale deployment of data centers, AI industrial power supplies have become the critical infrastructure ensuring the stable and efficient operation of servers, GPUs, and accelerators. The power conversion and delivery systems, serving as the "energy heart" of the entire unit, provide high-current, high-fidelity power to critical loads like compute cards, memory, and high-speed interfaces. The selection of power semiconductors (MOSFETs, IGBTs) directly determines system efficiency, transient response, power density, and operational reliability. Addressing the stringent requirements of AI power supplies for peak efficiency, high power density, and 24/7 stability, this article focuses on scenario-based adaptation to develop a practical and optimized device selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Multi-Dimensional Collaborative Optimization
Device selection requires coordinated optimization across key dimensions—voltage class, conduction/switching losses, package thermal performance, and ruggedness—ensuring precise matching with high-frequency switching and high-current demands of AI power topologies (e.g., PFC, LLC, multi-phase VRM):
Adequate Voltage & Safe Operating Area (SOA): For AC-DC stages (e.g., PFC, 400V/800V bus), prioritize sufficient voltage margin (≥30-50%) and robust avalanche/SCPT capability. For high-current DC-DC stages (e.g., 48V-12V/1.xV), focus on low Rds(on) and optimized gate charge (Qg) to minimize losses.
Ultra-Low Loss Priority: Prioritize devices with minimal total power loss (conduction + switching). For primary-side switches, low Qg and Coss are critical for high-frequency operation (e.g., >100 kHz). For secondary-side synchronous rectifiers (SR) and VRM stages, ultra-low Rds(on) is paramount.
Package & Thermal Co-design: Choose high-power packages (TO-247, TO-263) with excellent thermal impedance (RthJC) for primary switches and high-current paths. Utilize compact packages (SOP8, TO-252) for auxiliary switches and point-of-load (POL) converters to maximize power density. Consider Kelvin-source configurations for optimal gate drive.
Reliability & Ruggedness for Critical Duty: Meet 24/7 operational demands under high ambient temperatures. Focus on high junction temperature rating (Tjmax ≥ 150°C), excellent thermal cycling capability, and inherent robustness against voltage spikes and transients.
(B) Scenario Adaptation Logic: Categorization by Power Stage Function
Divide the power supply into three core functional stages: First, the High-Voltage Input/Conversion Stage (e.g., PFC, LLC primary), requiring high-voltage withstand and efficient switching. Second, the High-Current, Intermediate DC-DC Stage (e.g., 48V-12V buck, SR), demanding ultra-low conduction loss and fast body diode. Third, the Auxiliary Power & Intelligent Control Stage, requiring compact, efficient switches for housekeeping, sequencing, and protection. This enables precise device-to-application matching.
II. Detailed Device Selection Scheme by Scenario
(A) Scenario 1: High-Voltage Input / Primary-Side Switching Stage – PFC & LLC Resonant Converter
This stage handles rectified line voltage (e.g., ~400VDC) and requires high-voltage devices with good switching performance for efficient power factor correction and resonant conversion.
Recommended Model: VBP110MR12 (N-MOS, 1000V, 12A, TO-247)
Parameter Advantages: 1000V drain-source voltage provides ample margin for 400V/800V bus applications, handling voltage spikes safely. Planar technology offers stable performance and good avalanche capability. TO-247 package facilitates excellent heat dissipation with low thermal resistance.
Adaptation Value: Ideal for the switch in a boost PFC circuit or as the primary switch in an LLC resonant converter. The high voltage rating ensures reliability against input surges common in industrial environments. When driven optimally, it supports switching frequencies suitable for high-power-density designs.
Selection Notes: Verify operating bus voltage and worst-case voltage spikes. Gate drive must be robust (VGS ≥ 12V) to ensure full enhancement and low Rds(on). Pay close attention to switching loss optimization due to relatively high Coss/Qg; use resonant or soft-switching topologies where possible. Adequate heatsinking is mandatory.
(B) Scenario 2: High-Current Intermediate Bus Conversion / Synchronous Rectification Stage – 48V to Point-of-Load (POL)
This stage converts an intermediate bus voltage (e.g., 48V/12V) to lower rails with extremely high output currents (tens to hundreds of Amps), demanding minimal conduction loss per switch.
Recommended Model: VBE1152N (N-MOS, 150V, 50A, TO-252)
Parameter Advantages: Exceptionally low Rds(on) of 19mΩ at 10V significantly reduces conduction loss. High continuous current rating of 50A (with high peak capability) is well-suited for multi-phase buck converter phases or synchronous rectification in isolated DC-DC modules. 150V rating is optimal for 48V bus applications (>3x margin). Trench technology provides excellent Rds(on)Area figure of merit.
Adaptation Value: As the control or synchronous FET in a high-current multi-phase buck regulator for GPU/CPU VRMs or as an SR FET in a 48V-12V converter. Its low loss directly translates to higher system efficiency (>96% target) and reduced thermal stress, enabling higher power density.
Selection Notes: Critical to parallel devices effectively in multi-phase designs. Ensure gate drive capability (low impedance) for fast switching to minimize cross-conduction loss. TO-252 (D2PAK) package requires substantial PCB copper pour (≥300mm²) and thermal vias for heat spreading. Implement accurate current sensing and per-phase thermal monitoring.
(C) Scenario 3: Auxiliary Power Management & Intelligent Control Stage – Housekeeping, OR-ing, Protection
This stage involves lower-power circuits for auxiliary rails (e.g., 12V, 5V, 3.3V), fan control, module enable/disable, and protection functions (e.g., OR-ing, hot-swap), requiring compact, efficient, and reliable switches.
Recommended Model: VBA2410 (P-MOS, -40V, -16.1A, SOP8)
Parameter Advantages: Very low Rds(on) of 10mΩ at 10V for a P-MOS in a compact SOP8 package minimizes voltage drop in power path applications. -40V VDS is suitable for switching on 12V/24V auxiliary buses. Low Vth of -1.8V allows for easy direct or level-shifted drive from logic. The small footprint saves valuable PCB space in dense layouts.
Adaptation Value: Perfect for high-side load switch applications (enabling/disabling auxiliary rails), ideal for OR-ing diodes replacement in redundant power paths to reduce loss, and suitable for fan speed control (PWM). Its efficiency and small size support the trend towards highly integrated, high-power-density auxiliary power boards.
Selection Notes: Confirm maximum load current and ensure it remains within safe operating limits with adequate derating. For high-side switching, ensure proper gate drive voltage (VGS) relative to the source pin. Although thermally capable, attention to PCB copper layout under the SOP8 pins is necessary for currents above 5A.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Optimized for Switching Performance
VBP110MR12: Pair with dedicated high-side gate driver ICs (e.g., IR2110, UCC5350) capable of sourcing/sinking >2A peak current. Use a low-inductance gate drive loop. Consider adding a small gate resistor (1-10Ω) to fine-tune switching speed and damp ringing.
VBE1152N: Use high-performance, multi-phase PWM controllers with integrated drivers (e.g., IR35201, TDA214xx) or discrete drivers placed very close to the MOSFETs. Implement adaptive dead-time control to minimize body diode conduction.
VBA2410: Can often be driven directly from a microcontroller GPIO through a small series resistor (22-100Ω). For faster switching or when driving capacitive loads, a simple NPN/PNP buffer stage is recommended. Include a pull-up resistor on the gate to ensure defined off-state.
(B) Thermal Management Design: Stage-Appropriate Cooling
VBP110MR12 (TO-247): Mount on a dedicated heatsink, possibly with forced air cooling. Use thermal interface material (TIM) and ensure proper mounting torque.
VBE1152N (TO-252): Implement extensive copper pours on the PCB (top and bottom layers connected by multiple thermal vias). For currents >30A per device, consider attaching a clip-on heatsink to the tab. Monitor temperature via nearby NTC thermistor.
VBA2410 (SOP8): Standard PCB copper layout (≥50mm² per pin) is usually sufficient. Ensure overall system airflow covers the auxiliary power section.
General: Implement comprehensive thermal monitoring via ICs or NTCs. Use temperature data for fan speed control and potential power throttling.
(C) EMC and Reliability Assurance
EMC Suppression:
VBP110MR12: Utilize snubber circuits (RC/RCD) across the drain-source if needed to damp high-frequency ringing. Ensure proper placement of input EMI filter (X/Y capacitors, common-mode choke).
VBE1152N: Minimize high di/dt loop areas (input capacitor to switch to inductor). Use low-ESR/ESL ceramic capacitors very close to the drain and source pins. Consider adding a small ferrite bead in series with the gate drive path.
VBA2410: For switching inductive loads (fans, solenoids), include a flyback diode or TVS protection.
PCB Layout: Strictly separate high-power noisy stages from sensitive analog/logic areas. Use ground planes effectively.
Reliability Protection:
Derating: Apply standard derating rules: Voltage (≤80% of rating), Current (derate based on Tj max and thermal design), Temperature (Tj ≤ 125°C for long-life applications).
Overcurrent/Short-Circuit Protection: Implement hardware-based protection using shunt resistors, comparators, or driver IC desat detection for primary switches (VBP110MR12). Use e-fuses or current-limit controllers for load switches (VBA2410).
Transient Protection: Employ TVS diodes at input terminals (AC and DC). Use avalanche-rated MOSFETs where applicable. Ensure proper input undervoltage/overvoltage lockout.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Power Conversion Efficiency: Strategic device selection targeting lowest loss per stage enables system efficiencies >96% (Platinum/Titanium level), reducing operational costs (OPEX) and cooling requirements.
Superior Power Density and Scalability: The combination of high-performance discrete devices (VBE1152N, VBA2410) allows for optimized, scalable power stage design, accommodating varying power levels from kilowatts to tens of kilowatts per rack.
Enhanced System Reliability for Critical Infrastructure: The selected devices, with robust voltage ratings and package options, are engineered for the demanding, continuous operation of AI data centers, minimizing downtime risk.
(B) Optimization Suggestions
Higher Frequency / Higher Efficiency: For next-generation PFC/LLC stages targeting >500kHz, consider investigating Super-Junction MOSFETs (like VBL165R20S for 650V applications) or GaN HEMTs for even lower switching losses.
Higher Current Density: For ultra-high-current POL applications (>100A per phase), explore dual or quad MOSFET packages in advanced low-inductance formats (e.g., PowerQFN, LFPAK) to further reduce parasitic and thermal impedance.
Enhanced Integration & Monitoring: For auxiliary power management, consider using intelligent load switch ICs that integrate the MOSFET, driver, protection (OCP, OTP), and diagnostic reporting (e.g., power good, fault flag).
Specialized Applications: For 3-phase AC input PFC or inverter stages, evaluate IGBT modules (like VBM16I30 for specific mid-power inverters) or use multiple VBP110MR12/VBL165R20S in parallel/bridge configurations.
Conclusion
Power semiconductor selection is central to achieving the trifecta of high efficiency, high power density, and unwavering reliability in AI industrial power supplies. This scenario-based, device-optimized scheme provides a clear technical roadmap for power supply designers. By matching the right device (VBP110MR12, VBE1152N, VBA2410) to its specific functional stage and adhering to rigorous system-level design practices, the development of cutting-edge power solutions for the AI era is accelerated, forming the robust energy foundation for future computing advancements.

Detailed Selection Topology by Scenario