With the rapid evolution of wearable technology and increasing consumer focus on health monitoring, high-end smartwatches have become integrated hubs for personal health and connectivity. The power management and peripheral drive systems, serving as the "energy heart and control nerves" of the device, provide precise power delivery and switching for critical loads such as haptic motors, multi-sensor arrays, and always-on displays. The selection of power MOSFETs directly determines the system's standby endurance, performance density, thermal management, and reliability. Addressing the stringent requirements of smartwatches for ultra-compact size, ultra-low quiescent current, precise control, and high reliability, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Four-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across four dimensions—voltage, loss, package, and leakage—ensuring precise matching with the system's ultra-constrained environment:
Minimal Voltage Footprint: For mainstream 3.3V/5V/VSYS (3.8V-4.4V) rails, select devices with a rated voltage just above the maximum system voltage with sufficient margin (typically ≥30% for Li-ion battery spikes), minimizing gate charge (Qg) and capacitance (Ciss/Coss) associated with higher voltage ratings.
Ultra-Low Loss Dominance: Prioritize devices with extremely low Rds(on) at low VGS (e.g., 2.5V, 4.5V) to minimize conduction loss from battery. Prioritize low Qg for switching loss and driver overhead. Prioritize low leakage current (IDSS, IGSS) to extend sleep mode battery life.
Package & Integration Criticality: Choose the smallest possible package (SC75-6, DFN, TSSOP8) with low thermal resistance. Prioritize dual/channel configurations in a single package (e.g., TSSOP8 dual) to save PCB area, which is at a premium.
Reliability for Dynamic Environment: Must withstand dynamic on-wrist conditions (temperature cycles, ESD from charging, mechanical shock). Focus on robust ESD ratings, stable Rds(on) over temperature, and a wide operating junction temperature range.
(B) Scenario Adaptation Logic: Categorization by Load Type
Divide loads into three core scenarios: First, Core Power Path Management & Distribution (Energy Gatekeeper), requiring ultra-low Rds(on) for efficiency and compact size. Second, Haptic Feedback Motor Drive (User Interface Core), requiring low-Rds(on) for strong torque and fast response, with possible dual-N configuration for H-bridge control. Third, Multi-Sensor/Peripheral Power Switching (Function Enabler), requiring small-signal switching with near-zero leakage for always-on sensors and selective peripheral activation.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: Core Power Path Management – Energy Gatekeeper
This involves load switches for main system rails, battery protection circuits, or charging path control. Key needs are minimal voltage drop (low Rds(on) at low VGS) and minimal package size to conserve space.
Recommended Model: VBTA8338 (P-MOS, -30V, -2.4A, SC75-6)
Parameter Advantages: SC75-6 is one of the smallest packages available. Rds(on) of 42mΩ @ VGS=4.5V is excellent for its size. -30V rating provides robust margin for battery-connected circuits. Low Vth of -1.7V ensures full enhancement by low-voltage PMIC GPIOs (1.8V/3.3V).
Adaptation Value: As a main power switch, its low Rds(on) minimizes voltage drop, maximizing usable battery energy. The tiny footprint saves critical board space for batteries or larger sensors. Low leakage ensures negligible drain during long-term sleep.
Selection Notes: Ensure the peak current (e.g., system startup surge) is within safe operating area. Adequate copper for heat spreading is still needed despite low loss. Ideal for placement directly at the battery or main VDD output of the PMIC.
(B) Scenario 2: Haptic Feedback Motor Drive – User Interface Core
Linear Resonant Actuators (LRAs) or Eccentric Rotating Mass (ERM) motors require an H-bridge for precise directional control. Needs include very low Rds(on) for strong drive and fast PWM, and a compact dual MOSFET solution.
Recommended Model: VBC6N2005 (Common Drain Dual N-MOS, 20V, 11A, TSSOP8)
Parameter Advantages: Exceptional Rds(on) of only 5mΩ @ VGS=4.5V, enabling high motor current with minimal loss and heat. Common-drain configuration in TSSOP8 is tailor-made for constructing one half of an H-bridge, simplifying layout. 20V rating is perfect for VSYS-based drives.
Adaptation Value: Enables sharp, strong, and efficient haptic feedback, crucial for premium user experience. The low Rds(on) allows for higher peak torque or longer duration effects without thermal issues. The integrated dual die saves significant area compared to two discrete MOSFETs.
Selection Notes: Requires a gate driver or PMIC capable of generating the high-side supply voltage (bootstrapping) for the high-side N-MOSFET in the H-bridge. Pair with a similar part or a dedicated H-bridge driver IC. Pay close attention to power loop layout to minimize inductance.
(C) Scenario 3: Multi-Sensor/Peripheral Power Switching – Function Enabler
This involves independently powering sensors (SPO2, bio-impedance, altimeter), GNSS modules, or communication backups (NFC). Needs are ultra-low leakage, small package, and often multiple channels.
Recommended Model: VBQF3211 (Dual N-MOS, 20V, 9.4A per ch., DFN8(3x3))
Parameter Advantages: Dual independent N-channel in a compact DFN8 package offers high design flexibility. Low Rds(on) of 10mΩ @ VGS=10V (and good performance at 4.5V) ensures minimal voltage drop. 20V rating is sufficient. DFN offers good thermal performance.
Adaptation Value: Allows individual, software-controlled power cycling of multiple peripherals, drastically reducing overall system sleep current by shutting down unused blocks. The dual channel effectively manages two independent loads, maximizing integration. Enables sophisticated power sequencing for sensor fusion hubs.
Selection Notes: Can be driven directly from a PMIC's low-voltage GPIO if Rds(on) at 1.8V is acceptable for the load current, or via a level translator. Use to implement "cold-switching" of sensors to eliminate leakage paths. Ensure proper gate driving to avoid slow turn-off causing cross-conduction in adjacent circuits.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Matching Device Characteristics
VBTA8338 (P-MOS Load Switch): Can often be driven directly by a PMIC GPIO. A small series resistor (e.g., 10Ω) on the gate is recommended to limit inrush current and damp ringing. Ensure the GPIO's pull-down strength is sufficient for fast turn-off.
VBC6N2005 (Motor H-Bridge): Requires a dedicated H-bridge motor driver IC (e.g., DRV2605, AW86907) with integrated gate drivers and bootstrapping circuitry. The PCB layout must minimize the high-current loop area (from VSYS -> High-side FET -> Motor -> Low-side FET -> GND).
VBQF3211 (Dual Peripheral Switch): Gate drive can be optimized based on turn-on/off speed requirements. For fastest switching, use a dedicated buffer. For lowest quiescent current, drive directly from a low-leakage GPIO with a series resistor.
(B) Thermal Management Design: Constrained-Space Strategy
Primary Heat Source (VBC6N2005): The motor drive MOSFETs see pulsed high currents. Use generous copper pours connected to the drain pins (which are also the switch nodes) for heat spreading. The use of an internal ground plane is critical. Keep duty cycle and peak current within the device's SOA at the maximum case temperature.
Secondary Heat Sources (VBTA8338, VBQF3211): For continuous conduction paths, ensure even a small copper area (≥ 5mm² per amp) is connected to the source/drain pins. Thermal vias under the DFN package of the VBQF3211 to an internal plane are highly effective.
System Integration: Place MOSFETs away from heat-sensitive sensors (e.g., skin temperature sensors). Utilize the watch casing as a final heat sink if electrically isolated.
(C) EMC and Reliability Assurance
EMC Suppression:
VBC6N2005: Keep motor leads short or use twisted pairs. A small RC snubber across the motor terminals or a ferrite bead in series can damp high-frequency noise generated by PWM.
VBQF3211: For switching inductive loads (e.g., a small antenna), consider a small TVS or snubber. Use localized decoupling capacitors (100nF + 1µF) very close to the drain pin of the switching MOSFET.
General: Maintain a solid, low-impedance ground plane. Isolate noisy motor/supply currents from sensitive analog sensor grounds.
Reliability Protection:
Derating Design: Derate VDS to <60% of rating for battery-connected switches. Derate continuous current based on worst-case (wrist in hot environment) thermal modeling.
Overcurrent Protection: Rely on the integrated protection of the PMIC or dedicated motor driver IC (for VBC6N2005). For load switches (VBTA8338, VBQF3211), the PMIC's integrated current limit or a fuse is typically used.
ESD/Surge Protection: All external connections (charging port, sensors) require ESD protection (e.g., TVS in tiny packages). Gate pins of externally accessible circuits should have series resistors and/or ESD clamps.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Battery Life and Performance: Ultra-low Rds(on) and leakage devices minimize energy waste, directly translating to longer usage between charges or enabling more powerful features.
Ultra-High Density Integration: The selection of miniature and multi-channel packages allows for more features in a constant or shrinking form factor, a key competitive edge.
Enhanced User Experience: Precise, strong motor control and reliable, independent sensor power management enable a responsive, always-aware, and premium-feeling product.
(B) Optimization Suggestions
For Even Lower VGS Operation: For systems running core rails at 1.8V, consider devices characterized for Rds(on) at VGS=1.5V/1.8V, though VBTA8338 with Vth=-1.7V is a strong candidate.
For Higher Voltage Rails: If a boost converter for displays or sensors generates a 12V rail, select devices like VBK7695 (60V) for switching that rail.
For Advanced Haptics: Pair the VBC6N2005 with a advanced haptic driver IC supporting auto-resonance tracking and waveform libraries for immersive feedback.
Integration Upgrade: Explore PMICs with integrated load switches and motor drivers to further reduce component count, though discrete solutions offer superior Rds(on) and flexibility.
Conclusion
Power MOSFET selection is central to achieving the trifecta of miniaturization, ultra-long endurance, and high performance in smartwatch design. This scenario-based scheme, from the energy gatekeeper to the interface enabler, provides a targeted component foundation. Future exploration can focus on even more integrated, wafer-level chip-scale packaged (WLCSP) MOSFETs and co-packaging with drivers, pushing the boundaries of next-generation wearable technology.

Detailed MOSFET Application Topology