With the rapid evolution of wearable technology and increasing demands for health monitoring, smartwatches have become essential personal devices. The power management and load switching systems, serving as the "energy hub and control nerve" of the entire unit, provide precise power delivery and control for key loads such as sensors, haptic feedback motors, and communication modules. The selection of power MOSFETs directly determines system efficiency, standby time, power density, and reliability. Addressing the stringent requirements of smartwatches for ultra-low power consumption, miniaturization, and high reliability, this article focuses on scenario-based adaptation to develop a practical and optimized MOSFET selection strategy.
I. Core Selection Principles and Scenario Adaptation Logic
(A) Core Selection Principles: Three-Dimensional Collaborative Adaptation
MOSFET selection requires coordinated adaptation across three dimensions—voltage & loss, package, and control compatibility—ensuring precise matching with the stringent constraints of wearable systems:
Adequate Voltage with Minimal Loss: For typical 3.8V Li-ion battery systems with charging voltages up to 5V, prioritize devices with rated voltages like 20V or 30V, providing ample margin for transients. Ultra-low Rds(on) is paramount to minimize conduction loss, directly extending battery life.
Ultra-Compact Packaging: The PCB area is extremely limited. Prioritize the smallest possible packages (e.g., SOT23-3, DFN) with good thermal characteristics to achieve high power density and allow space for other components.
Logic-Level Compatibility & Low Leakage: Must be fully driven by low-voltage (1.8V/3.3V) MCU GPIOs without need for level shifters. Very low gate charge (Qg) and leakage current are critical for efficient high-frequency switching and minimizing power loss in sleep modes.
(B) Scenario Adaptation Logic: Categorization by Load Type
Divide loads into three core scenarios based on function and power profile: First, High-Efficiency Power Conversion (e.g., DC-DC synchronous rectification), requiring ultra-low Rds(on) for core power path efficiency. Second, General-Purpose Load Switching (e.g., sensor/peripheral power rails), requiring the smallest footprint and logic-level drive for distributed control. Third, Dedicated Load/Protection Switching, requiring a balance of current capability, thermal performance, and voltage margin for specific higher-power or safety-critical paths.
II. Detailed MOSFET Selection Scheme by Scenario
(A) Scenario 1: High-Efficiency Power Conversion & Motor Drive – Core Power Device
Synchronous buck converters for the core SoC power supply and drivers for haptic motors demand minimal conduction loss and compact integration.
Recommended Model: VBBC3210 (Dual N+N MOSFET, 20V, 20A per channel, DFN8(3x3)-B)
Parameter Advantages: Trench technology achieves an exceptionally low Rds(on) of 17mΩ at 10V per channel. The 20V rating is ideal for battery-powered systems. The dual N-channel configuration in a single DFN8 package saves significant PCB area compared to two discrete FETs, while the package offers good thermal performance.
Adaptation Value: Dramatically reduces conduction loss in synchronous rectifier stages, boosting converter efficiency to >95%. The dual channels can be used independently (e.g., for two power rails) or paralleled for higher current capability (e.g., motor drive), offering design flexibility. Supports high-frequency switching for compact inductor sizing.
Selection Notes: Ensure the total power loss (conduction + switching) is within the thermal limits of the small package. Adequate copper pour under the DFN is essential for heat dissipation. Pair with a controller/driver IC capable of independently driving both high-side and low-side FETs.
(B) Scenario 2: General-Purpose Load Switch – Peripheral Control Device
Sensors (HRM, SpO2), GPS, and wireless modules require individual power gating for deep sleep power savings. The key is minimal footprint and guaranteed turn-on at low MCU voltage.
Recommended Model: VB1240 (Single N-MOSFET, 20V, 6A, SOT23-3)
Parameter Advantages: The SOT23-3 is one of the smallest practical packages. A low Vth range of 0.5V-1.5V ensures robust turn-on even with 1.8V MCU GPIOs under all temperature conditions. Rds(on) is a low 28mΩ at 4.5V, minimizing voltage drop and power loss.
Adaptation Value: Enables fine-grained power domain control, allowing inactive peripherals to be completely powered down, reducing system sleep current to microamp levels. Its tiny size allows placement close to the load it controls, simplifying PCB routing.
Selection Notes: Confirm the inrush current of the load is within safe limits. A small gate resistor (e.g., 10Ω) is recommended to damp ringing. For loads with large capacitance, implement soft-start control in the MCU firmware to limit turn-on surge current.
(C) Scenario 3: Dedicated Load / Protection Switch – Balanced Performance Device
Applications such as main power path switching, backlight LED array control, or battery terminal protection require a balance of current rating, thermal performance, and extra voltage margin.
Recommended Model: VBI1322G (Single N-MOSFET, 30V, 6.8A, SOT89)
Parameter Advantages: SOT89 package offers a better thermal resistance (RthJA) than SOT23, suitable for slightly higher continuous power dissipation. The 30V rating provides extra safety margin against voltage spikes, especially near the battery input. Rds(on) is a low 22mΩ at 4.5V.
Adaptation Value: Serves as a robust main system load switch or for controlling higher-current auxiliary circuits. The higher voltage rating is beneficial for input line protection. Its thermal performance allows it to handle short-duration peak currents better than smaller packages.
Selection Notes: Useful in locations where space is slightly less constrained but thermal management is a concern. Can be driven directly by an MCU GPIO. Ensure the PCB provides a modest copper pad for heat sinking.
III. System-Level Design Implementation Points
(A) Drive Circuit Design: Optimizing for Low Voltage
VBBC3210: Requires a dedicated gate driver capable of sourcing/sinking adequate peak current for fast switching. Keep gate drive loops exceptionally short. Bootstrap circuits for the high-side channel must be carefully designed for 100% duty cycle capability if needed.
VB1240 & VBI1322G: Can be driven directly from MCU GPIO pins. A series gate resistor (10-47Ω) is essential to limit peak drive current, reduce EMI, and prevent MCU pin overstress. For very fast switching, ensure the MCU's GPIO drive strength is sufficient.
(B) Thermal Management Design: PCB-as-a-Heatsink
Primary Strategy: All heat dissipation relies on the PCB copper. Use sufficient copper area connected to the drain pad (as per package recommendations), with multiple thermal vias connecting to internal ground/power planes for 4+ layer boards.
VBBC3210: Requires the most attention. Maximize copper pour under the DFN package. A 1oz copper weight is minimum; 2oz is preferred if board thickness allows.
VB1240: Local copper pour of ~10-20 mm² is typically sufficient due to its very low typical power dissipation.
VBI1322G: Provide a copper pad extending from the tab, with a area of ~30-50 mm² for optimal performance.
Layout: Avoid placing heat-sensitive components (e.g., crystal oscillators, specific sensors) near MOSFETs.
(C) EMC and Reliability Assurance
EMC Suppression:
Use small ceramic capacitors (100pF to 100nF) placed directly at the drain-source terminals of switching FETs (especially VBBC3210) to suppress high-frequency ringing.
Keep high-current switching loops (power path) as small as possible.
Use ferrite beads in series with power inputs to sensitive analog sub-circuits.
Reliability Protection:
Derating: Operate MOSFETs at ≤50% of rated VDS and ≤60-70% of rated ID under maximum ambient temperature (e.g., 45°C skin temperature + internal heating).
Inrush Current Limiting: Implement soft-start via MCU PWM or use an RC circuit on the gate for loads with high capacitance.
ESD Protection: Incorporate ESD protection diodes on all external connector pins and consider TVS diodes on the battery input line.
IV. Scheme Core Value and Optimization Suggestions
(A) Core Value
Maximized Battery Life: Ultra-low Rds(on) and logic-level compatibility minimize conduction losses and control overhead, directly contributing to longer usage between charges.
Ultra-Compact Form Factor: The use of SOT23-3 and DFN packages minimizes the footprint of the power management system, freeing up crucial space for larger batteries or additional features.
Enhanced System Reliability: Proper voltage derating, robust thermal design via PCB, and protection strategies ensure stable operation across the device's lifetime and environmental conditions.
(B) Optimization Suggestions
For Even Lower Rds(on): In space-constrained DC-DC applications, explore single N-channel devices in DFN packages (e.g., similar technology to VBBC3210 but single channel) if the dual channel is not needed.
For Lower Vth Requirements: In systems where the MCU core voltage may drop very low in sleep, ensure selected MOSFETs (like VB1240) have a Vth(max) well below the minimum guaranteed MCU GPIO output voltage.
For Higher Voltage Applications: If the design incorporates features requiring higher bus voltages (e.g., >5V), select devices from the same family with appropriate voltage ratings (e.g., 40V).
Integration Path: For the highest level of integration and simplest design, consider Power Management ICs (PMICs) with integrated load switches and synchronous buck controllers, using discrete MOSFETs only for higher-power or specialized paths.
Conclusion
Power MOSFET selection is central to achieving the trifecta of ultra-long battery life, miniature size, and robust reliability in smartwatch designs. This scenario-based scheme provides targeted technical guidance for R&D through precise matching of MOSFET characteristics to specific load requirements and system constraints. Future exploration can focus on MOSFETs with even lower Qg for higher frequency operation and advanced wafer-level chip-scale packaging (WLCSP) to further drive miniaturization, aiding in the development of the next generation of feature-rich, enduring wearable devices.

Detailed Scenario Topology Diagrams