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Optimization of Power Chain for On-Board Chargers: A Precise MOSFET Selection Scheme Based on PFC, Isolated DCDC, and Low-Voltage Distribution
OBC Power Chain Optimization Topology Diagram

OBC Power Chain Optimization: Complete System Topology

graph LR %% AC Input & PFC Stage subgraph "AC Input & Power Factor Correction (PFC)" AC_IN["Universal AC Input
85-265VAC"] --> EMI_FILTER["EMI Input Filter"] EMI_FILTER --> BRIDGE_RECT["Bridge Rectifier"] BRIDGE_RECT --> PFC_BOOST_INDUCTOR["Boost Inductor"] PFC_BOOST_INDUCTOR --> PFC_SWITCH_NODE["PFC Switching Node"] subgraph "PFC Switch MOSFET" Q_PFC["VBQF1154N
150V/25.5A"] end PFC_SWITCH_NODE --> Q_PFC Q_PFC --> HV_BUS["High-Voltage DC Bus
~375VDC"] PFC_CONTROLLER["PFC Controller"] --> PFC_DRIVER["Gate Driver"] PFC_DRIVER --> Q_PFC end %% Isolated DC-DC Conversion Stage subgraph "Isolated DC-DC LLC Resonant Converter" HV_BUS --> LLC_RESONANT_TANK["LLC Resonant Tank"] LLC_RESONANT_TANK --> HF_TRANSFORMER["High-Frequency Transformer
Primary"] subgraph "Primary Side Switch" Q_LLC_PRIMARY["VBQF1154N
150V/25.5A"] end HF_TRANSFORMER --> Q_LLC_PRIMARY Q_LLC_PRIMARY --> PRIMARY_GND["Primary Ground"] LLC_CONTROLLER["LLC Controller"] --> LLC_DRIVER["Gate Driver"] LLC_DRIVER --> Q_LLC_PRIMARY HF_TRANSFORMER --> SEC_OUTPUT["Transformer Secondary"] subgraph "Synchronous Rectification MOSFETs" Q_SR["VBGQF1806
80V/56A
Ultra-Low Rds(on)"] end SEC_OUTPUT --> Q_SR Q_SR --> DC_OUTPUT["Isolated DC Output
Battery Voltage"] SYNC_RECT_CONTROLLER["Synchronous Rectifier Controller"] --> SYNC_DRIVER["Negative Voltage Driver"] SYNC_DRIVER --> Q_SR end %% Low-Voltage Distribution Stage subgraph "Post-Regulation & Low-Voltage Distribution" DC_OUTPUT --> INTERMEDIATE_BUS["Intermediate DC Bus"] subgraph "Multi-Rail Synchronous Buck Converters" BUCK1["Buck Converter 1
(e.g., 12V)"] BUCK2["Buck Converter 2
(e.g., 5V)"] end INTERMEDIATE_BUS --> BUCK1 INTERMEDIATE_BUS --> BUCK2 subgraph "Integrated Half-Bridge Power Stage" Q_BUCK["VBQF3310G
30V/35A
Half-Bridge Pair"] end BUCK1 --> Q_BUCK BUCK2 --> Q_BUCK Q_BUCK --> BUCK_INDUCTOR["Buck Inductor"] BUCK_INDUCTOR --> LV_OUTPUT1["Low-Voltage Rail 1
12V"] BUCK_INDUCTOR --> LV_OUTPUT2["Low-Voltage Rail 2
5V"] DIGITAL_PMIC["Digital PMIC/PWM Controller"] --> BUCK_DRIVER["Buck Driver"] BUCK_DRIVER --> Q_BUCK end %% Load Distribution & Control subgraph "Intelligent Load Management & Control" MCU["Main Control MCU"] --> LOAD_SWITCH_CONTROL["Load Switch Control"] subgraph "Load Switch Applications" SW_AUX["Auxiliary Systems"] SW_CONTROL["Control Circuitry"] SW_COMM["Communication Modules"] end LOAD_SWITCH_CONTROL --> SW_AUX LOAD_SWITCH_CONTROL --> SW_CONTROL LOAD_SWITCH_CONTROL --> SW_COMM LV_OUTPUT1 --> SW_AUX LV_OUTPUT2 --> SW_CONTROL SW_AUX --> VEHICLE_AUX["Vehicle Auxiliary Loads"] SW_CONTROL --> CONTROL_CIRCUITS["OBC Control Circuits"] SW_COMM --> CAN_BUS["Vehicle CAN Bus"] end %% Protection & Monitoring subgraph "System Protection & Monitoring" subgraph "Electrical Protection" SNUBBER_PFC["RCD Snubber
(PFC Stage)"] SNUBBER_LLC["RC Absorption
(LLC Stage)"] TVS_ARRAY["TVS/Gate Protection"] BODY_DIODE_PROT["Body Diode Protection"] end subgraph "Monitoring Sensors" CURRENT_SENSE["High-Precision Current Sensing"] TEMP_SENSORS["NTC Temperature Sensors"] VOLTAGE_MONITOR["Voltage Monitoring"] end SNUBBER_PFC --> Q_PFC SNUBBER_LLC --> Q_LLC_PRIMARY TVS_ARRAY --> PFC_DRIVER TVS_ARRAY --> LLC_DRIVER BODY_DIODE_PROT --> Q_SR CURRENT_SENSE --> MCU TEMP_SENSORS --> MCU VOLTAGE_MONITOR --> MCU end %% Thermal Management subgraph "Hierarchical Thermal Management" COOLING_LEVEL1["Level 1: Primary Heatsink
(Forced Cooling)"] --> Q_PFC COOLING_LEVEL1 --> Q_LLC_PRIMARY COOLING_LEVEL1 --> HF_TRANSFORMER COOLING_LEVEL2["Level 2: Secondary Heatsink
(Airflow)"] --> Q_SR COOLING_LEVEL3["Level 3: PCB Thermal Design
(Conduction)"] --> Q_BUCK COOLING_LEVEL3 --> BUCK_INDUCTOR TEMP_SENSORS --> THERMAL_CONTROLLER["Thermal Management Controller"] THERMAL_CONTROLLER --> FAN_CONTROL["Fan/Pump Control"] end %% Communication & Control Links MCU --> PFC_CONTROLLER MCU --> LLC_CONTROLLER MCU --> DIGITAL_PMIC MCU --> CLOUD_INTERFACE["Cloud Communication"] %% Style Definitions style Q_PFC fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_SR fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_BUCK fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Preface: Building the "Energy Gateway" for Electric Vehicles – Discussing the Systems Thinking Behind Power Device Selection
In the core ecosystem of electric vehicle energy replenishment, the on-board charger (OBC) is a sophisticated "energy gateway" responsible for efficiently and safely converting grid AC power into battery DC power. Its performance metrics—high power density, high conversion efficiency, electromagnetic compatibility, and reliable thermal management—are fundamentally determined by the optimal selection and application of power semiconductor devices at each conversion node. This article adopts a holistic, application-driven design philosophy to address the core challenge: how to select the most suitable power MOSFETs for the critical stages of Power Factor Correction (PFC), high-frequency isolated DC-DC conversion, and post-regulation low-voltage distribution, under stringent constraints of cost, volume, and automotive-grade reliability.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The Front-End Efficiency Guardian: VBQF1154N (150V, 25.5A, DFN8) – PFC Stage / DC-DC Primary Side Switch
Core Positioning & Topology Deep Dive: Ideally suited for the critical switching node in a Boost PFC circuit or as the primary switch in an isolated DC-DC converter (e.g., LLC resonant half-bridge). Its 150V drain-source voltage rating provides a robust safety margin for universal input OBCs (85-265VAC, rectified DC up to ~375V). The low Rds(on) of 35mΩ @10V directly minimizes conduction losses, which is crucial for achieving high full-load efficiency.
Key Technical Parameter Analysis:
Balanced Performance: The 3V typical threshold voltage (Vth) ensures good noise immunity while remaining easy to drive. The DFN8(3x3) package offers an excellent thermal resistance to footprint ratio, facilitating heat dissipation in high-density designs.
Technology Choice: Trench MOSFET technology provides a favorable balance between low on-resistance and switching performance, making it cost-effective for the demanding but cost-sensitive OBC market.
Application Fit: Its voltage and current ratings align perfectly with 3.3-6.6kW OBC designs, serving as a reliable and efficient workhorse in the front-end power conversion stage.
2. The High-Frequency Conversion Enabler: VBGQF1806 (80V, 56A, DFN8) – DC-DC Secondary Side Synchronous Rectifier
Core Positioning & System Benefit: As the core synchronous rectifier (SR) MOSFET on the secondary side of an isolated DC-DC stage (e.g., in an LLC converter), its ultra-low Rds(on) of 7.5mΩ @10V is paramount. This exceptionally low resistance is the key to minimizing the dominant conduction losses in SRs, where current is high and duty cycle is large.
Key Technical Parameter Analysis:
Ultra-Low Loss Core: The use of SGT (Shielded Gate Trench) technology enables this remarkably low Rds(on) in a compact DFN package, directly translating to higher system efficiency and reduced thermal stress on the secondary side.
High Current Capability: With a continuous drain current rating of 56A, it can handle high output currents typical of fast-charging OBCs, supporting high power delivery to the battery.
Voltage Margin: The 80V rating is well-suited for secondary-side voltages in OBCs (typically battery voltage up to ~60V for 400V systems), providing ample headroom for voltage spikes.
3. The Intelligent Post-Regulation Manager: VBQF3310G (30V, 35A, DFN8) – Multi-Output Low-Voltage Synchronous Buck Converter / Load Switch
Core Positioning & System Integration Advantage: This integrated half-bridge (N+N) pair in a single DFN8 package is a strategic component for compact, multi-rail post-regulation. It can seamlessly form the core switching stage of a non-isolated synchronous buck converter, generating various low-voltage rails (e.g., 12V, 5V) for the vehicle's auxiliary systems and the charger's own control circuitry from a stable intermediate bus.
Key Technical Parameter Analysis:
High-Density Integration: The half-bridge configuration saves significant PCB area and simplifies layout compared to using two discrete MOSFETs, improving power loop inductance and switching performance.
Optimized for High Frequency: With low Rds(on) (9mΩ @10V per FET) and presumably optimized internal gate charge, it is designed for efficient operation at the high switching frequencies (500kHz-1MHz+) used in modern point-of-load converters, enabling the use of smaller inductors and capacitors.
Dual Role Flexibility: Beyond buck converters, this pair can also be configured as a high-current, low-loss load distribution switch for enabling/disabling major auxiliary loads managed by the OBC controller.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Coordination
PFC/LLC Primary Control: The driver for VBQF1154N must interface precisely with the PFC or LLC controller, ensuring critical timing for ZVS (Zero Voltage Switching) where applicable. Its gate drive loop must be optimized for clean switching to meet EMI standards.
Synchronous Rectification Strategy: The VBGQF1806 typically requires a dedicated SR controller or a controller with integrated SR timing logic to accurately turn on/off in sync with the transformer secondary voltage, maximizing efficiency gains over diode rectification.
Multi-Rail Digital Power Management: The VBQF3310G in buck converter applications will be driven by a dedicated digital PWM controller (e.g., a PMIC), allowing for programmable output voltage, sequencing, and dynamic response to load changes on the auxiliary rails.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Forced Cooling): The VBQF1154N (PFC/primary) and VBGQF1806 (SR) are primary heat sources. They should be placed on a dedicated thermal pad connected to the system's primary heatsink, often coupled with the transformer/magnetics.
Secondary Heat Source (PCB Conduction + Airflow): The VBQF3310G and its associated buck inductor will generate localized heat. A combination of a thick copper PCB pour, thermal vias under its DFN package, and airflow from the system fan is essential for reliable operation.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
VBQF1154N: Snubber networks are crucial to dampen voltage spikes caused by transformer leakage inductance or PCB parasitic inductance during turn-off.
VBGQF1806: As an SR, its body diode can be subjected to hard commutation if timing is imperfect. The controller's dead-time must be carefully set, and its VDS rating provides a key buffer.
VBQF3310G: Input and output capacitors must be placed very close to the package to minimize high-frequency ringing in the switching power loop.
Enhanced Gate Protection: All devices require robust gate driving. Series gate resistors should be optimized, and local TVS or Zener diodes (respecting the ±20V or ±12V Vgs limits) are recommended to protect against transients.
Automotive Derating Practice:
Voltage Derating: Operate VBQF1154N VDS below 120V (80% of 150V) considering worst-case input transients. Ensure VBGQF1806 VDS has margin above the maximum secondary reflected voltage.
Thermal Derating: All junction temperatures must be derated from absolute maximums. A target Tj max of 125°C or lower under worst-case ambient conditions ensures long-term reliability. Utilize the thermal impedance data from datasheets for accurate loss and temperature estimation.
III. Quantifiable Perspective on Scheme Advantages
Quantifiable Efficiency Gains: Using VBGQF1806 as the SR in a 6.6kW OBC can reduce secondary-side conduction losses by over 40% compared to standard MOSFETs, directly boosting peak efficiency by 0.3-0.5% and reducing thermal load.
Quantifiable Power Density Improvement: The combination of VBQF1154N (DFN8) and VBQF3310G (integrated half-bridge) versus discrete TO-220 or SO-8 solutions can reduce the power stage PCB footprint by more than 35%, enabling more compact OBC designs.
System Reliability & Cost Optimization: Selecting these application-optimized, package-advanced devices reduces the number of components and solder joints, improving MTBF. The efficiency gains also reduce the required heatsink size, contributing to overall system cost savings.
IV. Summary and Forward Look
This scheme constructs a highly optimized power device chain for on-board chargers, covering high-voltage AC-DC conversion, high-frequency isolated DC-DC transformation, and intelligent multi-rail low-voltage generation.
Input/Primary Stage – Focus on "Robust Efficiency": Select a balanced, cost-effective MOSFET (VBQF1154N) with sufficient voltage margin and low loss.
Isolated Output Stage – Focus on "Ultra-Low Conduction Loss": Invest in the secondary-side SR (VBGQF1806) with the lowest possible Rds(on) for maximum efficiency payoff.
Post-Regulation Stage – Focus on "Integrated Intelligence": Employ highly integrated multi-MOSFET solutions (VBQF3310G) to achieve compact, flexible, and efficient point-of-load conversion.
Future Evolution Directions:
Wide Bandgap Adoption: For next-generation ultra-high efficiency and high-power density OBCs (>11kW), the PFC and primary LLC stage can transition to GaN HEMTs, while SiC MOSFETs can be used for the SR, enabling MHz+ switching frequencies.
Fully Integrated Power Stages: The trend towards integrating drivers, controllers, protection, and MOSFETs into single modules or ICs will further simplify design, enhance performance, and improve reliability for automotive power conversion.

Detailed Stage Topology Diagrams

PFC & Primary DC-DC Stage Detail

graph LR subgraph "Power Factor Correction (PFC) Stage" AC_IN["AC Input"] --> EMI["EMI Filter"] EMI --> RECT["Bridge Rectifier"] RECT --> L_PFC["Boost Inductor"] L_PFC --> NODE_PFC["PFC Switch Node"] NODE_PFC --> Q1["VBQF1154N
150V/25.5A"] Q1 --> HV_BUS["HV DC Bus (~375V)"] D1["Boost Diode"] --> HV_BUS NODE_PFC --> D1 C_PFC["Output Capacitor"] --> HV_BUS HV_BUS --> GND_PFC["PFC Ground"] PFC_IC["PFC Controller IC"] --> DRV_PFC["Gate Driver"] DRV_PFC --> Q1 end subgraph "LLC Primary Side" HV_BUS --> LLC_TANK["LLC Resonant Tank
(Lr, Cr, Lm)"] LLC_TANK --> TRANS_PRI["Transformer Primary"] subgraph "Half-Bridge Switches" Q2["VBQF1154N
High-Side"] Q3["VBQF1154N
Low-Side"] end TRANS_PRI --> NODE_LLC["LLC Switching Node"] NODE_LLC --> Q2 Q3 --> GND_LLC["Primary Ground"] HV_BUS --> Q2 NODE_LLC --> Q3 LLC_IC["LLC Controller"] --> DRV_LLC["Half-Bridge Driver"] DRV_LLC --> Q2 DRV_LLC --> Q3 end subgraph "Protection & Sensing" RCD["RCD Snubber"] --> Q1 RC["RC Absorption"] --> Q2 RC --> Q3 CS_PFC["Current Sense"] --> PFC_IC CS_LLC["Current Sense"] --> LLC_IC end style Q1 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q2 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q3 fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

Isolated DC-DC & Synchronous Rectification Detail

graph LR subgraph "Transformer & Secondary Side" TRANS_SEC["Transformer Secondary"] --> SR_NODE["Synchronous Rectification Node"] subgraph "Synchronous Rectification Bridge" SR1["VBGQF1806
80V/56A"] SR2["VBGQF1806
80V/56A"] end SR_NODE --> SR1 SR_NODE --> SR2 SR1 --> OUTPUT_FILTER["LC Output Filter"] SR2 --> GND_SEC["Secondary Ground"] OUTPUT_FILTER --> VOUT["DC Output to Battery"] end subgraph "Synchronous Rectification Control" SR_IC["SR Controller"] --> DRV_SR["Negative Voltage Driver"] DRV_SR --> SR1 DRV_SR --> SR2 TRANS_SEC --> ZCD["Zero-Crossing Detection"] ZCD --> SR_IC VOUT --> VOLT_FB["Voltage Feedback"] VOLT_FB --> SR_IC end subgraph "Protection Features" DEAD_TIME["Dead-Time Control"] --> SR_IC BODY_DIODE["Body Diode Protection"] --> SR1 BODY_DIODE --> SR2 TVS_SR["TVS Protection"] --> DRV_SR end style SR1 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style SR2 fill:#e3f2fd,stroke:#2196f3,stroke-width:2px

Low-Voltage Distribution & Load Management Detail

graph LR subgraph "Multi-Rail Buck Converter" VIN["Intermediate Bus (e.g., 48V)"] --> BUCK_INPUT["Buck Input"] subgraph "Integrated Half-Bridge" HS["VBQF3310G High-Side"] LS["VBQF3310G Low-Side"] end BUCK_INPUT --> SW_NODE["Switching Node"] HS --> SW_NODE LS --> BUCK_GND["Ground"] SW_NODE --> BUCK_INDUCTOR["Buck Inductor"] BUCK_INDUCTOR --> VOUT_RAIL["Output Rail (e.g., 12V/5V)"] BUCK_CAP["Output Capacitor"] --> VOUT_RAIL BUCK_CONTROLLER["Digital PWM Controller"] --> BUCK_DRIVER["Driver"] BUCK_DRIVER --> HS BUCK_DRIVER --> LS end subgraph "Load Switch Configuration" MCU_GPIO["MCU GPIO"] --> LEVEL_SHIFTER["Level Shifter"] LEVEL_SHIFTER --> LOAD_SW["VBQF3310G as Load Switch"] VCC["Input Voltage"] --> LOAD_SW LOAD_SW --> LOAD["Controlled Load"] LOAD --> LOAD_GND["Load Ground"] end subgraph "Control & Sequencing" PMIC["Power Management IC"] --> BUCK_CONTROLLER PMIC --> SEQUENCING["Rail Sequencing"] PMIC --> FAULT_MGMT["Fault Management"] VOUT_RAIL --> VOLT_MON["Voltage Monitor"] CUR_MON["Current Monitor"] --> FAULT_MGMT end subgraph "PCB Layout Considerations" THERMAL_VIAS["Thermal Vias"] --> HS THERMAL_VIAS --> LS POWER_LOOP["Minimized Power Loop"] --> BUCK_INPUT POWER_LOOP --> BUCK_CAP DECOUPLING["Local Decoupling"] --> BUCK_CONTROLLER end style HS fill:#fff3e0,stroke:#ff9800,stroke-width:2px style LS fill:#fff3e0,stroke:#ff9800,stroke-width:2px style LOAD_SW fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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