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Optimization of Power Chain for Automotive Electric Power Steering Systems: A Precise Semiconductor Selection Scheme Based on Motor Drive, Control Logic, and Auxiliary Management
Automotive EPS Power Chain Optimization Topology Diagram

Automotive EPS Power Chain System Overall Topology Diagram

graph LR %% Power Input Section subgraph "Automotive Power Input & Distribution" BATTERY["Automotive Battery
12V/24V"] --> INPUT_PROT["Input Protection & Filtering
TVS, Fuse, EMC Filter"] INPUT_PROT --> MAIN_PWR_BUS["Main Power Bus"] INPUT_PROT --> AUX_PWR_BUS["Auxiliary Power Bus"] end %% Motor Drive Section subgraph "BLDC Motor Drive Inverter Bridge" MAIN_PWR_BUS --> INVERTER_BUS["DC-Link Bus"] INVERTER_BUS --> PHASE_U_L["Phase U High-Side"] INVERTER_BUS --> PHASE_V_L["Phase V High-Side"] INVERTER_BUS --> PHASE_W_L["Phase W High-Side"] subgraph "Three-Phase Inverter MOSFET Array" Q_UH["VBE1105
100V/100A
TO-252"] Q_VH["VBE1105
100V/100A
TO-252"] Q_WH["VBE1105
100V/100A
TO-252"] Q_UL["VBE1105
100V/100A
TO-252"] Q_VL["VBE1105
100V/100A
TO-252"] Q_WL["VBE1105
100V/100A
TO-252"] end PHASE_U_L --> Q_UH PHASE_V_L --> Q_VH PHASE_W_L --> Q_WH Q_UH --> MOTOR_U["Motor Phase U"] Q_VH --> MOTOR_V["Motor Phase V"] Q_WH --> MOTOR_W["Motor Phase W"] MOTOR_U --> Q_UL MOTOR_V --> Q_VL MOTOR_W --> Q_WL Q_UL --> GND_MOTOR Q_VL --> GND_MOTOR Q_WL --> GND_MOTOR end %% Control & Logic Power Section subgraph "ECU Control Logic Power Path" AUX_PWR_BUS --> PRE_REG["Pre-Regulator & Filter"] PRE_REG --> MAIN_SW_NODE["Main Supply Switch Node"] MAIN_SW_NODE --> Q_LOGIC["VBGQA1304
30V/50A
DFN8 5x6
Rds(on)=4mΩ"] Q_LOGIC --> LOGIC_PWR_BUS["Clean Logic Power Bus
5V/3.3V"] LOGIC_PWR_BUS --> MCU["Main Control MCU
with FOC Algorithm"] LOGIC_PWR_BUS --> SENSORS["Torque & Position Sensors"] LOGIC_PWR_BUS --> GATE_DRIVERS["Three-Phase Gate Drivers"] GATE_DRIVERS --> Q_UH_GATE["Gate Drive UH"] GATE_DRIVERS --> Q_UL_GATE["Gate Drive UL"] GATE_DRIVERS --> Q_VH_GATE["Gate Drive VH"] GATE_DRIVERS --> Q_VL_GATE["Gate Drive VL"] GATE_DRIVERS --> Q_WH_GATE["Gate Drive WH"] GATE_DRIVERS --> Q_WL_GATE["Gate Drive WL"] Q_UH_GATE --> Q_UH Q_UL_GATE --> Q_UL Q_VH_GATE --> Q_VH Q_VL_GATE --> Q_VL Q_WH_GATE --> Q_WH Q_WL_GATE --> Q_WL end %% Auxiliary Load Management Section subgraph "Auxiliary Load Control & Management" AUX_PWR_BUS --> AUX_SW_BUS["Auxiliary Switch Bus"] subgraph "High-Side Auxiliary Switches" Q_CLUTCH["VBA1101N
100V/16A
SOP8"] Q_FAN["VBA1101N
100V/16A
SOP8"] Q_DIAG["VBA1101N
100V/16A
SOP8"] Q_SPARE["VBA1101N
100V/16A
SOP8"] end AUX_SW_BUS --> Q_CLUTCH AUX_SW_BUS --> Q_FAN AUX_SW_BUS --> Q_DIAG AUX_SW_BUS --> Q_SPARE MCU --> CLUTCH_CTRL["Clutch Control"] MCU --> FAN_CTRL["Fan Control"] MCU --> DIAG_CTRL["Diagnostic Control"] MCU --> SPARE_CTRL["Spare Control"] CLUTCH_CTRL --> Q_CLUTCH_GATE["Gate Drive"] FAN_CTRL --> Q_FAN_GATE["Gate Drive"] DIAG_CTRL --> Q_DIAG_GATE["Gate Drive"] SPARE_CTRL --> Q_SPARE_GATE["Gate Drive"] Q_CLUTCH_GATE --> Q_CLUTCH Q_FAN_GATE --> Q_FAN Q_DIAG_GATE --> Q_DIAG Q_SPARE_GATE --> Q_SPARE Q_CLUTCH --> CLUTCH_LOAD["Clutch Solenoid Load"] Q_FAN --> FAN_LOAD["Cooling Fan Load"] Q_DIAG --> DIAG_LOAD["Diagnostic Circuit"] Q_SPARE --> SPARE_LOAD["Spare Auxiliary Load"] CLUTCH_LOAD --> GND_AUX FAN_LOAD --> GND_AUX DIAG_LOAD --> GND_AUX SPARE_LOAD --> GND_AUX end %% Protection & Monitoring Section subgraph "System Protection & Diagnostics" subgraph "DC-Link Protection" DC_TVS["TVS Array
Load Dump Protection"] DC_CAP["DC-Link Capacitors
Low-ESR Electrolytic"] SNUBBER["Snubber Circuit
for Voltage Spikes"] end subgraph "Current Sensing & Monitoring" SHUNT_RES["Shunt Resistors
Phase Current Sensing"] ISOL_AMP["Isolated Amplifiers"] ADC_INPUT["MCU ADC Inputs"] end subgraph "Temperature Monitoring" NTC_MOTOR["NTC on Motor Housing"] NTC_MOSFET["NTC on Inverter Heatsink"] NTC_ECU["NTC in ECU Enclosure"] end DC_TVS --> INVERTER_BUS DC_CAP --> INVERTER_BUS SNUBBER --> Q_UH SNUBBER --> Q_VH SNUBBER --> Q_WH SHUNT_RES --> ISOL_AMP ISOL_AMP --> ADC_INPUT ADC_INPUT --> MCU NTC_MOTOR --> MCU NTC_MOSFET --> MCU NTC_ECU --> MCU end %% Thermal Management Section subgraph "Hierarchical Thermal Management" COOLING_LEVEL1["Level 1: Metal Substrate/Forced Air
Motor Inverter MOSFETs"] --> Q_UH COOLING_LEVEL1 --> Q_VH COOLING_LEVEL1 --> Q_WH COOLING_LEVEL1 --> Q_UL COOLING_LEVEL1 --> Q_VL COOLING_LEVEL1 --> Q_WL COOLING_LEVEL2["Level 2: PCB Thermal Relief
Control Logic MOSFET"] --> Q_LOGIC COOLING_LEVEL3["Level 3: Natural Convection
Auxiliary Switches"] --> Q_CLUTCH COOLING_LEVEL3 --> Q_FAN COOLING_LEVEL3 --> Q_DIAG MCU --> FAN_PWM["PWM Fan Control Output"] FAN_PWM --> Q_FAN_GATE end %% Communication & Interfaces MCU --> CAN_TRANS["CAN Transceiver"] CAN_TRANS --> VEHICLE_CAN["Vehicle CAN Bus"] MCU --> DIAG_INTERFACE["Diagnostic Interface
OBD-II/UDS"] %% Style Definitions style Q_UH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_LOGIC fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style Q_CLUTCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Preface: Architecting the "Neuromuscular System" for Vehicle Dynamics – A Systems Approach to Power Device Selection in EPS
In the critical domain of automotive safety and dynamics, the Electric Power Steering (EPS) system stands as a prime example of electromechanical integration. Its performance metrics—responsive assist, precise torque control, silent operation, and unwavering reliability—are fundamentally determined by the efficacy of its power electronic conversion chain. This chain must handle high burst currents for motor torque, ensure flawless low-power signal integrity, and manage auxiliary functions, all within the stringent constraints of automotive-grade temperature ranges, EMI compliance, and cost.
This analysis adopts a systems engineering perspective to address the core challenge in EPS power design: selecting the optimal power switches for the three critical nodes—the high-current motor drive bridge, the low-voltage control & logic supply, and the auxiliary load management—balancing ultra-low loss, high reliability, miniaturization, and robust protection.
I. In-Depth Analysis of the Selected Device Combination and Application Roles
1. The Muscle of Steering: VBE1105 (100V, 100A, TO-252) – Main 3-Phase Brushless DC (BLDC) Motor Inverter Switch
Core Positioning & Topology Deep Dive: As the core switch in the low-voltage, high-current three-phase inverter bridge for the EPS motor. Its extremely low Rds(on) of 5mΩ @10V is critical for minimizing conduction loss, which directly translates to system efficiency, thermal management headroom, and maximum continuous/peak assist torque capability. The 100V rating provides robust margin for 12V/24V automotive systems, accommodating load dump and other transients.
Key Technical Parameter Analysis:
Ultra-Low Conduction Loss: The primary contributor to power loss in the motor drive under high-duty-cycle, high-current assist scenarios (e.g., parking). This low Rds(on) maximizes battery energy utilization for steering assist.
High Current Capability: The 100A rating, combined with the thermally enhanced TO-252 (D2PAK) package, ensures reliable handling of stall currents and peak torque demands.
Drive & Switching Considerations: While Rds(on) is paramount, its gate charge (Qg) must be evaluated to ensure the gate driver can achieve fast switching, reducing switching losses at typical PWM frequencies (10-20kHz) and improving current loop bandwidth for precise control.
2. The Intelligent Core Enabler: VBGQA1304 (30V, 50A, DFN8 5x6) – Control Unit Power Path & Pre-Driver Supply Switch
Core Positioning & System Benefit: This device serves as the high-efficiency, compact switch for distributing power within the EPS Control Unit (ECU), particularly to critical loads like the microcontroller, sensors, and gate driver ICs. Its very low Rds(on) of 4mΩ @10V (SGT technology) minimizes voltage drop and power loss on the primary logic supply rail.
Key Technical Parameter Analysis:
Power Density & Efficiency: The DFN8 (5x6) package offers superior thermal performance and minimal footprint, crucial for compact ECU design. Low loss is key for always-on or frequently active control circuits.
SGT Technology Advantage: Shielded Gate Trench technology typically offers an excellent balance of low Rds(on), low gate charge, and robustness, ideal for clean power switching in the noisy automotive electrical environment.
Application Role: Can be used for active in-rush current limiting, power sequencing, or as a main supply switch controlled by the ECU's wake-up/sleep logic, enhancing system-level power management.
3. The Auxiliary & Protection Sentinel: VBA1101N (100V, 16A, SOP8) – Auxiliary Solenoid/Valve Control & General-Purpose High-Side Switch
Core Positioning & System Integration Advantage: This N-channel MOSFET in a space-saving SOP8 package is ideal for controlling medium-power auxiliary loads within the EPS system, such as the clutch solenoid (for column-type EPS), cooling fan, or diagnostic load circuits. Its 100V rating aligns with automotive electrical robustness requirements.
Key Technical Parameter Analysis:
Versatile High-Side/Low-Side Use: As an N-channel device, it can be used in either configuration. For high-side switching, a charge pump or bootstrap driver is needed, but it offers lower Rds(on) compared to similar P-channel parts.
Balance of Performance & Size: With 9mΩ Rds(on) and 16A capability, it provides a solid performance-to-size ratio for auxiliary functions, reducing the need for bulky relays.
Protection & Diagnostics: Its fast switching allows for quick shutdown in fault conditions. The status of such switches can be monitored for diagnostics, contributing to functional safety goals.
II. System Integration Design and Expanded Key Considerations
1. Topology, Drive, and Control Loop Synergy
Motor Drive & FOC Control: The VBE1105 trio forms the inverter bridge for the EPS motor. Their switching performance must be tightly matched and synchronized by a dedicated gate driver IC to implement precise Field-Oriented Control (FOC) or advanced BLDC control algorithms, minimizing torque ripple.
Logic Power Integrity: The VBGQA1304, supplying the ECU core, must be driven to ensure stable voltage rail even during engine cranking or load transients. Its control can be integrated into the ECU's power management IC.
Auxiliary Load Management: The VBA1101N is typically driven by a GPIO pin of the microcontroller via a simple driver stage, allowing software-controlled activation/deactivation of auxiliary functions.
2. Hierarchical Thermal Management Strategy
Primary Heat Source (Metal Substrate/Forced Air): The three VBE1105 devices on the motor inverter are the main heat sources. They must be mounted on a thermally conductive isolated metal substrate or a heatsink, possibly integrated with the EPS housing for heat dissipation.
Secondary Heat Source (PCB Thermal Relief): The VBGQA1304, while efficient, may require a dedicated thermal pad connection to internal PCB ground planes for heat spreading, given its high current capability in a small package.
Tertiary Heat Source (Natural Convection): The VBA1101N and similar auxiliary switches can typically rely on the PCB's copper area and natural convection, given their lower average power dissipation.
3. Engineering Details for Reliability Reinforcement
Electrical Stress Protection:
Motor Inverter (VBE1105): Snubber networks or careful layout is needed to manage voltage spikes caused by motor winding inductance during switching. TVS diodes on the DC-link are mandatory for load dump protection.
Inductive Load Control (VBA1101N): Freewheeling diodes must be placed across inductive loads (solenoids) to protect the MOSFET from turn-off voltage spikes.
Enhanced Gate Protection: All gate drive circuits should include series resistors, low-ESD pull-down resistors, and Zener diode clamps (appropriate to VGS max) to protect against transients and ensure reliable turn-off.
Derating Practice:
Voltage Derating: Ensure VDS for VBE1105 and VBA1101N operates below 80% of 100V under worst-case transients. For VBGQA1304, keep VDS well below 24V.
Current & Thermal Derating: Use junction temperature and transient thermal impedance data to derate continuous and pulse current ratings. The maximum junction temperature should be derated from the absolute maximum (e.g., target Tj < 150°C) to ensure longevity, especially for the motor drive switches under high ambient temperature.
III. Quantifiable Perspective on Scheme Advantages
Efficiency & Thermal Gain: Using VBE1105 (5mΩ) for the motor inverter versus a standard 10mΩ MOSFET can reduce conduction losses by approximately 50% at high currents, directly lowering heat sink requirements and improving efficiency, especially during low-speed, high-torque maneuvers.
Power Density & Integration: Employing VBGQA1304 in a DFN8 package for core power switching saves over 70% board area compared to a TO-220 solution, enabling more compact and potentially cheaper ECU designs.
Reliability & Functional Safety: The use of robust, automotive-suitable switches like VBA1101N for auxiliary functions, combined with proper protection, enhances system diagnostic coverage and fail-safe capability, contributing to ASIL compliance.
IV. Summary and Forward Look
This selection provides a holistic, optimized power chain for an EPS system, addressing the high-power muscle, the intelligent control core, and the auxiliary functions.
Motor Drive Level – Focus on "Ultra-Low Loss & Peak Current": Prioritize the lowest possible Rds(on) and robust packaging to handle torque demands efficiently.
Control Power Level – Focus on "Density & Clean Power": Use advanced technology (SGT) in miniature packages to ensure stable, efficient power for sensitive electronics.
Auxiliary Management Level – Focus on "Robust Versatility": Select cost-effective, robust switches that offer diagnostic capability and replace electromechanical components.
Future Evolution Directions:
Fully Integrated Motor Driver Modules: For highest power density, consider smart power modules that integrate the inverter bridge (MOSFETs), gate drivers, protection, and diagnostics into a single package.
Advanced Wide-Bandgap for Premium EPS: For systems targeting ultra-high efficiency or higher bus voltages (e.g., 48V), GaN HEMTs could be considered for the inverter stage to drastically reduce switching losses and enable higher control frequencies.
Enhanced Monitoring & Prognostics: Future devices with integrated current sensing and temperature reporting will further aid in predictive health monitoring of the EPS system.
Engineers can refine this selection based on specific EPS architecture (Column, Pinion, Rack type), motor voltage/peak power, required ASIL level, and packaging constraints.

Detailed Topology Diagrams

BLDC Motor Inverter Bridge Topology Detail

graph LR subgraph "Three-Phase Inverter Bridge for BLDC Motor" DC_BUS["DC-Link Bus
12V/24V"] --> PHASE_BRIDGES subgraph "Phase U Bridge Leg" U_HIGH["High-Side"] --> Q_UH["VBE1105
100V/100A"] Q_UH --> U_OUT["Phase U Output"] U_OUT --> Q_UL["VBE1105
100V/100A"] Q_UL --> GND_U end subgraph "Phase V Bridge Leg" V_HIGH["High-Side"] --> Q_VH["VBE1105
100V/100A"] Q_VH --> V_OUT["Phase V Output"] V_OUT --> Q_VL["VBE1105
100V/100A"] Q_VL --> GND_V end subgraph "Phase W Bridge Leg" W_HIGH["High-Side"] --> Q_WH["VBE1105
100V/100A"] Q_WH --> W_OUT["Phase W Output"] W_OUT --> Q_WL["VBE1105
100V/100A"] Q_WL --> GND_W end U_OUT --> MOTOR_U["Motor Phase U"] V_OUT --> MOTOR_V["Motor Phase V"] W_OUT --> MOTOR_W["Motor Phase W"] subgraph "Gate Drive System" DRIVER_IC["Three-Phase Gate Driver IC"] --> PRE_UH["Pre-Driver UH"] DRIVER_IC --> PRE_UL["Pre-Driver UL"] DRIVER_IC --> PRE_VH["Pre-Driver VH"] DRIVER_IC --> PRE_VL["Pre-Driver VL"] DRIVER_IC --> PRE_WH["Pre-Driver WH"] DRIVER_IC --> PRE_WL["Pre-Driver WL"] PRE_UH --> Q_UH PRE_UL --> Q_UL PRE_VH --> Q_VH PRE_VL --> Q_VL PRE_WH --> Q_WH PRE_WL --> Q_WL end MCU["FOC Control MCU"] --> PWM_GEN["PWM Generation"] PWM_GEN --> DRIVER_IC end subgraph "Protection & Sensing Circuits" SHUNT_U["Shunt Resistor U"] --> I_SENSE_U["Current Sense Amp"] SHUNT_V["Shunt Resistor V"] --> I_SENSE_V["Current Sense Amp"] SHUNT_W["Shunt Resistor W"] --> I_SENSE_W["Current Sense Amp"] I_SENSE_U --> ADC_MCU["MCU ADC"] I_SENSE_V --> ADC_MCU I_SENSE_W --> ADC_MCU TVS_DC["TVS Diode Array"] --> DC_BUS SNUBBER_RC["RC Snubber Network"] --> Q_UH SNUBBER_RC --> Q_VH SNUBBER_RC --> Q_WH end style Q_UH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_VH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px style Q_WH fill:#e8f5e8,stroke:#4caf50,stroke-width:2px

ECU Control Logic Power Path Topology Detail

graph LR subgraph "Control Unit Power Distribution Architecture" AUX_IN["Auxiliary Power Input
12V/24V"] --> INPUT_FILTER["Input Filter & Protection"] INPUT_FILTER --> PRE_REG["Pre-Regulator"] PRE_REG --> MAIN_SW_NODE["Main Switch Node"] MAIN_SW_NODE --> Q_MAIN["VBGQA1304
30V/50A DFN8
Rds(on)=4mΩ"] Q_MAIN --> CLEAN_PWR_BUS["Clean Power Bus"] CLEAN_PWR_BUS --> LDO_5V["5V LDO Regulator"] CLEAN_PWR_BUS --> LDO_3V3["3.3V LDO Regulator"] LDO_5V --> PWR_5V["5V Power Rail"] LDO_3V3 --> PWR_3V3["3.3V Power Rail"] PWR_5V --> GATE_DRV_PWR["Gate Driver Supply"] PWR_5V --> SENSOR_PWR["Sensor Supply"] PWR_3V3 --> MCU_PWR["MCU Core Power"] PWR_3V3 --> ADC_REF["ADC Reference"] subgraph "Power Management Control" PMIC["Power Management IC"] --> ENABLE_CTRL["Enable Control"] ENABLE_CTRL --> Q_MAIN_GATE["Gate Drive Circuit"] Q_MAIN_GATE --> Q_MAIN PMIC --> POWER_SEQ["Power Sequencing"] POWER_SEQ --> LDO_5V POWER_SEQ --> LDO_3V3 PMIC --> UVLO["Under-Voltage Lockout"] PMIC --> OVLO["Over-Voltage Protection"] PMIC --> OC_PROT["Over-Current Protection"] end MCU["Main Control MCU"] --> PMIC_COMM["PMIC Communication"] PMIC_COMM --> PMIC end subgraph "Gate Drive Power & Isolation" GATE_DRV_PWR --> BOOTSTRAP["Bootstrap Circuit"] BOOTSTRAP --> HIGH_SIDE_DRV["High-Side Driver Supply"] GATE_DRV_PWR --> ISO_PWR["Isolated Power Supply"] ISO_PWR --> LOW_SIDE_DRV["Low-Side Driver Supply"] subgraph "Three-Phase Driver System" DRIVER_U["Phase U Driver"] --> GATE_UH["Gate UH"] DRIVER_U --> GATE_UL["Gate UL"] DRIVER_V["Phase V Driver"] --> GATE_VH["Gate VH"] DRIVER_V --> GATE_VL["Gate VL"] DRIVER_W["Phase W Driver"] --> GATE_WH["Gate WH"] DRIVER_W --> GATE_WL["Gate WL"] end MCU --> PWM_SIGNALS["PWM Signals"] PWM_SIGNALS --> DRIVER_U PWM_SIGNALS --> DRIVER_V PWM_SIGNALS --> DRIVER_W end style Q_MAIN fill:#e3f2fd,stroke:#2196f3,stroke-width:2px style MCU fill:#fce4ec,stroke:#e91e63,stroke-width:2px

Auxiliary Load Management Topology Detail

graph LR subgraph "High-Side Auxiliary Load Switches" AUX_PWR["Auxiliary Power Bus"] --> SWITCH_INPUTS subgraph "Clutch Solenoid Control Channel" IN_CLUTCH["Clutch Control Input"] --> DRV_CLUTCH["Driver Circuit"] DRV_CLUTCH --> Q_CLUTCH["VBA1101N
100V/16A SOP8"] AUX_PWR --> Q_CLUTCH Q_CLUTCH --> CLUTCH_OUT["To Clutch Solenoid"] CLUTCH_OUT --> FLYBACK_D1["Freewheeling Diode"] FLYBACK_D1 --> GND_CLUTCH end subgraph "Cooling Fan Control Channel" IN_FAN["Fan PWM Control"] --> DRV_FAN["Driver Circuit"] DRV_FAN --> Q_FAN["VBA1101N
100V/16A SOP8"] AUX_PWR --> Q_FAN Q_FAN --> FAN_OUT["To Cooling Fan"] FAN_OUT --> FLYBACK_D2["Freewheeling Diode"] FLYBACK_D2 --> GND_FAN end subgraph "Diagnostic Load Channel" IN_DIAG["Diagnostic Control"] --> DRV_DIAG["Driver Circuit"] DRV_DIAG --> Q_DIAG["VBA1101N
100V/16A SOP8"] AUX_PWR --> Q_DIAG Q_DIAG --> DIAG_OUT["To Diagnostic Circuit"] DIAG_OUT --> GND_DIAG end subgraph "Spare Auxiliary Channel" IN_SPARE["Spare Control"] --> DRV_SPARE["Driver Circuit"] DRV_SPARE --> Q_SPARE["VBA1101N
100V/16A SOP8"] AUX_PWR --> Q_SPARE Q_SPARE --> SPARE_OUT["To Spare Load"] SPARE_OUT --> GND_SPARE end end subgraph "Protection & Diagnostics" subgraph "Inductive Load Protection" TVS_CLUTCH["TVS Diode"] --> CLUTCH_OUT TVS_FAN["TVS Diode"] --> FAN_OUT RC_SNUBBER["RC Snubber"] --> Q_CLUTCH RC_SNUBBER --> Q_FAN end subgraph "Current Monitoring" SENSE_CLUTCH["Current Sense"] --> CLUTCH_OUT SENSE_FAN["Current Sense"] --> FAN_OUT SENSE_CLUTCH --> ADC_IN["MCU ADC Input"] SENSE_FAN --> ADC_IN end subgraph "Fault Detection" OC_DETECT["Over-Current Detection"] --> Q_CLUTCH OC_DETECT --> Q_FAN OC_DETECT --> Q_DIAG OC_DETECT --> Q_SPARE OT_DETECT["Over-Temperature Detection"] --> Q_CLUTCH OT_DETECT --> Q_FAN OC_DETECT --> FAULT_OUT["Fault Output"] OT_DETECT --> FAULT_OUT FAULT_OUT --> MCU["MCU Interrupt"] end end subgraph "Control Interface" MCU --> GPIO_CLUTCH["GPIO Clutch Control"] MCU --> GPIO_FAN["GPIO Fan Control"] MCU --> GPIO_DIAG["GPIO Diagnostic Control"] MCU --> GPIO_SPARE["GPIO Spare Control"] GPIO_CLUTCH --> IN_CLUTCH GPIO_FAN --> IN_FAN GPIO_DIAG --> IN_DIAG GPIO_SPARE --> IN_SPARE end style Q_CLUTCH fill:#fff3e0,stroke:#ff9800,stroke-width:2px style Q_FAN fill:#fff3e0,stroke:#ff9800,stroke-width:2px
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