When using PMOS to control the on and off of a large capacitive load circuit, how can we achieve fast shutdown?

The conventional slow-start circuit (integrating capacitors at the gate-source to achieve slow turn-on) charges the PMOS tube gate slowly when turned off, which can easily damage the device under load.

By connecting a 10uF capacitor C2 in parallel between the gate and source to achieve slow start-up and adding a fast discharge control loop, the gate-source voltage can be quickly restored when shutting down, thereby achieving fast shutdown of the PMOS.

 Let's look at its detailed principle. When S1 is not enabled, there is no current in the b-pole of transistors Q2 and Q1, and Q2 and Q1 are not conducting. At this time, the gate voltage of the PMOS tube, the base and emitter of the transistor Q5 are all 60V, and the PMOS tube is not conducting.

When S1 is enabled, transistors Q1 and Q2 are turned on. At this time, the base of Q5 is 0V and the emitter is 40V. At this time, the PMOS is in the on state.

When S1 is disconnected, the base of the transistor is quickly charged to 60V under the action of R6. At this time, Q5 is turned on, and 60V directly reaches the PMOS gate through Q5, achieving rapid discharge. The discharge speed can be controlled by adjusting R6.

The following figure is a simulation diagram with gate discharge circuit added and gate and drain voltage waveforms. The green one is the gate voltage waveform and the red one is the drain voltage waveform.

 The figure below is the simulation diagram and waveform diagram without adding (disconnecting the emitter of Q5 transistor and the gate of PMOS), and the meaning of the waveform color is the same as the above figure.

 The simulation results show that after adding the gate discharge loop, the gate voltage rise time is greatly shortened, indicating that the circuit can achieve fast gate discharge of the PMOS slow-start circuit and accelerate shutdown.

 However, in actual debugging, after S1 is closed, the E pole voltage of Q5 is abnormal, and the EB pole voltage difference exceeds the rated value; we can add diode D1 and resistor R1 so that the E pole of Q5 can be pulled down to GND through D1 and R1 when S1 is closed.