Figure 1

As shown in Figure 1, when 1 is connected to a high level and 2 is connected to a low level, the gate G is at a low level, the source S is at a VCC high level, and the PMOS is turned on; when 1 is connected to a low level and 2 is connected to a high level, both the gate G and the source S are at a high level, the PMOS is not turned on, and the direction of the body diode is from the drain D to the source S, which is in the cut-off state.

Figure 2

As shown in Figure 2, when the Control terminal is connected to a low level, the transistor Q1 is not turned on. At this time, the source S and the gate G are both connected to a high level, and the PMOS is not turned on; when the Control terminal is connected to a high level, the transistor is turned on, the gate G is grounded through Q1 and becomes a low level, while the source S is still at a high level, and the PMOS (Q2) is turned on.