How to use PMOS to make an anti-backflow circuit?

Adding a control I/O port to control the opening can prevent backflow when actively shut down.

For example, this circuit is a two-way switch that can fully control on/off.

 Let’s see how it works:

When the control level is high , the NMOS of Q4 is turned on, and the G-pole potentials of Q2 and Q3 are pulled down to 0V.

The body diode of Q2 is turned on, the S-pole level of Q2 is VCC-0.7V, at this time the G-pole level is 0, and Q2 is fully turned on.

Here, the S pole of Q3 is connected to the S pole of Q2, and they have the same potential, both VCC.

At this time, the G electrode level is 0, which meets the turn-on condition. Q3 is also fully turned on, and VCC supplies power to the load normally.

Conversely, if VCC=0 and the load is a voltage source, it can also be turned on, except that the body diode of Q3 is turned on first, and then Q2.

When the control level is low, the circuit is completely shut down:

When the control level is low, Q2 and Q3 will be turned off, R2 will continue to pull up, keeping Vgs=0, and the two PMOS are in a completely off state.

However, this circuit also has a disadvantage, that is, it requires too many components and needs to connect two PMOS in series, which will affect the efficiency and cost of the load.

Some of the above pictures and information are from the Internet