How to calculate the power consumption of MOS tube? This article cannot be more detailed...

A friend asked me to write an article on how to calculate the power consumption of MOS tubes. Today, the editor of VBsemi will talk about the power consumption of MOSFET.

Usually when calculating MOSFET power loss, people will use a simple calculation formula: P=Id*Id*Rds(on), but this is only part of the MOSFET loss. How many parts does MOSFET power consumption include?

MOSFET power dissipation (PI)

It is mainly divided into three types: driving loss (Pdr), switching loss (Psw) and conduction loss (Pc). Switching loss (Psw) can be divided into turn-on loss, turn-off loss and reverse recovery loss of diode.

 Today we will first look at the MOSFET turn-on process

When the MOSFET of this upper tube is turned on, the output voltage changes from 0 to UDr, and this time constant is determined by the product of Rg and Ciss (input capacitance) . The output will not change until the gate voltage reaches UGS. (ID=0A, UDS=UDD).

When the gate voltage reaches UGS(th), iD starts to rise. During this current rise time, the freewheeling diode is still turned on and the drain-source VDS voltage is UDD.

We need to turn this diode off , which means removing all the minority carriers stored in it.

This reverse recovery current will be absorbed by the MOSFET, causing additional power losses. The worst-case values of this reverse recovery charge (Qrr) and duration (trr) are used in the power loss calculation.

 When the diode is turned off, the drain-source voltage drops from UDS=UDD to its on-state value. After the Miller effect occurs, the gate-source voltage is clamped at UGS=U.

The slope of the drain-source voltage is determined by the gate current and the gate-to-drain capacitance (CGD=Crss).

In order to calculate the voltage fall time (tfu) with reasonable accuracy, the nonlinearity of the gate-drain capacitance must be taken into account. This nonlinearity is difficult to incorporate into engineering calculations. That is why the two-point approximation is used.

Assuming that the drain-source voltage is in the range uDS∈[UDD/2,UDD], the gate-drain capacitance is CGD1=CGD(UDD).

On the other hand, if the drain-source voltage is in the UDS range ∈ [0V, UDD/2], the gate-drain capacitance is CGD2 = CGD.

 The drain-source voltage during the fall time is shown as a dotted line in Figure B, because this approximation is only used to determine the UDS voltage fall time (and the rise time of UDS during the turn-off period). It is assumed that the drain-source voltage can be used in a linear form (solid line in Figure B).

 Some of the above pictures and information are from the Internet