In actual circuit applications, current backflow may occur sometimes. Today we will share three PMOS anti-backflow circuits.

 Let's look at this circuit: the control signal G_CTRL controls VB4.2+ to supply power to VCC_OUT.

 Here, the source and drain terminals are not connected in reverse. The function of resistor R2 is to control the gate current so that it will not be too large, and R3 controls the normal state of the gate.

When R3 is pulled high, Pmos is turned off.

This circuit can also be seen as a pull-up for the control signal. When the pin inside the MCU is not pulled up, the output is open drain and the PMOS cannot drive it off.

Then an external voltage pull-up is required, and R3 plays two roles at this time.

Second circuit:

 This circuit can not only prevent backflow, but also realize anti-reverse connection protection function.

When the power supply is connected in reverse, the PMOS does not conduct and the subsequent circuit is disconnected.

A voltage regulator is added here to protect the MOS tube.

In addition to the above two circuits, in practical applications we can also connect two MOS tubes to prevent backflow back to back.

 When the control terminal is at a high level, transistor Q9 is turned on, the gates of Q3 and Q4 are pulled down to 0V, Q3 is turned on through the body diode, and then Q4 is turned on, and the load end obtains the Vin voltage.

When the control terminal is at a low level, transistor Q9 is disconnected, Q3 and Q4 are not conducting, and are completely turned off. Since the body diodes of 3 and Q4 are connected in series in reverse, they are blocked in either direction, thus achieving backflow prevention.

Note though, this circuit may require an IO to control.