Sharing a circuit situation that Microbee saw online

 Is it easy to drive PMOS? Why does it take so long to turn off?

 Share a circuit situation that Microbi saw on the internet.

 When driving a PMOS at 100kHz, the voltage signal at the G-pole of the PMOS is not a pulse wave, and the PMOS is always in a linear amplification state and cannot be turned off.

 So the circuit was modified by replacing the signal driving the triode with DC, and the PMOS turned on normally, but this was with a completely low-frequency DC drive.

So change the triode to NMOS, PMOS still did not turn off, change the frequency of the driving pulse to 10k, and finally found that the PMOS turn-off time is too long.

 Why is the turn-off time of PMOS so long?

 When the PMOS is turned on, the junction capacitor voltage needs to fall, that is, the capacitor for reverse charging, in the shutdown PMOS needs to junction capacitor charging, at this time the junction capacitor is no fast discharge circuit, the junction capacitor only through the resistor R12 will be discharged after the gate voltage can rise, which is why the shutdown time is long!

 That is to say, when designing the circuit, the PMOS gate must be high when it is first powered on, so that the PMOS can avoid turning itself on.

 For example, in this circuit, Q1 conducts to charge the junction capacitor when it is turned off, and Q1 cuts off when pulse V4 is high, and the junction capacitor of the PMOS forms a charging loop through the power supply V3 , D2 , R2 and Q2.

 Thus, the turn-off delay is gone, but the turn-on speed is still very slow, so can the value of R2 be further reduced?

 If the value of R2 is reduced, a large current will flow through resistor R2 and M1 (MOSFET) during steady state, which can easily lead to damage to the regulator.

 What about using a totem pole driver?

 This circuit opens using the instantaneous conduction of Q2 to realize the junction capacitor reverse charge, at which time the R1 voltage instantly becomes about 10 V. Q2 conduction.

 At the moment of shutdown, Q1 conduction, the junction capacitance through Q1 quickly release the charge, realize the drive.

 Although the realization of the PMOS drive, but there is still a problem here, that is, the drive voltage is seriously dependent on the supply voltage, if the supply voltage is lowered, the PMOS Vgs differential voltage will also become lower, does anyone know of a better way?

 We will continue to talk about PMOS drive circuits in the next installment.

Some of the above pictures and information are from the Internet